Verilog Lab. Two s Complement Add/Sub Unit. TA: Xin-Yu Shi
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1 Verilog Lab. Two s Complement Add/Sub Unit TA: Xin-Yu Shi genius@access.ee.ntu.edu.tw
2 Introduction In previous lecture, what you have learned : Complete representation for binary negative number Arithmetic operation of binary number Skills to deign combinational circuits Basic concept and syntax in Verilog-HDL In this lab, we ll guide you to model a combinational add/sub unit with gate-level Verilog HDL SILOS : Verilog design / debug / simulation IDE Logic Design Xin-Yu Shi, 11/24/2006 pp. 2
3 Guideline 1. Analyze specified function, divide problems into sub-problems and conquer them one by one 2. Figure the architecture 3. Coding 4. Simulation Logic Design Xin-Yu Shi, 11/24/2006 pp. 3
4 Block Diagram Logic Design Xin-Yu Shi, 11/24/2006 pp. 4
5 Input/Output Description Input signals operand_a, operand_b: signed 4-bit integer mode: select the operation 0: result = operand_a + operand_b 1: result = operand_a operand_b Output signals result: signed 4-bit integer Logic Design Xin-Yu Shi, 11/24/2006 pp. 5
6 Two s Complement (1/2) [N] 2 = 2 n (N) 2 EX:2 s complement of (N) 2 = ( ) 2 [N] 2 = [ ] 2 = 2 8 ( ) 2 = ( ) 2 ( ) 2 = ( ) 2 EX:show that (N) 2 + [N] 2 = (carry) [N] 2 = - (N) 2 Logic Design Xin-Yu Shi, 11/24/2006 pp. 6
7 Two s Complement (2/2) Convert (N) 2 to [N] 2 : 1 0 a k a k, then add N = complement each bit 1 add Logic Design Xin-Yu Shi, 11/24/2006 pp. 7
8 Unsigned Adder Unsigned addition by carry ripple adder (CRA) Implement with 1-bit full adders For N-bit addition, each bit: Sum i = 1, if the number of 1 in {a i, b i, carry i-1 } is odd Carry i = 1, if the number of 1 in{a i, b i, carry i-1 } is equal to or more than 2 Logic Design Xin-Yu Shi, 11/24/2006 pp. 8
9 Implement Add/Sub with Unsigned Adder Divide and conquer add subtract Identical: signal connection module instance Logic Design Xin-Yu Shi, 11/24/2006 pp. 9
10 Architecture Design Share the 4-bit carry ripple adder For subtract, inverse b 3 ~b 0 and add 1 from carry in a 3 b 3 a 2 b 2 a 1 b 1 a 0 b 0 mode carry out FA 3 FA 2 FA 1 FA 0 result 3 result 2 result 1 result 0 operand_b i = mode b i Logic Design Xin-Yu Shi, 11/24/2006 pp. 10
11 Lab Procedures Please follow the steps to build the dual-mode adder hierarchically. 1. Download the Verilog source code files from: t/veriloglabsource.zip 2. Complete/modify the source code 3. Simulate by SILOS Logic Design Xin-Yu Shi, 11/24/2006 pp. 11
12 1. Full Adder Gate-Level Model Please complete the Verilog code of 1-bit full adder. (FA_1bit.v) Fill in the necessary code (Please only use AND/OR gate) Logic Design Xin-Yu Shi, 11/24/2006 pp. 12
13 2. Carry Ripple Adder Model Debug the Verilog code of 4-bit carry ripple adder. (CRA_4bit.v) Logic Design Xin-Yu Shi, 11/24/2006 pp. 13
14 3. Add/Sub Unit Model Complete the Verilog code of the add/sub unit (Add_Sub_Unit.v) Fill in the necessary code Fill in the necessary code Logic Design Xin-Yu Shi, 11/24/2006 pp. 14
15 4. Testbench Please complete the module instance in testbench. (tb_add_sub_unit.v) Fill in the necessary code Logic Design Xin-Yu Shi, 11/24/2006 pp. 15
16 Simulation using SILOS
17 Create new project Write your Verilog design code Create a new project: Project -> New -> (enter your project name) Include your verilog file(s): (choose your.v file) -> (click Add bottom) -> (click OK) Note that testbench should be included Then run and debug Logic Design Xin-Yu Shi, 11/24/2006 pp. 17
18 1. Select Verilog source file/testbanch 3. Click OK file 2. Add to project Type project name Logic Design Xin-Yu Shi, 11/24/2006 pp. 18
19 Run Run and Debug Press F5 or click the GO icon on toolbar An output window is generated to show whether there exists errors. Debug Press F6 then click the Open explorer icon on toolbar Choose signals you want to watch Click right button and select Add signal to analyzer Then you can debug with waveform Logic Design Xin-Yu Shi, 11/24/2006 pp. 19
20 Press Go (F5) Note if there is any warning or error Logic Design Xin-Yu Shi, 11/24/2006 pp. 20
21 1. Drag the signal you want to observe 3. Observe the waveform 2. Drop here Logic Design Xin-Yu Shi, 11/24/2006 pp. 21
22 Questions (1/2) Please write Verilog codes for dual-mode 8-bit Add/Sub circuit design. (Similar to the architecture on p.10) Download the needed Verilog codes (including test-bench & template files) from : eriloglabquestion.zip Please write your whole design in only one Verilog file. (You can concatenate all the modules in only one file.) Deadline : to genius@access.ee.ntu.edu.tw before 2:00 PM 12/08. Logic Design Xin-Yu Shi, 11/24/2006 pp. 22
23 Questions (2/2) Naming rule : For the student with student number of B , the hand-in file should be B v; otherwise, the grade will be empty. Template Code for Top Module : Logic Design Xin-Yu Shi, 11/24/2006 pp. 23
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