Elec 326: Digital Logic Design

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1 Elec 326: Digital Logic Design Project Requirements Fall 2005 For this project you will design and test a three-digit binary-coded-decimal (BCD) adder capable of adding positive and negative BCD numbers. The goals of this assignment are to: 1. Gain experience with modern CAD techniques used to design digital systems. 2. Gain experience with designs that require ad hoc design techniques. 3. Learn to test projects with simulation. 4. Learn to download projects to an FPGA board and perform physical testing. 5. Learn about BCD addition and subtraction. 1. Project Behavioral Specification The BCD adder you design must be capable of adding two three-digit BCD operands to produce a three-digit sum. Each of the two operands can be either positive or negative, so the adder must, in effect, be capable of both addition and subtraction. The operands and sum are represented by 13-bit binary vectors where 12 of the bits are the three 4-bit BCD digits and the 13-th bit is a sign bit (0 if the number is positive and 1 if it is negative). This is essentially a sign-plusmagnitude representation where the magnitude is represented with the BCD code. The adder should also have a one-bit overflow output signal that is 1 if the addition results in an overflow (a magnitude that is too big to be represented with 3 BCD digits) and 0 otherwise. BCD codes and arithmetic are discussed in Section of the Brown and Vranesic book. 2. Project Organization The adder is to be organized as three identical digit-adders connected in a ripple-carry configuration. Each of the digit-adders will be capable of adding two 4-bit BCD digits and a 1- bit carry/borrow input to produce a 4-bit BCD sum and 1-bit carry/borrow output. The adder should implement the following general algorithm: 1. The adder checks the signs and relative magnitude of the two operands. 2. If signs are the same, the adder adds the operands and makes the sign of the result equal the signs of the operands. Project 1 Elec 326

2 3. If the signs differ, then the adder compares the magnitudes of the operands, subtracts the smaller from the larger, and sets the sign of the result equal to the sign of the larger. Note that if the result is 0, the sign of the result must be positive (0 sign bit). Block Diagram A high-level block diagram for the project is given in the following figure. It shows the main data flow paths that connect the modules, but does not show the signals that connect to the control unit. That module will need inputs from the other modules and will generate control signals for all the modules. Part of the project assignment is to figure out what these control signals should be. The block diagram also shows how the switches and displays on the FPGA board are used. The remainder of this section describes the behavior of the modules in this diagram. Project 2 Elec 326

3 DIGITADD: This is a digit adder that takes two 4-bit BCD numbers and a carry/borrow input and produces a 4-bit BCD sum or difference and a carry/borrow output. SSCTLR: This is the seven-segment display controller. It takes three 4-bit BCD numbers and displays them in the right three digits of the display. It also displays the sign in the leftmost digit Project 3 Elec 326

4 position. The sign digit should turn on only the middle segment (minus sign) when the result is negative. When the result is positive, all segments on the fourth digit should be off. REGUNIT: This module contains two 4-bit registers that hold the input operands for the DIGITADD module. There are not enough switches on the FPGA board to bring each input digit from a switch, so BCD input digits must be entered sequentially, one at a time, into the REGUNIT registers. This unit is also responsible for swapping the operands when necessary because the available adders can only subtract the B input from the A input, not the other way around. It is also convenient to add logic to the REGUNIT to determine which of the input operands is larger (needed to determine if the operands must be switched). The logic for this should be designed so that when several REGUNIT modules are connected in series, they will determine which of the 3-digit BCD numbers is largest (or whether they are equal). CTLUNIT: This module takes information from the other modules and generates the control signals for those modules. It must check the signs and magnitudes of the operands and decide whether to do an addition or subtraction and whether to swap the operands. It is also responsible for computing the sign of the result. SWITCHES & DISPLAYS: Operands are entered through five toggle switches (4 for the magnitude and 1 for the sign). The 4-digit, seven segment display shows both the sign and magnitude of the result. One LED is used to indicate an overflow. One toggle switch (ABSEL) indicates which of the two operands (A or B) is being loaded. Another toggle switch (SHOWREG) indicates whether the output display shows the value stored in one of the operand registers or the output of the adders. If a register operand is displayed, the ABSEL switch determines which one. One pushbutton switch clears all the registers to 0. Another pushbutton causes the next digit to be loaded in the registers. 3. Project Implementation This section gives some more detailed information about how to implement the modules in the block diagram above. Each of the modules should be implemented as a schematic and as a Verilog module. Create a symbol for that schematic to use in other, higher level schematics. You will also probably find it necessary and convenient to implement each of the major modules in the block diagram as an interconnection of smaller modules represented by their own symbols. DIGITADD Probably the best way to implement the digit adder is by first doing a binary addition/subtraction and then correcting the sum, if it is outside the range of valid BCD digits (e.g., greater than 9). The correction can be implemented by adding a correction value to the intermediate result produced by the first addition/subtraction. You can implement this with a 4-bit binary adder/subtractor to do the first addition/subtraction and another binary adder to perform the correction. You must determine when to do the corrections and what correction values to add. You will need logic to generate the correction value. REGUNIT Project 4 Elec 326

5 You should implement the registers in this module so that when the three REGUNIT modules are connected together, the three A operand registers form a 4-bit wide shift registers and the three B operand registers form another shift register. These shift registers should shift from the least significant digit to the most significant digit. Connect four of the data entry toggle switches to the least significant position of both of these shift registers and use the ABSEL switch to determine which shift register is actually loaded (and shifted) when the LOAD pushbutton is pushed. You can use multiplexers on the outputs of the registers to swap the two operands. It is also possible to implement the feature that switches the output display from showing the result of the addition to showing the values stored in the registers by observing that adding 0 to a number does not change it. The logic that checks the relative magnitudes of the operands should take information from the comparison logic in the previous REGUNIT module and produce output signals that represent the result of comparing all digits through this position. These output signals are then passed to the next REGUNIT module. The output signals of the comparison logic in the last REGUNIT module indicate which of the full 3-digit operands is largest (or whether or not they are equal). SSCTLR Each digit on the seven-segment display is controlled by a signal connected to the anode of all the diodes in that digit. The signal must be low for any of the diodes to light. Individual diodes in a digit light when their anode is low and their cathode is also low. Note that this is different from what the Digilent manual for the DIO4 board says and what you would expect from the way diodes work. Indeed, a diode s anode must be high relative to its cathode in order for it to light. It appears that there is logic on the board that effectively inverts the anode signals. The four digits share the eight cathode input signals. For example cathode input signal CA is connected to the cathode of segment A on all four digits. Therefore, to light a segment on a digit, you must set the cathode signal corresponding to that segment low and also set the anode for that digit low. To display a BDC value on a digit of the display, you must set all the cathode inputs low for the segments that are lit for that value when the anode input for that digit is low. The SSCTLR module must have logic that will cycle through the digits while making sure that the cathode inputs are in sync with the anode signals. For additional information of how these displays work, refer to the Digilent DIO4 manual downloadable from their web site. The leftmost digit must display the sign, not a BCD digit. To implement this, you will need to use two of 4-bit patterns not used to represent BCD digits. That is, use patterns for binary numbers greater than 9 and less than 16. It is a good idea to use the following submodule inside the SSCTLR module. You can then add the necessary logic to cycle through the digits to get the complete module. Project 5 Elec 326

6 SSCONV: This is submodule of SSCTLR that does the conversion from a 4-bit input representing a BCD digit (or sign) to the seven outputs that control the cathodes of the seven segment display. To complete the implementation of the SSCTLR module you need to add logic that takes three 4-bit BCD input digits and a sign bit and selects them one at a time in a fixed order. At the same time it must activate the digits on the seven segment display (set there anodes low) in such a way that they are in sync with the selection of input digits. CTLUNIT This module must contain two flip-flops to hold the signs of the two operands. One of these should be loaded with the value of the sign switch every time the load button is pushed. The ABSEL switch determines which one to load. The module must also contain logic to use the signs of the two operands and the result of the magnitude comparison of the operands to compute the sign of the result and to tell the DIGITADD modules whether to add or subtract. 4. Assignments The project consists of four assignments, each with its own deadline and requirements. This section gives the details for these assignments. The first assignment is a lot easier than the other three. The main goal of that assignment is to learn to use the design tools and the FPGA boards. Assignment #1: Design of the SSCONV module For this assignment you are to design and test the SSCONV module used to convert BCD numbers to the seven segment code. This module will be used in the SSCTLR module in a later assignment. Complete the following steps: 1. Derive expressions for each of the cathode signals in terms of the four-bit BCD digits. Then write a behavioral Verilog module to realize these expressions. Verify the correctness of your module by simulation. 2. Realize the module as a schematic using gate symbols from the library. Then simulate the schematic and compare the results to those obtained in step 1 above. 3. You do not need to prepare a report for this assignment. 4. Go to the lab and download your design to an FPGA board. In your configuration file, connect the outputs of your circuit to one of the digits of the seven segment display. Have a lab assistant check your work. Assignment #2: Design of the DIGITADD module For this assignment you are to design and test the DIGITADD module using the following approach: 1. Develop an algorithm for BCD addition and subtraction and write a behavioral Verilog module to implement this algorithm. Test the algorithm for correctness by simulating the Verilog module. You should use high-level Verilog operations rather than binary logical Project 6 Elec 326

7 operations or gate instantiations. For example, use the + operations for addition; don t do addition by simulating a hardware adder using the logical operations (AND, OR, NOT, XOR, etc.). Use always statements, conditional operations (IF, CASE etc.), and comments to make it easy for the reader to understand your algorithm. 2. Realize the module as a schematic using the built-in adder and adder/subtractor symbols from the library. Write a Verilog module for the combinational part of the BCD correction logic, create a schematic symbol for it, and use it in the DIGITADD schematic. 3. Simulate the schematic and compare the results to those obtained in step 1 above. 4. Prepare an interim report for the DIGITADD module designed in this assignment conforming to the requirements in Section 5 (Project Report) below. Include all parts except the project description. This includes Verilog code, schematics, test results from this assignment, and a summary of resource usage and timing parameters. Include a block symbol for DIGITADD showing all input and output signals with signal names. 5. Go to the lab and download your design to an FPGA board and have a lab assistant check it. Also, submit the interim report. Assignment #3: Design of the REGUNIT module For this assignment you are to design and test the REGUNIT module. Then combine it with the DIGITADD module from assignment #2 to create a new module called REGADD. Complete the following steps: 1. Write a behavioral Verilog module for the REGUNIT module. Verify the correctness of this design by simulation. 2. Realize the module as a schematic using built-in symbols from the library to simplify the drawing. You will find it convenient to break this schematic up into several smaller schematics and use symbols for these in the top-level schematic. 3. Simulate the schematic and compare the results to those obtained in step 1 above. 4. Integrate the schematics for the DIGADD and REGUNIT modules into a single schematic called REGADD that contains symbols for each of these modules. 5. Simulate the REGADD schematic from part 4 to verify their correctness. 6. Augment the report from assignment #2 with the Verilog code, schematics, test results, resource usage, and timing parameters from this assignment. Include a block symbol for REGUNIT and one for REGADD showing all input and output signals with signal names. 7. Go to the lab and download your design to an FPGA board and have a lab assistant test it. Also, submit the interim report. Assignment #4: Design of the CTLUNIT and SSCTLR modules and Integration of all modules For this assignment you are to first design and test the SSCTLR module using the SSCONV module designed in assignment #1. Then you are to design the CTLUNIT module and combine it with the SSCTLR module and three copies of the REGADD module to realize the full BCD adder. Project 7 Elec 326

8 1. Write a Verilog module for the SSCTLR module using an instance of the SSCONV module from assignment #1. Verify the correctness of this design by simulation. 2. Realize the SSCTLR module as a schematic using built-in symbols from the library and a symbol for the SSCONV module from assignment #1 to simplify the drawing. 3. Simulate the schematic from step 2 and compare the results to those obtained in step 1 above. 4. Write a Verilog module for the CTLUNIT module and verify its correctness by simulation. 5. Realize the CTLUNIT module as a schematic using library symbols and lower-level combinational Verilog modules as appropriate. 6. Simulate the schematic from step 5 and compare the results to those obtained in step 4 above. 7. Design a schematic that combines the CTLUNIT with three copies of the REGADD module from assignment #3 and the SSCLTR module to get a realization of the full BCD adder. Call this top-level schematic BCDADD. You may want to first create a schematic and symbol for REGADD in order to fit the final schematic on one page. If so, name this schematic and symbol ADD3. 8. Simulate the schematic from step 7 to verify its correctness. 9. Write a Verilog module for the full BCD adder by using instances of the Verilog modules designed previously. 10. Simulate the Verilog module from step 9 and compare the results to those from step Augment the report from assignment #3 with the Verilog code, schematics, test results, resource usage, and timing parameters from this assignment. Include a block symbols for all modules showing all input and output signals with signal names. 12. Go to the lab and download your design to an FPGA board and have a lab assistant check it. Also, submit the interim report. Project 8 Elec 326

9 Clocking Design the adder so that all flip-flops and registers are clocked by the same system clock signal. On the FPGA board this is the 50 Mhz clock available on pin 182. Do not gate the clock signal before sending it to flip-flops and registers. Do not use the pushbutton on the FPGA board to generate clock signals except possibly for testing. This restriction on the use of clock signals is probably not necessary in small systems that do not need to run at a high clock frequency, such as this project. However, there are many systems where this restriction is necessary and many more where it can simplify the design and avoid subtle timing problems. Therefore, it is a good idea to adapt this approach in all your designs unless there is a significant reason not to. 5. Project Reports This section gives a detailed description of the format you are to use in preparing project reports. It is expected that you will follow this format closely. Departures from it may result in points deducted from your grade. General Report Organization The final project report must contain the following sections arranged in the order given below: 1. A title page 2. A written description of the project (not required for the interim reports) 3. A section for each of the main modules DIGITADD, REGUNIT, SSCTLR, and CTLUNIT in that order. For each of these sections, include the following in the order given. a. Symbols for the module and any submodules you created to design the module. b. All Verilog code for the module. c. All schematics for the module d. A representative set of simulation waveforms used to test the module. e. A summary of resource usage and timing parameters for both the Verilog and the schematic versions of your design. All reports must be typed and all documentation must be computer generated to the extent possible. In a few cases it may be necessary to write some information by hand, but that should not be done unless absolutely necessary. In all such cases the information must be neatly and carefully printed so that it is easy to read. The remainder of this document will give the detailed requirements for each of these sections. Title Page The title page should be a single page with only the following information: 1. Course number (Elec 326) Project 9 Elec 326

10 2. Project title 3. Your name 4. The date the project is submitted Layout the page with this information on four different lines in the order given and centered on the page. Use a font size of at least 18 points. Project Description This section should describe your design. It should provide the reader with information he or she would need to understand how the circuits work and how you designed them. It should contain the following clearly labeled subsections: 1. Introduction: This is a brief (usually one or two paragraphs) statement of the purpose of the project. It should be written in general terms without giving details. It should be written as if the circuits you design were to be a product or part of a larger product. Do not give any implementation details (e.g., how many gates were used) or go into the details of how you designed the circuits. Just talk about what the circuit does in general terms. Note that this section can be very similar to the first section of this document, (Project Specification), but it should be written as a finished product description, not as an assignment of something to be done. 2. Theory of operation: Explain how your circuit works, but do not give implementation details. This should be an expanded version of the introduction. That is, give a high level description of what your circuits do and how they do it. For example, you could explain any algorithms you implemented, any conditions or restrictions the user must observe to use the circuits (e.g., apply only BCD numbers), and the high level structure of your circuits at the block diagram level. This section can be very similar to the description of the block diagram given above, and you may include a block diagram similar to this one. 3. Design details: This subsection is where you can go into the details of your design. It should contain any logical expressions you use, any Karnaugh maps or algebraic simplifications you performed, and any tables or state diagrams for sequential circuits. It should explain these design techniques if they are not self-explanatory. It should refer to the detailed documentation (such as logic diagrams and VERILOG programs) explicitly. This section should also contain a description of any unusual problems you had and how you solved them and any aspect of your design that is novel. 4. Testing details: Most circuits are too large to test them by applying all inputs. You have to choose a subset that will do a good job of verifying that the circuits work. For those projects, this subsection should explain why you chose the test sequences you used and why you think they are sufficient. VERILOG Code Project 10 Elec 326

11 This section should contain a listing of all the VERILOG code you simulated in this project. The code should be commented and easy to read. Put the following information as comments at the beginning of each VERILOG description: Project title Title for the module Your name and your partner s name Date of the code was printed Logic Diagrams All logic diagrams should be prepared with the Xilinx schematic editor and printed for inclusion in the report according to the following rules: 1. Print each circuit on one or more 8.5x11 pages of paper in landscape orientation (i.e, width greater than height). You will probably need to tell the Xilinx schematic editor to use a larger size in order to fit you logic diagram on the pager. When you print it, use the Windows print commands to reduce it to the required size. 2. Put the following information in the lower, right corner of each page using 18 pt font: Project Title Title for the logic diagram Your name and your partner s name The date last modified. 3. Make sure all input and output connectors are labeled with the proper signal name. Add labels for any interior signals that appear in the written description of the circuit, especially those that appear in logical expressions. 4. The exact placement of parts and wires on the diagrams is not critical. However, you should use the following common guidelines. Circuit inputs should be on the left side of the page and circuit outputs on the right side so that information flow is from left to right across the page. Orient all parts so that information flows from left to right through the part. Layout parts so the information flows from left to right from one part to another, to the extent possible. Draw wires either vertically or horizontally (no diagonal wires) and minimize wire crossings as much as possible. Testing results This section contains a representative sample of the results of the testing you did to confirm that your circuits work properly. This primarily consists of the waveforms generated by the simulation of the VERILOG code and logic diagrams. These tests should be explained in the project description section, which should explicitly refer to the test data in this section. For that purpose, the data from each test must be labeled or numbered and the project descriptions should Project 11 Elec 326

12 refer to these labels. To this end, put the following on each item in this section: The project title Title or label for the test (e.g., Test 1: Test of overflow circuits) Your name and your partner s name Date the test was run. Put this information in a box in the lower right corner of the waveform diagrams. You do not need to include all of your test results. Only include a representative sample of test waveforms. These samples should give an example of all of the operations the module is supposed to perform, but you do not need to include all of the tests you performed to confirm this. In the description of the testing, you should include a brief summary of the full set of tests. For example, you may have tested the DIGITADD module with 40 different combinations of numbers or more. You should then pick out a few of these that show the unit can do addition and subtraction and that it produces a carry out and uses the carry in properly. You should be able to do this in one to three waveform pages. In the project description you can say how many total tests you performed and explain what features the included waveforms test. Resources used and timing parameters The resource usage should list the number of slices, LUTs, IOBs, and Flip-flops used in the design. The timing parameters should include all relevant parameters such as minimum clock period, global setup time, global hold time, global delay, and I/O delay (combination delay from input to output terminals). 6. Project Procedures For each assignment the instructor will assign lab groups consisting of two students. If the number of students is odd, there will be one group of three students. These lab groups will be different for each of the four assignments. The lab groups will be determined randomly and will be posted on the course web site. After each assignment, each member of the lab group should make his or her own copy of all the work done on that assignment to take it on to the next assignment. For assignments 2, 3 and 4, the two members of a lab group will have different designs for the project up to that point. The group is free to select either one of these or can combine features of each and then proceed to augment it with the current assignment. After the fourth assignment is completed, each student is to take the documentation of the project at that point and augment it will the project description section specified in Section 5 (Project Reports) to get a final report. Therefore, every student will turn in an individual report containing all of the work done on the individual assignments plus a project description written without collaboration with any one else. 7. Project Deadlines and Grades The following table gives the deadlines for the four project assignments and the final report. Project 12 Elec 326

13 Assignment #1 Tuesday, 9/27/05, 5:00pm, in AL A126 Assignment #2 Thursday, 10/13/05, 5:00pm, in AL A126 Assignment #3 Tuesday, 11/1/05, 5:00pm, in AL A126 Assignment #4 Tuesday, 11/22/05, 5:00pm, in AL A126 Final Report Thursday, 12/1/05, 5:00pm, in DH 3029 To get full credit for an assignment, it must work and the documentation must be complete by the date given above. A lab assistant will verify this in the lab during a regularly scheduled lab day. If the assignment or documentation is incomplete, the lab assistant will make an assessment of the percentage complete and scale that grade for that assignment by this amount. If there are errors or omissions on the documentation, it will be considered incomplete. You must fix any errors or omissions in the documentation before including it in the final report. The whole project (including documentation) is worth 100 points. These points will be distributed as follows: Assignment #1: Assignment #2: Assignment #3: Assignment #4: Final Report: 10 points 20 points 20 points 30 points 20 points 8. Outcomes Evaluated The project evaluates student performance relative to the following course objectives & outcomes: Outcome 3: Design of combinational circuits Outcome 4: Design of sequential circuits Outcome 5: Design of combinational & sequential circuits using PLDs Outcome 6: Specification of digital system behavior using an HDL (Verilog) Outcome 7: Prepare documentation Project 13 Elec 326