ECE2029: Introduction to Digital Circuit Design. Lab 2 Implementing Combinational Functional Blocks

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1 ECE2029: Introduction to Digital Circuit Design Lab 2 Implementing Combinational Functional Blocks Objective: In this lab exercise you will simulate, test, and download various digital circuits which implement some common combinational functions like an adders and a two's complement circuit. You will again simulate and implement your circuits completely using Verilog code. Pre-lab Assignment: This pre-lab assignment is to be completed by each students before your lab session and must be signed-off by the TA during your lab session. Pre-labs help you to become oriented to the problem before you enter lab, help complete your design in advance and prevent wasting time in lab. Include the signed pre-labs for both team members in your report. 1) READ the whole lab assignment! 2) A full adder, as we discussed in class, is a circuit that adds 2 bits A and B plus any possible Carry from a less significant bit. For the full adder block diagram below: a. Refer to the posted notes from Lecture 4 for the truth table for a Full Adder. Write out the full Sum of Products (i.e. full sum of minterms) expressions for Cout and Sum. Also write out the full Product of Sums expressions for for Cout and Sum (you may use sigma and pi notation). b. Using a Karnaugh Map, find minimized expressions for Cout and Sum. Cin Cout Full A Adder Sum B Figure 1 3) Using the block diagram of the one bit full adder shown above, draw a schematic showing how you would implement a 4 bit adder which could add any two 4-bit binary numbers like A 3 A 2 A 1 A 0 + B 3 B 2 B 1 B 0 S 3 S 2 S 1 S 0 using four full adders. Be sure to label all inputs and outputs and show how the carry out of each less significant bit becomes the carry in of the next more significant bit (but carry-in of the LSB is always 0).

2 4) Write out a Boolean expression for detecting OVERFLOW in addition of two 4-bit signed numbers. OF_S = 5) Write out a Boolean expression for detecting OVERFLOW in addition of two 4-bit unsigned numbers. OF_U = Lab Assignment: In this lab you will impement your Full Adder design and then you will use your 1-bit adder to implement a 4-bit adder. Refer back to the Lab 1 tutorial for detail on creating new projects, adding sources, performing simulations, etc. 1. Open Vivado and create a new project correctly setting the target FPGA properties as you did in Lab 1. Add a new Verilog source module and call it fulladd.v. 2. Fill out the Port-assignment Wizard according to figure below with inputs A, B and Cin and outputs Sum and Cout. Remeber that Verilog, like C, is case sensitive and A is considered a different variable from a. Vivado will generate the Verilog module shell with those inputs and outputs declared. REMEMBER TO FILL IN THE COMMENTS BLOCK with your name(s) and a brief description of the module!!

3 You will need to add the assign statements to implement your full-adder expressions for Cout and Sum. In Verilog the Boolean operations are written as & for AND, for OR, ~ for NOT and ^ for XOR. 3. Unlike most calculators and many software programming languages there is NO implied order of operations among the BOOLEAN operators in Verilog. You must enforce order of operations with ( ). Ex: F = (A B' + C)' + A'C // Verilog assignment for F assign F = (~((A & (~B)) C)) ((~A) & C); Implement the Verilog assignment statements for the expressions you generated for Cout and Sum in the module and save. 4. Drawing on the contraints file from Lab 1 as an example, add a contraints (.xdc) file to your project that assignes inputs A, B and Cin to switches SW0, SW1 and SW2 respectively and assigns outputs Sum and Cout to LEDs LD0 and LD1 respectively. The constraints file is stored in a directory called something like "proj_name/proj_name.srcs/constrs_1". Below is this directory structure for my lab 1 project. Note that I run Linux but you will see a similar directory stucture in Windows Explorer for your lab 1 project directory. 5. Run Synthesis. You should see no errors.

4 6. Add a source for simulation to implement a full-adder test bench (as you did in Lab 1). Add Verilog to instantiate your fulladd module as U1 and apply test inputs for all possible input combinations of A, B and Cin. Remember that you will need to make register declarations to define the input variables to your U1 module and wire declarations for the output variables. This is because the simulation is run entirely within the development environment. It does not use the input/output constraints associated with the fulladd.v source Run a Behavioral Simulation to verify that you circuits are behaving correctly. Capture these ISim results for your lab report. 7. Run Implementation and then run a Post Implementation Timing Simulation. Measure the timing delay for Cout for when A=1 B=0 transitions to A=1 B=1. Capture these ISim results for your lab report. 8. Generate Bit file and Program Device. Verify that your full adder is working properly then demonstrate it to the TA for sign-off. Implementing a 4-Bit Adder in Verilog 9. Save your project then add a new Verilog Design Source, called fouradd.v, and fill in it's comment block. In this case your inputs and outputs will be 4 bit buses. See the example Port Declaration below. Notice that this module has no inputs for carries. That is because carry from one column to the next is part of the internal workings of this circuit. The user does not need (or want) to see that. Rather the user expects to input two 4-bit numbers and get the correct 4-bit result (or be flagged that an error has occurred). 10. Right click on fouradd.v then Set as Top. In this Verilog module you will instantiate copies of the fulladd module. To instantiate a module you need to call it something unique so that Verilog can separate the fulladd used for bit 0 from the one used for bit 3.

5 Give each of the 4 fulladd-ers you instantiate a U#. See the code example below. You will also need internal connections (called wires ) to convey carry information from one fulladd module to the next. These wires are not inputs or outputs so they weren't defined when we did the port declaration. They are like labeled intermediate points on a circuit diagram. 11. Use assign statements to implement the signed overflow flag, OF_S, and the unsigned overflow flag, which is carry out of the most significant bit, C_MSB. 12. Right click on your fulladd.xdc constraint file and remove it from the project (you should not delete it, however). There can only be one constraint file active in a project at a time. Now add a new contraints file (fouradd.xdc) to your project and assignes inputs A[3:0] to SW3-SW0 (shown below) and B[3:0] to SW7-SW4. Also assign outputs Sum[3:0] to LEDs LD3-LD0 and OF_S to LD15 and C_MSB to LD14 respectively. Remember, pin assignment are given in Figure 16 of the Basys 3 Reference Manual. Run Synthesis. #Switches set_property PACKAGE_PIN V17 [get_ports {A[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {A[0]}] set_property PACKAGE_PIN V16 [get_ports {A[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {A[1]}] set_property PACKAGE_PIN W16 [get_ports {A[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {A[2]}] set_property PACKAGE_PIN W17 [get_ports {A[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {A[3]}] #... ADD other switches and LEDs 12. Add a new source for simulation and create a test bench for your fouradd module. Make sure to set your new TB as top. (If there is a problem, you may need to remove your fulladd testbench. Again, don't delete it!) There are 256 possible input combinations

6 for A and B. Select a handful of inputs to test in your simulation. Be sure to set one or two that will activate OF_S and/or C_MSB. Run a Behavioral Simulation and save the ISim output for your report. 13. Run Implementation and a Post Implementation Timing Simulation. Measure the longest timing delay for the input cases you chose. Capture these ISim results for your lab report. 14. Generate Bit file and Program Device. Verify that your 4-bit adder is working properly then demonstrate it to the TA for sign-off. IMPLEMENT 2's COMP CIRCUIT In this section you will exploit hierarchical design strategies to implement a twos complement circuit. This module will make use of your fouradd module which in turn makes use of your fulladd module. 15. Save your project then add a new Verilog Design Source, called twoscomp4, and fill in it's comment block. Your module will have a single 4-bit input called B and a single 4-bit output called negb. Set twoscomp4 as the Top Module. 16. As we saw earlier in the term 2's complement encoding is an efficient way to encode negative numbers because it is "consistant" under addition. The four bit adder you just implemented works for the addition of both positive and negative numbers provided the numbers are encoded in 2's complement format. As you may remember from Mini-Exam #1 expressing negative numbers in 2's comp is not very intuitive to do by hand. While it is relatively easy to convert +6 to 0110b it is not as straigthforward to convert -6 to its 2's comp representation of Therefore we will create a circuit automatically convert a number B to -B in 2's complement. Note: You will use this module again next week. -B = not(b) + 1 B 2's -B Comp This step will require you to use a multi-bit constant as one of the inputs to your fouradd module. In Verilog, constant vectors are implemented as follows n'bxxx...x where n = number of digits, B = code for the base (e.g. b = binary ) x = digits So a 4-bit constant equal to 0001b would be written in Verilog as 4b' Remove, but don't delete, your fouradd constraint file then add a new constraint file for your 2's comp circuit. Assign inputs B[3:0] to SW3-SW0 and outputs negb[3:0] to LEDs 3-0.

7 19. Add a testbench for your twoscomp4 module and set it as Top in simulation. Instantiate your 2's comp module and exhaustively test all 16 input combinations. 20 Run a Behavioral Simulation and then run Implementation and a Post Implementation Timing Simulation. Capture both these ISim results for your lab report. 21. Generate a bit file and Program the Artix 7. Verify that your 4-bit 2's comp circuit is working properly then demonstrate it to the TA for sign-off. 22. Write a high-quality Lab Report which includes all your Verilog code, constraint, files, testbenches, simulation results, your pre-labs, your sign-off sheet as well as the grading rubric. ALL TEAM MEMBERS SHOULD SAVE THIS PROJECT TO YOUR NETWORK DRIVES RIGHT NOW!!!

8 ECE2029 Lab 2 Sign-Off Sheet Make sure lab instructor/tas initial and date each part. Attach this sheet and the Report Grading Rubric to your team's lab report! Your Name: ECE BOX #: Lab Partner: Date Performed: Demonstrated correctly: Pre-lab Complete (1) (2) (10 pts, individually) Verilog Full Adder (15pts) Verilog 4-bit Adder (20 pts) Verilog 4-bit Two's complement (20 pts) TA Questions: (1) (2) (5 pts, individually ) Report (one per team) (30 pts) (including all Verilog modules, test bench, constraint files, test screen shots, this sign-off sheet and the grading rubric below.)

9 Lab 2 Implementing Combinational Functional Blocks Review Item Comments Points (max) 1) Prelabs from each student complete (5) and thoughtful 2) Introduction effectively presents the (5) objectives and purpose of the lab. Methodology gives enough details to allow for replication of procedure. 3) Discussion opens with an effective (5) statement on the goals of the lab, backs up statement with reference to appropriate findings, provides sufficient and logical explanation for the statement, addresses other issues pertinent to lab. 4) Results opens with effective statement of (5) overall findings, presents visuals clearly and accurately, presents findings clearly and with sufficient support. You MUST include screen shots of the test bench results for each part of the lab. Conclusion convincingly describes what has been learned in the lab. 5) Other: (10) References are included. Tables and figures are formatted. Grammar and spelling are correct Comment Blocks for ALL Verilog modules are filled in with students names and module description/purpose Report is written clearly and to the point. Overall, the team... has successfully demonstrated what the lab was designed to teach demonstrates clear and thoughtful scientific inquiry has accurately measured and analyzed data for lab findings Total: (30)