Lab 2 Implementing Combinational Logic in VHDL. Advanced Testbenches.

Transcription

1 Task 1 (30%) Lab 2 Implementing Combinational Logic in VHDL. Advanced Testbenches. Draw a block diagram of the combinational circuit described by the given below pseudocode. Inputs: A: 8-bit unsigned integer B: 8-bit signed integer Sel: 2-bit selection signal En: 1 bit enable input (active low) Outputs: X: 8 bit integer (treated as signed or unsigned Y: 8 bit integer (treated as signed or unsigned Intermediate Variables: Unsigned 16-bit integers: L Signed 16-bit integers: K Unsigned 8-bit integers: C, D, F, N Unsigned 4-bit integers: G, J Unsigned 2-bit integers: H Unsigned 1-bit integers: I Signed 8-bit integers: E, M 8-bit integers: Xp, Yp (treated as signed or unsigned Algorithm: C = A <<< 4 /* rotation left by 4 */ D = A/2 E = B/2 if A/16 is prime then F = A/16 elsif A is binary palindromic then F = A elsif E is negative then F = C F = E Endif G = F/16

2 If G >= 8 then H = 3 elsif G >= 4 then H = 2 elsif G >=2 then H = 1 H = 0. if G = 0 then I = 0 I = 1 end if if I = 0 then J = 0 elsif H = 3 J = 8 elsif H = 2 J = 4 elsif H = 1 J = 2 J = 1 K = D * E /* signed multiplication */ L = D * E /* unsigned multiplication by an absolute value of E */ M = D + E N = D + E /* addition of an absolute value of E */ if Sel = 0 then Xp = F elsif Sel = 1 then Xp = K/256 elsif Sel = 2 Xp = L/256 if Sel = 3 Xp = M if Sel = 0 then Yp = G J /* G concatenated with J */ elsif Sel = 1 then Yp = K mod 256 elsif Sel = 2 Yp = L mod 256 if Sel = 3

3 Yp = N if En = 0 then X = Xp Y = Yp X = "ZZZZZZZZ" Y = "ZZZZZZZZ" Endif Requirements: 1. You are allowed to use only standard components discussed in Lecture 3: Combinational-Circuit Building Blocks. Data Flow Modeling of Combinational Logic. 2. You are not allowed to use a divisor circuit / implementing division for an arbitrary value of a divisor. All divisions by powers of two should be implemented using appropriate logic or arithmetic shifts. 3. You are not allowed to use mod operator. Replace it by an appropriate split. 4. You are not allowed to use an operator computing an absolute value of the integer X, X. 5. Clearly mark the widths and directions of all buses in your circuit. 6. You can use connections by name, especially if drawing wires would reduce the readability of your diagram. 7. Your diagram can be drawn by hand and scanned (for regular points). You can also use a graphical editor, such as Xfig, Visio, Dia, Power Point, etc. in order to develop an electronic diagram (for bonus points). In case you use a graphical editor, please submit an editable version and a pdf version of your diagram. 8. You can use at most two levels of hierarchy. 9. In case of using ROM, clearly specify the number of address and data bits. In a separate diagram, please show the memory map (the contents) of your ROM. Hints: 1. The entire if operation in the pseudocode (or even two related if operations) may represent a single basic logic component, known to you. 2. Different if operations may represent different combinational components (or different groups of components).

4 Task 2 (30%) Develop a VHDL dataflow description of a combinational circuit described by the pseudocode from Task 1. You description should use only one level of hierarchy (one entity and one architecture), for all components other than is_prime and is_binary_palindromic, which may be implemented using separate entities. Task 3 (20%) Develop an advanced testbench for your VHDL code from Task 2, based on an array of records representing multiple test vectors, to be used to verify the operation of your circuit. Your testbench should give a binary result: circuit correct or circuit incorrect. In case the circuit is incorrect, the first 5 discrepancies between actual and expected outputs should be printed, together with the values of corresponding inputs. Use the array of records provided on the web page of Lab 2, generated by the C program available on the same page. Use this testbench to debug your circuit, and document your findings. Print an output from simulation (in the form of timing waveforms and console messages) to the PDF file. Please note that you can modify C program, and generate test vectors for intermediate results, if needed. Task 4 (20%) Modify your testbench from Task 3, in such a way that the test vectors are stored in a text file. Use the text file provided on the web page of Lab 2, generated by the C program available on the same page. Use this testbench to debug your circuit, and document your findings. Print an output from simulation (in the form of timing waveforms and console messages) to the PDF file. Task 5 (tested during demonstration, may affect up to 50% of your points) Be prepared to demonstrate the operation of your code using Aldec Active-HDL and Xilinx ISim. You may be tested on your level of understanding of both simulators, based on the following features. 1. Adding signals to the Waveform window. 2. Including signals from lower levels of hierarchy.

5 3. All options to run Simulation. 4. Introduce Breakpoints and showing the execution of logic before and after Breakpoints in the Waveform window. 5. Measuring Time intervals. 6. Dealing with Buses (Expanding and viewing all bits of a signal). 7. Taking a signal and changing Radix to Decimal, Binary and Hexadecimal. 8. Saving the waveforms in Native format of the simulators. 9. Printing output of the simulators to PDF files. 10. Clearing waveforms. In your report, please describe any problems you have encountered while using Aldec Active-HDL and Xilinx ISim. Please grade each simulator on the scale from 0 to 10, based on your experiences with using it. Shortly justify your rating. Bonus task (bonus 20%) Modify your block diagram and your VHDL code, by adding output Z calculated as follows: Z = Xp <<< Yp. Show an internal structure of the combinational variable rotator using block diagram. Implement your circuit using dataflow VHDL. Extend your two testbenches, and use them to debug your code. Deliverables: 1. Block diagram handdrawn and scanned for regular points; electronic version (editable and PDF) for 5 extra points. 2. Dataflow VHDL code for Tasks 2, and possibly Bonus Task. 3. Behavioral VHDL codes of testbenches for Tasks 3, 4, and possibly Bonus Task. 4. Short report describing the status of your code, including the statement which portions of the pseudocode you have been able to implement and verify successfully. Please describe any problems you have encountered while coding in VHDL or using Active-HDL and ISim. Please grade each simulator on the scale from 0 to 10, based on your experiences with using it. Shortly justify your rating. Important Dates Hands-on Session and Introduction to the Experiment Demonstration and Deliverables Due Wednesday Section Thursday Section 01/30/ /31/ /06/ /07/2013