EE 101 Lab 5 Fast Adders

Transcription

1 EE 0 Lab 5 Fast Adders Introduction In this lab you will compare the performance of a 6-bit ripple-carry adder (RCA) with a 6-bit carry-lookahead adder (CLA). The 6-bit CLA will be implemented hierarchically starting with a 4-bit CLA block and building up to a 6-bit CLA. You should work individually on this lab, NOT in teams. 2 What you will learn This lab is intended to give you experience using the hierarchical design features of the Xilinx tools. Specifically, you will learn how to take a design, create a symbol for it and instantiate it in other designs. Also, this lab will illustrate the benefits of using a carry lookahead adder vs. a ripple carry adder. 3 Background Information and Notes Carry-Lookahead Adder Design: We have seen that ripple-carry adders are slow, especially for large bit-widths, because the carry generation delay is proportional to the length of the chain, n. Carry-lookahead adders seek to compute the carries for a group of columns all at once. By using this idea and implementing it hierarchically, we can create a carry chain that is proportional to the logarithm of the length of the chain (log m n). To implement a carry-lookahead adder, we rely on the generating all the carries for a set of columns at one time. To do this, we define the concept of carry propagation and generation for a single column. A column of bits (A i, B i ) will propagate a carry-in in if either input is true. A column of bits will generate a carry (w/o having to wait for the carry coming in) if both inputs are true. p i = A i + B i g i = A i B i For 4-columns of additions and the overall carry-input, C0, we can define each carry (C, C2, C3, C4) using the following equation: c i+ = g i + p i c i However, this does not make the design any faster because c i+ still would need to wait for c i to be generated. However, by unrolling the recursion relation (substituting c i with its form of c i+ ) we can reduce down to only two levels of logic. For example: c = g 0 + p 0 c 0 c 2 = g + p c = g + p (g 0 +p 0 c 0 ) = g + p g 0 + p p 0 c 0 Last Revised: 0/8/204

2 EE 0 Lab 5 - Fast Adders Essentially, the equation for c 2 can be understood by looking at each term. C 2 can be in three ways: g could be indicating a carry was generated from that column (A and B were both generating a carry), or p and g 0 could be (indicating the 0 th column will generate a carry and at least input in the st column is allowing that carry-in to propagate to the carry-out of that column), or p, p 0, and c 0 could be (indicating the original carry-in was and at least input is in each of the st and 0 th columns allowing the original carry-in to propagate through). As an analogy consider a tube broken into segments with valves to control the flow between segments. Each segment also has an entrance where fluid can be inserted. Insertion of the fluids are the generates and the control of the valves are equivalent to the propagate inputs. The cases for the fluid reaching the output (i.e. c 2 are shown below) Generate g Valve (p) Generate g0 Valve (p0) Carry-in c0 c2 Figure - Analogy for propate (p i ) and generate (g i ) signals Using a similar recursive unrolling, 2-level SOP equations for c 3 and c 4 can be derived. In addition, to generating the carries for 4-columns of addition, we can also generate an overall propagate, P, and generate, G. We will eventually use this carry-lookahead logic to hierarchically create a 6-bit adder. These overall Propagate and Generate signals indicate whether for 4-columns of addition, a carryinput to the first column will propagate all the way through the 4 columns or whether the 4 columns will generate a carry-out independent of the carry-in to the 4 columns. These signals can be defined as: P = p 3 p 2 p p 0 G = g 3 + p 3 g 2 + p 3 p 2 g + p 3 p 2 p g 0 2 Last Revised: 0/8/204

3 EE 0 Lab 5 - Fast Adders We will decompose the design into several levels of hierarchy. You will design a block of logic to generate all the p i and g i signals called PG. You will design a block of logic to generate all the carries for 4 sets of p,g inputs, called CLL (Carry- Lookahead Logic). You will then design a 4-bit carry-look ahead adder, called, and then use 4 of these plus another CLL block to create a 6-bit CLA. g3 p3 g2 p2 g p g0 p0 C0 PG A3 B3 A2 B2 A B A0 B0 Carry-Lookahead Logic (CLL) g3 p3 g2 p2 g p g0 p0 G P C4 C3 C2 C Figure 2 - Implementation of PG and CLL block (you will need to derive the logic for the CLL block yourself) A[3:0] B[3:0] C0 A3 B3 A2 B2 A B A0 B0 A3 B3 A2 B2 A B A0 B0 PG g3 p3 g2 p2 g p g0 p0 g3 p3 g2 p2 g p g0 p0 C0 Carry-Lookahead Logic (CLL) G P C4 C3 C2 C A3 B3 A2 B2 A B A0 B0 S3 S2 B[3:0] S S0 G P C4 S[3:0] Figure 3 - Implementation of a 4-bit Carry-Lookahead adder () using the PG and CLL blocks Last Revised: 0/8/204 3

4 EE 0 Lab 5 - Fast Adders A[5:2]B[5:2]? A[:8] B[:8]? A[7:4] B[7:4]? A[3:0] B[3:0] C0 A[3:0] B[3:0] C0 A[3:0] B[3:0] C0 A[3:0] B[3:0] C0 A[3:0] B[3:0] C0 G P C4 S[3:0] G P C4 S[3:0] G P C4 S[3:0] G P C4 S[3:0]?? N/C?? N/C?? N/C?? N/C S[5:2] S[:8] S[7:4] S[3:0] CLA6???????? g3 p3 g2 p2 g p g0 p0 C0 Carry-Lookahead Logic (CLL) G P C4 C3 C2 C C6??? Figure 4-6-bit CLA using building blocks and CLL block to AVOID carry chaining (?'s represent connections you need to figure out, N/C = Not Connected = Should not be connected to anything) Note: Many good web resources exist with discussions of carry-lookahead logic and carry-lookahead adders (Wikipedia offers a reasonably good explanation for carry lookahead adder ). Feel free to reference these for your design. Xilinx Tools for Hierarchy and Timing: Before starting this lab you should either watch the advanced Xilinx design and simulation training video or the in-class demo covering the same topics by your instructor/ta. After this training you should be familiar with: a) Creating a symbol/component for a schematic and instantiating that component into other designs b) Naming instances c) Creating a multi-sheet design d) Synthesizing a design and finding the area and timing results e) Reading the critical path information In this design you will need to design the CLL component and instantiate it in your design. You will design the block and create a symbol so you can instantiate it in your CLA6 design. Use the symbol wizard (Tools..Symbol Wizard) and select the schematic you want to create the symbol for. You can then instantiate it from the Symbols tab and the Category corresponding to your project directory. 4 Last Revised: 0/8/204

5 EE 0 Lab 5 - Fast Adders To see the timing and area of the circuit, you will need to double-click the Synthesize process in the processes pane. Check for warnings and errors in the console as your design is synthesized. Then expand the Synthesis process and double-click Synthesis Report. Scroll down to find the logic usage % and the estimated critical path timing. 4 Prelab Watch the Xilinx advanced design and simulation video tutorial. 5 Procedure To implement your 6-bit CLA, we will build up a hierarchy of components (those shown in the figures above) and compare the 6-bit CLA to a 6-bit RCA.. Download the skeleton CLA project.zip file from Blackboard. Extract the files to a folder. 2. The CLA project has a completed PG schematic and we have created a symbol for it as well. You should not need to modify this symbol/component or underlying schematic. 3. The CLA project also has an unfinished CLL schematic with just the I/O s defined. Complete the logic for the carries: c, c2, c3, c4, and the overall P and G signal for the 4-column set. Your schematic will likely require multiple sheets. If you do need another sheet, right-click anywhere on the schematic, select Object Properties and under the Sheets category, click the New button and create another sheet. You can switch between sheets by clicking the appropriate tabs in the top right of the schematic window. Any net that has been labeled on one sheet can be accessed by using the same net name/label on another sheet (same label/net name implies a wire connection). A symbol has already been created for you for this component based on its I/O. 4. The skeleton project also has an unfinished schematic with just the PG component instantiated and the I/O s defined. Complete the design of a 4-bit CLA by instantiating the CLL component (in the Symbols tab, look for the category labeled with your project directory). Reference Figure 3 for design details. Make the necessary connections and implement logic for the sum bits. Other outputs of the include the final carry out and the OVERALL P and G signals from your CLL block which will be needed to make a fast, 6-bit CLA. Please also name/label the CLL instance itself as _CLL (by selecting the instance, right-clicking and selecting Object Properties, you can name the instance in the resulting dialog box.) Last Revised: 0/8/204 5

6 EE 0 Lab 5 - Fast Adders 5. Create a symbol for your design taking care to make sure the symbol is associated with the schematic. 6. Add a new schematic to your project and call it cla6. In this schematic, instantiate four components and a CLL block to build an equivalent 6-bit CLA. Reference Figure 4 for design details (you will need to figure out what connections should be made for those inputs and outputs labeled with a? ; also the carry-outs marked N/C should not be connected to anything think about where the carry-in s to each should come from.). The I/O s of this CLA6 should be as follows [You can reference the completed 6-bit RCA design available online for how we want the I/O and how to make the connections.] A(5:0) B(5:0) C0 S(5:0) C6 Input Input Input Initial carry-in Output Sum Output Final carry-out You should also create intermediate labels for the P and G signals coming out of your blocks. These will be helpful for debug purposes. In addition, name/label each of the instances with some kind of naming pattern (up to you) as well as naming the CLL instance. This will also make debugging easier when trying to select which signals you want to view in ISim. 7. Once you have completed your design, open each schematic (CLL,, and CLA6) and select Tools..Check Schematic. This will report any errors in connections or naming in the console window at the bottom of the screen. 8. Now let us simulate our design to ensure it is working properly. In the sources pane click over to Behavioral Simulation from Implementation. Add a new testbench source (Verilog Test Fixture) to your project called cla6_tb.v. When asked make sure you select cla6 as the associated design for this testbench. Change the Verilog testbench module name to cla6_tb(). Again delete the lines between the `ifdef and `endif. Add your own initial block with desired input patterns for A, B, and C0: initial begin A = 6 h0000; B = 6 h0000; C0 = 0; #200; A = 6 h0000; B = 6 h0000; C0 = ; #00; // more assignments separated by #00 delays end 6 Last Revised: 0/8/204

7 EE 0 Lab 5 - Fast Adders At this point you should think of input cases that will exercise your adder. Key cases are those that cause carries, especially carries from one block to another. For example, adding 000f hex to 000 hex will cause a carry out of the first 4-bit CLA to the input of the next and should produce an output of 000 hex. Generate enough test cases (vectors) as you think appropriate to test your design. [Recall that an exhaustive test of your adder would require 2 33 combinations since there are 33 inputs]. But by selecting good test cases we can have confidence our circuit is working. Save your testbench. 9. To simulate, go to the processes pane and expand the ISim Simulator option in the Processes tab. Right-click the Simulate Behavioral Model option and select Properties. Under Simulation Properties set the Simulation Run Time to 2000 ns rather than 000 ns. Click OK. 0. Now double-click Simulate Behavioral Model to launch ISim to simulate your design. Examine the waveform output and see if your adder is working. If your circuit is NOT working, you will need to find the source of the error, likely by adding more internal and intermediate signals to the waveform. You can find these signals under the appropriate instances, drag them to the wave window, reset the simulation by typing restart f at the prompt in the console window and then re-run the simulation by typing run 2000 ns at the prompt in the console window. When you find a signal that looks to be wrong, go back to your schematics and figure out why. Close Modelsim, change and save the schematics to fix the problem, and then restart and rerun the Modelsim simulation. Iterate through this process until your circuit works.. The last step is to synthesize your working design to find the timing and area for your design. In the sources pane, switch back to Implementation from Behavioral Simulation. Then in the processes tab, double-click Synthesize. After synthesis has completed there should be a green check mark next to it if it ran without error. Errors and warnings can be viewed (and will need to be fixed) by looking in the appropriate tabs at the bottom of the screen. Once synthesis has run correctly, click the "Design Summary/Reports" Option in the Processes Pane. It will bring up a Design overview table in the main window. Find the "Synthesis report option under Detailed Reports and click on it. Scroll to the bottom to the Final Report section. You should see a Device Utilization Summary listing how many of the 4656 internal logic slices (resources) were used and how many of the 232 outer ring logic (IOB s) blocks were used. By adding the total used and dividing by we can get a rough estimate of the chip area needed to implement your design. (Example: If your design requires 0 internal logic slices and 50 bonded IOB s then the approximate chip area is 50/4888 which is approximately % of the chip area. Next examine the Timing Report further down. At the end of that section it will list the worst path delay in nanoseconds and approximate levels of logic, as Last Revised: 0/8/204 7

8 EE 0 Lab 5 - Fast Adders well as showing you the entire path that causes that worst case delay. Record these values. You can also read this path by looking at the hierarchical names to see what blocks the path is tracing through (e.g. _/CLA_PG -> _/CLL -> etc.). You will need to understand this path for the Review portion of the lab. 6 Review. What were the area percentage and worst case timing and levels of logic for your 6-bit CLA? 2. Print out the top-level schematic page of your CLA6 (i.e. the four 4-bit CLA s plus the hierarchical CLL). Then on that sheet, trace the critical-path (worst delay path through the circuit) using a colored pen or highlighter. You should start at some Ai or Bi and end at the output that takes the longest to become valid, tracing the intermediate steps along the way. 3. We have posted a completed 6-bit RCA design project. Download the project, synthesize it and compare the worst path delay time and approximate levels of logic to the corresponding values of your 6-bit CLA. 4. Consider the case of building a 64-bit RCA. Using your understanding of an RCA and the results from the 6-bit RCA design, approximately how many levels of logic would the critical path be for a 64-bit RCA. 5. Now consider the case of building a 64-bit CLA. Describe (using a few sentences) how you could create a 64-bit CLA using your 6-bit CLA s as building blocks. Then as precisely as possible indicate how many levels of logic the critical path would be of the 64-bit CLA, giving explanation for your answer. 8 Last Revised: 0/8/204

9 EE 0 Lab 5 - Fast Adders 7 Lab Report Name(s): Due: Score: (Detach and turn this sheet along with any other requested work or printouts) You may turn in one report PER group.. Turn in a printout of your CLL schematic, schematic, CLA6 schematic, as well as a printout of your testbench waveform from ISim [Show the inputs in hex rather than binary so it is readable]. 2. Turn in answers to the review questions. (For #2, attached your schematic with critical path highlighted). Last Revised: 0/8/204 9

10 EE 0 Lab 5 - Fast Adders 8 EE 0 Lab 5 Grading Rubric Student Name: Item Outcome Score Max. CLL Correct p,g logic generation Correct carry implementation: C4,C3,C2,C CLA logic (2 pts. Each) # correct 4 Overall P generation Overall G generation 2 Correct sum implementation: S3, S2, S, S0 Correct symbols (no missing ports) CLA6 Correct wire connections Additional CLL used Additional CLL connected correctly 2 3 Testbench and Simulation Tested carries from 4-bit CLA 2 Tested carries from hierarchical CLL 2 Waveform provided Review Questions Correct CLA area number and percentage Correct timing number and levels of logic Correct highlighted critical path 3 Correct RCA area and timing Extrapolated 64-bit RCA timing is correct and adequately documented and described Extrapolated 64-bit CLA timing is correct and 2 adequately documented and described SubTotal 30 Late Deductions (- pts. per day) Total 30 Open Ended Comments: 0 Last Revised: 0/8/204