Intel instruc,on set architecture-32 bit (IA-32)

Transcription

1 Intel instruc,on set architecture-32 bit (IA-32) ISA Background ISA evolution IA-32 Overview Pentium 4 / Netburst µarchitecture SSE2 Hyper Pipeline Overview Branch Prediction Execution Types Rapid Execution Engine Advanced Dynamic Execution Memory Management Segmentation Paging Virtual Memory Address Modes / Instruction Format Address Translation Cache Levels of Cache (L1 & L2) / Execution Trace Cache Instruction Decoder System Bus Register Files Enhanced Floating Point & Multi-Media Unit

2 Instruc,on Set Architecture (ISA) Serves as an interface between software and hardware. Provides a mechanism by which the software tells the hardware what should be done. High level language code : C, C++, Java, Fortran, compiler Assembly language code: architecture specific statements assembler Machine language code: architecture specific bit patterns software instruction set hardware

3 Evolu,on of Instruc,on Sets Single Accumulator (EDSAC 1950, Maurice Wilkes) Accumulator + Index Registers (Manchester Mark I, IBM 700 series 1953) Separation of Programming Model from Implementation High-level Language Based Concept of a Family (B ) (IBM ) General Purpose Register Machines Complex Instruction Sets Load/Store Architecture (Vax, Intel ) (CDC 6600, Cray ) CISC Intel x86, Pentium RISC (MIPS,Sparc,HP-PA,IBM RS6000,PowerPC )

4 IA-32 Overview Traced to 1969 Intel 4004 P4 1 st IA-32 processor based on Intel Netburst microprocessor. Netburst Allows Higher Performance Levels Performance at Higher Clock Speeds Compa,ble with exis,ng applica,ons and opera,ng systems WriPen to run on Intel IA-32 architecture Processors

5 IA-32 Overview Rapid Execu,on Engine Hyper Pipelined Technology Advanced Dynamic Execu,on Innova,ve Cache Subsystem Streaming SIMD Extensions 2 (SSE2) 400 MHz System Bus

6 Hyper Pipelined What is hyper pipeline technology? Deeper pipeline Fewer gates per pipeline stage What are the benefits of hyper pipeline? Increased clock rate Increased performance

7 Hyper Pipelined 1 Fetch 2 Fetch 3 4 Decode Decode 5 6 Decode Rename 7 ROB Rd Typical P6 Pipeline 8 9 Rdy/Sch Dispatch 10 Exec 1 2 TC Nxt IP 3 4 TC Fetch 5 6 Drive Alloc 7 8 Rename 9 Que 10 Sch 11 Sch 12 Sch 13 Disp 14 Disp 15 RF 16 RF 17 Ex 18 Flgs 19 BrCk 20 Drive Typical Pen,um 4 Pipeline

8 Hyper Pipelined 1 2 TC Nxt IP 3 4 TC Fetch 5 6 Drive Alloc 7 8 Rename 9 Que 10 Sch 11 Sch 12 Sch 13 Disp 14 Disp 15 RF 16 RF 17 Ex 18 Flgs 19 BrCk 20 Drive 3.2 GB/s System Interface BTB & I-TLB Decoder L2 Cache and Control BTB Trace Cache µcode ROM Rename/Alloc µop Queues Schedulers Integer RF FP RF Store AGU Load AGU ALU ALU ALU ALU FP move FP store Fmul Fadd MMX SSE L1 D-Cache and D-TLB

9 Branch Predic,on

10 Branch Predic,on Centerpiece of dynamic execu,on Delivers high performance in pipelined µ- architecture Allows con,nuous fetching and execu,on Predicts next instruc,on address Branch is predictable within 4 or less itera,ons Benefit: Branch Predic,on decreases the amount of instruc,ons that would normally be flushed from pipeline

11 Branch Predic,on If (a == 5) a = 7; Else a = 5; Examples L1: lpcnt++; If ((lpcnt % 5)== 0) prini ( Loop count is divisible by 5\n ); Predictable Not Predictable

12 Out-of-Order Execu,on Logic Re,rement Logic ` Branch History Update

13 Rapid Execu,on Engine Contains 2 ALU s Twice core processor frequency Allows basic integer instructions to execute in ½ a clock cycle Up to 126 instructions, 48 load, and 24 stores can be in flight at the same time Example Rapid Execution Engine on a 1.50 GHz P4 Processor runs at Hz?

14 Advanced Dynamic Execu,on Out-of-Order Engine Reorders Instructions Executes as input operands are ready ALU s kept busy Reports Branch History Information Increases overall speed

15 Memory Management (PVAM)* The protection mechanism is divided into two parts: Segmentation - isolates individual processes so that multiple programs can on same processor without interfering w/each other. Demand Paging - provides a mechanism for implementing a virtual-memory that is much larger than the actual memory, seemingly infinite. * PVAM = protected virtual addressing mode

16 Underlying Concepts The following slides will illustrate the underlying principles of the x86 PVAM operation: 1) Memory Management 2) Operating modes 3) Paging 4) Segmentation 5) Address translation 6) Privilege levels 7) addressing modes

17 Multitasking memory management Virtual Addressing Reloca'on In systems with virtual memory, programs in memory must be able to reside in different parts of the memory at different,mes. This is because when the program is swapped back into memory aper being swapped out for a while it can not always be placed in the same loca,on. Memory management in the opera,ng system should therefore be able to relocate programs in memory and handle memory references in the code of the program so that they always point to the right loca,on in memory. Protected Protec'on Processes should not be able to reference the memory for another process without permission. This is called memory protec,on, and prevents malicious or malfunc,oning code in one program from interfering with the opera,on of other running programs. Sharing Even though the memory for different processes is protected from each other different processes should be able to share informa,on and therefore access the same part of memory. Logical organiza'on Programs are open organized in modules. Some of these modules could be shared between different programs, some are read only and some contain data that can be modified. The memory management is responsible for handling this logical organiza,on that is different from the physical linear address space. One way to arrange this organiza,on is segmenta,on. Physical organiza'on Memory is usually divided into fast primary storage and slow secondary storage. Memory management in the opera,ng system handles moving informa,on between these two levels of memory.

18 Modes of Opera,on Concentration on: Protected mode - Native operating mode of the processor. All features available, providing highest performance and capability. Other modes: - Must use segmentation, paging optional. Real-address mode processor programming environment System management mode (SMM) - Standard arch. feature in all later IA-32 processors. Power management, OEM differentiation features Virtual-8086 mode - used while in protected mode, allows processor to execute 8086 software in a protected, multitasked environment.

19 Virtual Memory Main memory acts as a cache to secondary storage Allows memory to be shared Make memory appear to be larger than it physically is Each program has own address space Enforces protec,on Virtual memory block is called a page, a miss is called a page fault Virtual addresses are translated into physical

20 Memory Management Address Transla,on Ex: Instruction Address Instruction Instruction Decoder Control Word Memory IA-32 (Virtual Address) Logical Address Segmentation & Paging Physical Address Control Word Memory

21 Converting a Logical to Linear Address The segment selector (16-bit) points to a segment descriptor, which contains the base address of a memory segment. The 32-bit offset from the logical address is added to the segment s base address, generating a 32-bit linear address. addresslogical ector Sel LDTR GDTR/ fset Of tabledescriptor DescriptorSegment addresslinear + address of(contains base table)descriptor

22 Address Transla,on Segment Offset Linear Address Dir Page Offset Physical Address Control Word Index TI RPL Segment Table Index: The number of the segment. Serves as an index to the segment Table. TI: (one bit) Table indicator indicates either global or local segment table to be used for translation RPL: (two bits) Requested privilege level, 0=high privilege, 3 = low Page Directory Paging Page Table Main Memory

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25 Paging Subdivide memory into small fixed-size chunks called frames or page frames Divide programs into same sized chunks, called pages Loading a program in memory requires the allocation of the required number of pages Limits wasted memory to a fraction of the last page Page frames used in loading process need not be contiguous - Each program has a page table associated with it that maps each program page to a memory page frame

26 Paging Linear Address Logical Address Segmentation Dir Page Offset Virtual Memory: Physical Address Control Word Only program pages required for execution of the program are actually loaded Demand Paging Only a few pages of any one program might be in memory at a time Possible to run program consisting of more pages than can fit in memory Page Directory Paging Page Table Main Memory

27 Page Faults Main memory is 100,000,mes faster than disk Page faults are expensive Reduce page fault rate Fully associa,ve placement of pages in memory Each process has a page table that maps virtual addresses to physical addresses OS creates space on disk for all the process s pages Swap space OS maintains another table that keeps track of each page in main memory During a page fault, the OS must decide which page to replace Least recently used (LRU) Write-back used for writes

28 TLB a memory cache that stores recent translations of virtual memory to physical addresses for faster retrieval. When a virtual memory address is referenced by a program, the search starts in the CPU. First, instruction caches are checked. Page lookups must be performed in hardware Page table is cached on-chip Transla,on-lookaside buffer Small fully associa,ve or large limited associa,ve

29 Segmenta,on Programmer subdivides the program into logical units called segments - Programs subdivided by function - Data array items grouped together as a unit Paging - invisible to programmer, Segmentation - usually visible to programmer - Convenience for organizing programs and data, and a means for associating access and usage rights with instructions and data - Sharing, segment could be addressed by other processes, ex: table of data - Dynamic size, growing data structure

30 Processor Privilege-Levels The usefulness of protected-mode derives from its ability to enforce restrictions upon software s freedom to take certain actions Four distinct privilege-levels are supported Organizing concept is concentric rings Innermost ring has greatest privileges, and privileges diminish as rings move outward

31 Four Privilege Rings Ring 3 Ring 2 Least-trusted level Ring 1 Ring 0 Most-trusted level

32 Suggested ring purposes Ring0: opera'ng system kernel Ring1: opera'ng system services Ring2: custom extensions Ring3: ordinary user applica'ons

33 Data Isolation To guard against unintentional sharing of privileged information, different stacks are provided at each distinct privilege-level Accordingly, any transition from one ring to another must necessarily be accompanied by an mandatory stack-switch operation The CPU provides for automatic switching of stacks and copying of parameter-values

34 Descriptors

35 Selectors

36 Call-Gate Descriptors offset[ ] D P P 0 L gate type parameter count code-selector offset[ ] 31 0 Legend: P=present (1=yes, 0=no) DPL=Descriptor Prvilege Level (0,1,2,3) code-selector (specifies memory-segment containing procedure code) offset (specifies the procedure s entry-point within its code-segment) parameter count (specifies how many parameter-values will be copied) gate-type ( 0x4 means a 16-bit call-gate, 0xC means a 32-bit call-gate)

37 An Interprivilege Call When a lesser privileged routine wants to invoke a more privileged routine, it does so by using a far call machine-instruction (also known as a long call in the GNU assembler s terminology) 0x9A (ignored) callgate-selector opcode offset-field segment-field In as assembly language: lcall $callgate-selector, $0

38 Sequence of CPU s actions - pushes the current SS:SP register-values onto a new stack-segment - copies the specified number of parameters from the old stack onto the new stack - pushes the updated CS:IP register-values onto the new stack - loads new values into registers CS:IP (from the callgate-descriptor) and into SS:SP

39 Diagram of the relationships old code-segment new code-segment CS:IP call-instruc'on TASK STATE SEGMENT called procedure OLD STACK SEGMENT params SS:SP stack-pointer Descriptor-Table gate-descriptor TSS-descriptor params NEW STACK SEGMENT TR GDTR

40 Segment Addressing Modes Offset - Determine technique for offset genera,on Base Register Index Register x Scale 1, 2, 4, or 8 Descriptor Registers + Displacement (in instruction; 0, 8, or 32 bits) Segment Base Address Access Rights Limit Base Address Effective Address (Offset) + Linear Address Paging (invisible to programmer) Limit Main Memory

41 Base Mode Addressing Modes e at Imedi dregister acement spl Di tbase dex tscaled ith tbase with d tbase ve i at Rel AOperand = R= LA (SR) A+ = LA (B) (SR) + = LA A+ (SR) (B) LA = + A+ (SR) S LA = x (I) + A+ (SR) (I) LA = (B) + A+ (B) + (SR) S LA = x (I) + (PC) A+ = LA thmi gor Al sla Xntents = (X) of t rsr rpc A = contents of an address field in the instruction rr rb ri g rs

42 Segment Ex: scaled index with displacement Index Register x Descriptor Registers Scale 1, 2, 4, or 8 + Displacement (in instruction; 0, 8, or 32 bits) Segment Base Address Access Rights Limit Base Address Effective Address (Offset) + Linear Address Limit

43 Instruc,on Format Bytes 0 or 1 0 or 1 0 or 1 0 or 1 Instruction Prefix Segment Override Operand Size Override Address Size Override Bytes 0 to 4 1 or 2 0 or 1 0 or 1 0, 1, 2, or 4 0, 1, 2, or 4 Instruction Prefixes Opcode Mod R/M SIB Displacement Immediate Mod Reg/Opcode R/M Scale Index Base

44 Cache Organiza,on Physical Memory System Bus (External) L2 Cache Data Cache Unit (L1) Bus Interface Unit Instruc'on TLBs Data TLBs Instruc'on Decoder Trace Cache Store Buffer

45 Enhanced FP & mul,-media Unit Expands Registers 128-bit (from 64-bit) Adds One Additional Register Data Movement Improves performance on applications Floating Point Multi-Media

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47 Important ISA concepts: ISA evolu,on Netburst Features Virtual addressing Protec,on Real mode Protected mode Virtual 8086 mode Virtual address transla,on logical-linear-physical Paging Segmenta,on Privilege Levels Descriptors Selectors Addressing modes