SystemC. Short Introduction

Transcription

1 SystemC Short Introduction Karsten Einwich Fraunhofer IIS/EAS Dresden

2 SystemC is a definition of C++ language constructs for the description of complex digital hardware systems on different abstraction levels, using different Models of Computation (MoC) Definition of classes for modeling: Time De-composition, Hierarchy Concurrency (processes) / Signals / Reactivity Generic communication channels Generic Model of Computation based on the communication and synchronization of processes Datatypes SystemC models can be simulated using a reference implementation of the C++ class library 2

3 SystemC Use Flow

4 SystemC Files module1.h module2.h module1.cpp module2.cpp tb.cpp int sc_main( ) Recommendations: Split the module description into a header and a cpp implementation file Only one module per header / cpp file The name of the module shall be equal to the header / cpp file name Do not use capital letters and special characters (like ä,%,&, space, ) tb.exe

5 SystemC Example

6 A Simple SystemC Module #include <systemc.h> SC_MODULE(adder) sc_in<int> in1; sc_in<int> in2; sc_out<int> outp; void do_add(); SC_CTOR(adder) SC_METHOD(do_add); sensitive << in1 << in2; } }; void adder::do_add() outp = in1 + in2; } ENTITY adder IS PORT( in1 : IN Integer; in2 : IN Integer; outp: OUT Integer ); END; ARCHITECTURE behav OF adder IS BEGIN END behav; outp <= in1 + in2;

7 A Simple SystemC Module SystemC Modules include systemc.h or systemc SC_MODULE macro for module class declaration SC_CTOR macro for constructor One or more ports of an arbitrary types Module behavior described in process(es) A process is a C++ method without arguments and void return type which is registerd as a so called method or thread process in the constructor by the macros SC_METHOD or SC_THREAD SystemC processes can be sensitized in general to events (an sc_in port in the sensitive list represents a value changed event) #include "systemc.h" SC_MODULE(adder) sc_in<int> in1; sc_in<int> in2; sc_out<int> outp; void do_add() ; SC_CTOR(adder) SC_METHOD(do_add); sensitive << in1 << in2; } }; void adder::do_add() outp = in1 + in2; }

8 SystemC Module with Thread Process #include <systemc.h> SC_MODULE(stimuli_generator) sc_out<int> out_in1, out_in2; sc_in<int> in_outp; sc_out<bool> out_clk; void do_stimuli() ; SC_CTOR(stimuli_generator) SC_THREAD(do_stimuli); } }; void stimuli_generator::do_stimuli() out_clk = 0; out_in1 = 3; out_in2=0; wait(1.0,sc_ms); out_clk = 1; wait(1.0,sc_ms) if(in_outp!= 3) SC_REPORT_ERROR( stim_err, wrong result ); : sc_stop(); } ENTITY stimuli_generator IS PORT( out_in1 : OUT Integer; out_in2 : OUT Integer; in_outp : IN Integer; out_clk : OUT Bit ); END; ARCHITECTURE stimulus1 OF stimuli_generator IS BEGIN do_stimuli: PROCESS() BEGIN out_clk <= 0 ; out_in1<=3; out_in2 <=0; WAIT(1 ms); out_clk<= 1 ; WAIT(1 ms); IF in_outp /= 3 THEN ASSERT( wrong result ); END IF; : END do_stimuli; END stimulus1 ; Dac workshop san diego page 2-8

9 Method and Thread Processes SC_METHOD Registered in the constructor with SC_METHOD macro SC_THREAD / SC_CTHREAD Registrated in the constructor with SC_THREAD / SC_CTHREAD macro Activated first after elaboration and by events (e.g. signal changes) of the sensitivity list (sensitive << xxx statement after registration) Activated once after elaboration if returned it will never activated again Can be never suspended runs always to the end Used e.g. for RTL Can be suspended by wait statements Used e.g. for behavioral, modeling, stimuli, state machines Fast Not so fast

10 Hierarchical Model Example #include <systemc.h> #include "adder.h" #include "reg.h" SC_MODULE(dut) sc_in<bool > sc_in<int > sc_out<int > }; clk; in1, in2; outp; sc_signal<int> internal_signal; void architecture(); adder* add1; reg* reg1; SC_CTOR(dut) #include "dut.h" architecture(); } void dut::architecture() add1 = new adder("add1"); add1->in1(in1); add1->in2(in2); add1->outp(internal_signal); } reg1 = new reg("reg1"); reg1->clk(clk); reg1->inp(internal_signal); reg1->outp(outp); ENTITY dut IS PORT ( signal clk : in bit; signal in1, in2 : in bit; signal outp : out bit); END ENTITY dut; ARCHITECTURE str OF dut IS SIGNAL internal_signal: BIT; BEGIN add1: ENTITY work.adder(dfl) PORT MAP ( in1 => in1, in2 => in2, outp => internal_signal); reg1: ENTITY work.reg1(bhv) PORT MAP ( clk => clk; inp => internal_signal, outp => outp); END ARCHITECTURE str;

11 Testbench Example #include "dut.h" #include "stimuli_generator.h" int sc_main(int argc, char* argv[]) sc_signal<int> signal1, signal2; sc_signal<int> signal3; sc_signal<bool> clock1, stimuli_generator stg1("stg1"); stg1.out_in1(signal1); stg1.out_in2(signal2); stg1.in_outp(signal3); stg1.out_clk(clock1); dut dut1("dut1"); dut1.in1(signal1); dut1.in2(signal2); dut1.out(signal3); dut1.clk(clock1); sc_trace_file *tf= sc_create_vcd_trace_file("simplex"); } sc_trace(tf, clock1, "clock1"); sc_trace(tf, signal1, "in1"); sc_trace(tf, signal2, "in2"); sc_trace(tf, signal3, "out"); sc_trace(tf, dut1.internal_signal,"dut_signal"); sc_start(); sc_close_vcd_trace_file(tf); return 0;

12 SystemC notion of time - sc_time time is represented by the sc_time class there is support for absolute time units Syntax: sc_time time_obj(value, time_unit); value: integer or double representing the numerical time value time_unit: one of the following modifiers SC_FS: 1e-15s SC_PS: 1e-12s SC_NS: 1e-9s SC_US: 1e-6s SC_MS: 1e-3s SC_SEC: 1s arithmetic and comparison operators are defined stream output (operator<<) prints the time

13 Data Types C++ built in types long, int, short, char, unsigned long, unsigned short, unsigned char, float, double, long double, bool, long long, unsigned long long C++ STL types complex<t>, vector<t>, string,... SystemC provided data types Scalar boolean types, Vector boolean types, Integer types, Fixed point types User defined data types Assignment (=) and compare (==) operators must be defined

14 Selected SystemC Datatypes bool (sc_bit is obsolete) Single bit values true / false ( 1 / 0) sc_logic Four valued logic (`0`, `1`,`X`,`Z`) sc_bv<length> Vector of bool, bitwise logical operations, operations with strings, integers,... sc_lv<length> Vector of sc_logic, similiar to sc_bv sc_int<length>/ sc_uint<length> Two s complement representation for signed, up to 64 Bit, individual bit access, used as Integer for all operations

15 Signal Tracing Traces stored in the VCD format, which can be read by numerous digital waveviewers (e.g. gtkwave) sc_create_vcd_trace_file(char* name) opens a trace file -> the file name is <name>.vcd A trace file can be opened any time (after simulation start also) Traceable are: All public members, signals and ports Traces added by: sc_trace(sc_trace* tf,var/sig,char* name) sc_trace can be called anywhere before a delta cycle elapsed after opening All SystemC types and basic C types can be traced For user defined types an sc_trace function has to be provided sc_trace_file* tf= sc_create_vcd_file( uc_traces ); sc_trace(tf,sig1, sig1 ); sc_trace( tf, mod1->inst2->sig5, string(mod1->inst2->name())+.sig5 ); sc_trace(tf,variable, variable ); sc_close_vcd_trace_file(tf);

16 Simulation Control Functions void sc_start(); Runs simulation until no further event or sc_stop() void sc_start(sc_time time), void sc_start(double,sc_time_unit); Runs simulation until time is over or sc_stop(), can be called consecutively void sc_stop(); Stops simulation at the end of the current delta cycle, can be called from anywhere simulation can t be continued after sc_stop()

17 Static Sensitivity For static sensitivity the process activation event is bound to the process before elaboration sc_in has a implicit cast to an event Therefore the keyword is sensitive The keyword has to be used after the process registration Events can be added using the << operator SC_MODULE(my_module) sc_in<type> input1; sc_in<type> input2; sc_in<type> input3; }; sc_out<type> output; void proc_method(); SC_CTOR(my_module) } //method process registration SC_METHOD(proc_method); sensitive << input1 << input2 << input3; //there is a cast operator from sc_in -> //event which does input1->default_event()

18 Events and Dynamic Sensitivity sc_event sc_event e1; e1.notify(); e1.cancel(); e1.notify(sc_zero_time); e1.notify(1.0,sc_ms); Independend object Notification immedately, delayed or at time First event in time wins Cancel wait wait(); wait(ev); wait(e1 e2); wait(e1 & e2); wait(200,sc_ns); wait(1.0,sc_ms,e1 & e2);... Method of sc_module base class usable only in the context of thread processes Suspend process until event from sensitivity list, argument or time

19 Dynamic Sensitivity for Method Processes Method processes can t be suspended they run always in zero time until a return is reached However the next process activation time can be scheduled dynamically Therefore the method next_trigger is used This method returns immediately and the following code is still executed until a return is reached (no suspend) it influences only the next method invocation The possible arguments are similar to wait (time, event, event-list, time-out) next_trigger with an argument overrules static sensitivity list SC_MODULE(clock) sc_out<bool> out; void clk_proc() next_trigger(1.0,sc_ms); out.write(tmp); tmp=!tmp; } SC_HAS_PROCESS(clock); clock(sc_module_name, bool start=false) SC_METHOD(clk_proc); tmp=start; } private: bool tmp; };

20 SystemC Simulation Cycle Initialization (all processes called) Evaluate (select and run ready to run process) Evaluate update Non-pre-emptive threads yes ready to run processes Delta cycles Advance time yes yes Update (call pending updates scheduled in during evaluate) delayed notifications timed notifications Immediate event notification Delayed event notification Timed event notification Optional update Finish

21 Scheduler Timed and Delta Events Distinction between timed and delta events timed events are scheduled to occur at a certain simulation time in the future delta events are scheduled to occur without advancing simulation time delta events are necessary to serialize parallel actions for the simulation kernel delta time event3 at 5ns event2 at 5ns event1 at 5ns event2 at 10ns event1 at 10ns 0ns 5ns 10ns simulation time

22 SystemC - Layers

23 Architecture of a SystemC 2.x Model Separation of behavior and communication

24 SystemC Transaction Level Modeling What is TLM Modeling style for communication structures like bussystems Communication by function calls (IMC Inter Method Calls) Why TLM Fast Compact Flexible tradeoff between speed, modeling effort, accuracy and debug ability Early platform for SW development Early system exploration and performance modeling Functional verification

25 RTL vs. TLM modeling RTL simulates every event Functional Model Pin and Cycle accurate ,000 times faster TLM function call write(address,data) RTL Functional Model