Electronic System Level Design Introduction to SystemC

Transcription

1 Electronic System Level Design Introduction to SystemC Maziar Goudarzi

2 Today Program SystemC (ver. 1.0) History Highlights Design methodology A simple SystemC example 2009 ESL Design 2

3 SystemC History Synopsys ATG UC Irvine 1996 IMEC 1992 Synopsys Scenic Synopsys Fridge Frontier Design A/RT Library 1991 CoWare N2C 1997 Fixed Point Types SystemC v0.90 Sep. 99 Abstract Protocols VSIA SLD Data Types Spec (draft) SystemC v1.0 Apr. 00 SystemC v1.1 Jun ESL Design 3

4 SystemC History (cont d) SystemC v2.0 spec Feb. 01 IEEE Std Dec. 05 TLM 2.0 LRM v2.0.1 Lib Jul. 09 Abs. ports Dyn. process Timed events SystemC v1.1 Jun. 00 SystemC v2.0 LRM Jun. 03 SC 2.1 TLM 1.0 Jun. 05 SystemC v2.2 Apr. 07 TLM v2.0 Lib. Jun ESL Design 4

5 SystemC Highlights Features as an ESL Design language Modules Processes Ports Signals Rich set of port and signal types Rich set of data types Clocks Cycle-based simulation Multiple abstraction levels Communication protocols Debugging support Waveform tracing 2009 ESL Design 5

6 Conventional System Design Methodology C/C++ System Level Model Manual Conversion Refine Analysis VHDL/Verilog Results Simulation Synthesis Rest of Process 2009 ESL Design 6

7 Conv. System Design Methodology (cont d) C/C++ System Level Model Manual Conversion Refine Analysis VHDL/Verilog Results Simulation Problems Errors in manual conversion from C to HDL Disconnect between system model and HDL model Multiple system tests Synthesis Rest of Process 2009 ESL Design 7

8 SystemC Design Methodology SystemC Model Simulation Refinement Synthesis Rest of Process 2009 ESL Design 8

9 SystemC Design Methodology (cont d) Advantages Refinement methodology Written in a single language Higher productivity Reusable test benches Executable (compiled) event-driven simulation Compare to interpreted simulation Compare to compiled simulation 2009 ESL Design 9

10 SystemC (ver. 1.0) programming model Mod 1 Mod 2 Mod 3 A set of modules interacting through signals. Module functionality is described by processes ESL Design 10

11 SystemC Programming Model (cont d) System (program) debug/validation Test bench Simulation, Waveform view of signals Normal C++ IDE facilities Watch, Evaluate, Breakpoint,... sc_main() function instantiates all modules initializes clocks initializes output waveform files starts simulation kernel 2009 ESL Design 11

12 SystemC Programming Model (cont d) SystemC is C++ Any C++ statement is allowed cout, cin, file I/O, etc In principle, any C++ compiler can be used MS VC (VS-2008, 20xx!) for windows GCC for Linux 2009 ESL Design 12

13 SystemC Basic Building Block SC_MODULE( <module_name> ) { // declaring port types sc_in<int> in; // definition of processes void entry() { // circuit functionality SC_CTOR( <module_name> ) { // declaring processes SC_METHOD(entry); sensitive<<in; ; 2009 ESL Design 13

14 General Structure of SystemC Models SC_MODULE( inverter ) { sc_in<bool> in; sc_out<bool> out; void entry() { out =!in.read(); static cntr=0; cout<<cntr++<< \n ; SC_CTOR( inverter ) { SC_METHOD(entry); sensitive<<in; ; int sc_main(int, char*[]) { inverter not_gate( A_NOT_GATE ); sc_clock an_alternating_signal; not_gate.in( an_alternating_signal ); sc_start(5); 2009 ESL Design 14

15 A Simple Example: Defining a Module Complex-number Multiplier (a+bi)*(c+di) = (ac-bd)+(ad+bc)i a b c d Complex Multiplier (cmplx_mult) e f SC_MODULE(cmplx_mult) { sc_in<int> a,b; sc_in<int> c,d; sc_out<int> e,f; ESL Design 15

16 Example: Defining a Module (cont d) a b c d Complex Multiplier (cmplx_mult) e f SC_MODULE(cmplx_mult) { sc_in<int> a,b; sc_in<int> c,d; sc_out<int> e,f; void calc(); SC_CTOR(cmplx_mult) { SC_METHOD(calc); sensitive<<a<<b<<c<<d; ; void cmplx_mult::calc() { e = a*c-b*d; f = a*d+b*c; 2009 ESL Design 16

17 Completing the Design M1 input_gen a b c d M2 Complex Multiplier e f M3 display clk 2009 ESL Design 17

18 Test Bench: M1 a b M2 e M3 input_gen module input_gen c d Complex Multiplier f display clk SC_MODULE(input_gen) { sc_in<bool> clk; sc_out<int> a,b; sc_out<int> c,d; ; void generate(); SC_CTOR(input_gen) { SC_THREAD(generate); sensitive_pos(clk); void input_gen::generate() { int a_val=0, c_val=0; while (true) { a = a_val++; wait(); c = (c_val+=2); wait(); 2009 ESL Design 18

19 Test Bench: M1 a b M2 e M3 display module input_gen c d Complex Multiplier f display SC_MODULE(display) { sc_in<int> e,f; ; void show(); SC_CTOR(display) { SC_METHOD(show); sensitive<<e<<f; void display::show() { clk cout<<e<< + <<f<< i\n ; 2009 ESL Design 19

20 Putting it all together: sc_main function M1 a b M2 e M3 input_gen c d Complex Multiplier f display #include <systemc.h> int sc_main(int, char*[]) clk { input_gen M1( I_G ); cmplx_mult M2( C_M ); display M3( D ); sc_signal<int> a,b,c,d,e,f; sc_clock clk( clk,20,0.5); M1.clk(clk.signal()); M1.a(a); M1.b(b); M1.c(c); M1.d(d); M2.a(a); M2.b(b); M2.c(c); M2.d(d); M2.e(e); M2.f(f); M3.e(e); M3.f(f); sc_start(100); return 0; 2009 ESL Design 20

21 How to Compile & Run It? 1. Compile SystemC class library to generate systemc.lib (required just once) 2. Create a MS VC++ project & add your source files 3. Add systemc.lib to your project 4. Add c:\systemc-2.0.1\include to the default include directory (in project-settings) 5. Enable Run-Time Type Information (RTTI) (in your project-settings) 6. Compile & run. Enjoy SystemC! 2009 ESL Design 21

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24 The Generated Output 2009 ESL Design 24

25 What we learned today What s SystemC SystemC advantages SystemC programming model Modeling hardware in SystemC 2009 ESL Design 25

26 Other notes: SystemC Installation SystemC source files Course web-page under resources tab Our reference version: SystemC unless otherwise specified 2009 ESL Design 26

27 Other Notes Exercise (do before next lecture): Download and compile SystemC sources Compile and run (simulate) today simple example 2009 ESL Design 27