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1 KDEC Technical Seminar SystemC Overview & Example : 8-Bit RISC System Design KDEC Kook,ilho goodkook@nms.anslab.co.kr AnsLab Co. 1

2 KDEC Technical Seminar SystemC Overview & Example : 8-Bit RISC System Design KDEC Kook,ilho goodkook@nms.anslab.co.kr AnsLab Co. Typical SoC Device (source: ARM Ltd.) 1

3 SoC Design Flow Reference:Rosenfield (SystemC,Europe) Design Process Today Refinement Manual Translation System Level Design Hardware and Software Algorithm Development Processor Selection Done mainly in C/C++ C/C++ Environment Refinement IC Development Hardware Implementation Decisions Done mainly in Verilog/VHDL EDA Environment The Verification Process $$ Emulation / Prototyping Software Code development RTOS details Done mainly in C/C++ C/C++ Environment Reference: Wang(Synopsys) Productivity Gaps 2

4 HDL Based Flow C/C++ 4. Hand over specification document HDL 1. Conceptualize 2. Simulate in C++ 3. Write specification document 5. Understand 6. (Re)Implement in HDL 7. (Re)Verify 8. Synthesize from HDL Problems:Written specifications are incomplete and inconsistent Translation to HDL is time consuming and error prone Reference: Wang(Synopsys) C/C++ Based Flow C/C++ 1. Conceptualize 2. Simulate in C++ 3. Write specification document 4. Hand over Executable specification Testbench Written specification 5. Understand 6. Refine in C++ 7. Verify reusing testbenches 8. Synthesize from C++ Turning Algorithms into the Right Architectures for ASICs quicker and better Reference: Wang(Synopsys) C/C++ 3

5 Why C/C++ Based Design Specification between architect and implementer is executable High simulation speed at the higher level of abstraction Refinement, no translation into HDL (no semantic gap ) Testbench re-use C/C++ C/C++ System Architect SoC Design Marketing & Sales HDL Software Designer Reference: Wang(Synopsys) Hardware Designer Using Executable Specifications Ensure COMPLETENESS of Specification Even components(e.g. Peripherals) are so COMPLEX Create a program that Behave the same way as the system Avoid UNAMBIGUOUS Interpretation of the Specification Avoids unspecified parts and inconsistencies IP customer can evaluate the functionality up-front Validate system functionality before implementation Early feedback from customer Create early model and Validate system performance Refine and Test the implementation of the Specification Test automation improves Time-To-Market 4

6 Executable Spec Motivation Customer System Paper Spec HDL Design Netlist Layout Silicon Verification, Error Checking Bottleneck (SystemC TM ) Test automation: C-Interface (PLI/FLI), Coverage Test Customer System Executable Spec HDL Design Netlist Layout Silicon Reference: Mayer(Infineon) Executable Spec Potential Example: Cerberus_FPI(ca.6000 Lines of Code) Reference: Infineon 5

7 Can C++ be used as is? C++ does not support Hardware style communication Signals, protocols, etc. Notion of time Time sequenced operations. Concurrency Hardware and systems are inherently concurrent, i.e. they operate in parallel. Reactivity Hardware is inherently reactive, it responds to stimuli and is in constant interaction with its environment, which requires handling of exceptions. Hardware data types Bit type, bit-vector type, multi-valued logic type, signed and unsigned integer types and fixed-point types. SystemC vs. SpecC Constructs to model system architecture Hardware timing Concurrency Adding these constructs to C SystemC C++ Class library Standard C/C++ Compiler : bcc, msvc, gcc, etc SpecC Language extension : New keywords & Syntax Translator for C 6

8 SystemC is C++ Class Library use for Cycle-Accurate model for Software Algorithm Hardware Architecture Interface of SoC (System-on-Chip) System-level designs Executable Specification Purely Algorithm /Software in C++ High Level Abstract Hardware Model in SystemC C++ Software Model Behavioral Level Hardware Model in SystemC C++ Software Model Register Transfer Level Hardware Model in SystemC C++ Software Model HW/SW partitioning C++ Programs Reference: Wang(Synopsys) What is SystemC? SystemC is a C++ Class library Include any C++ programs, libraries, encapsulation... a methodology for modeling SoC designs consisting DSPs, ASICs, IP-Cores, Interfaces,... SystemC also enables Modeling at high level of abstraction (e.g. communication protocols) Refinement to hardware Software modeling - interrupts, exception handling System wide verification Hardware/Software co-verification IP exchange SystemC provides all the advantages of Verilog and VHDL Concurrent processes (e.g. methods, threads, clocked threads) Concept of a clock Wide variety of bit-true true data types SystemC IS NOT Another C++ dialect -> it is C++ Just for hardware modeling only -> you can model hardware AND software in C++ with SystemC 7

9 Short History of SystemC TM Scenery V0.9 Launches 9/27/1999 V1.0 Release 3/ DAC Paper fixed pt datatypes HDL constructs Source Code User Guide Reference Manual Discussion Forum All available from Reference: Wang(Synopsys) SystemC TM Highlights (1) Support Hardware-Software Co-Design Interface in a C++ environment Modules Container class includes hierarchical Entity and Processes Processes Describe functionality, Event sensitivity Ports Single-directional(in, out), Bi-directional(inout) mode Signals Resolved, Unresolved signals Rich set of port and signal types Rich set of data types All C/C++ types, 32/64-bit signed/unsigned, fixed-points, MVL, user defined 8

10 SystemC TM Highlights (2) Interface in a C++ environment (continued) Clocks Special signal, Timekeeper of simulation and Multiple clocks, with arbitrary phase relationship Cycle-based simulation High-Speed Cycle-Based simulation kernel Multiple abstraction levels From untimed from high-level functional model To detailed clock cycle accuracy RTL model Communication Protocols Debugging Supports Run-Time error check Waveform Tracing Supports VCD, WIF, ISBD SystemC and User Module User Module User Module #1 #1 User Module User Module #2 #2... User Module User Module #N #N Event & Signal I/F C++ Class Library Events Hardware Simulation Kernel (Event Scheduler) SystemC SystemC Executable Specification Executable Specification 9

11 System Design Methodology Current Manual Conversion from C to HDL Creates Errors Disconnect Between System Model and HDL Model Multiple System Tests SystemC (Executable-Specification) Refinement Methodology Written in a Single Language Current Methodology C/C++ System Level Model - Manual Conversion Creates Errors - Disconnect Between System Model and HDL Model - Multiple System Tests Refine Analysis VHDL/Verilog Result Simulation Synthesis 10

12 SystemC Methodology SystemC Model Simulation - Refinement Methodology : Not convert C to HDL for timing constructs - Written in Single Language from System to RTL model Refinement - Less effort to convert Synthesizable HDL Synthesis Design Flow in SystemC UTF UnTimed Functional Design Exploration Performance Analysis HW/SW partitioning TF Refine Timed Functional HW/SW Partition Multi-Tasking Abstract RTOS Inter Process comm. Scheduling/Priority Abstract RTOS BCA Bus Cycle Accurate Refine Target RTOS Target Code RTL Cycle Accurate Synthesizable 11

13 System Abstraction Level Untimed Functional (UTF) Level Decompose system into functional module Abstract communication channels Data transactions without notion of TIME Timed Functional (TF) Level Functional process can be assigned a RUN-TIME Timed but NOT Clocked Bus-Cycle Accurate (BCA) Level Transactions on the bus cycle-accurately Some behavior left at untimed level Cycle Accurate (CA) Level Behavior is clock cycle accurate Ready to RTL HDL System Design Flow Untimed Functional (UTF) Level Purpose Executable Spec. of a complete system Algorithmic behavior Functional decomposition Methodology NO distinction of HW and SW Remote Procedure Call (RPC) protocol Data Transaction : Abstract Port Minimal concurrent behavior 12

14 System Design Flow Timed Functional (TF) Level Purpose Performance modeling Time budgeting Methodology Process may be assigned a Rum-Time Timed and Untimed System expression TIME is used to express duration only Process execution by RPC chain and concurrent thread Design exploration : HW/SW partitioning System Design Flow HW/SW Partitioning HW Mapping Architecture Transform functional module into cycle accurate Refine Communication protocol SW Module Partition Tasks Inter-task communication Synchronization Use RTOS (Real-Time Operating System) 13

15 System Design Flow Bus-Cycle Accurate (BCA) Level Purpose Model Hardware with Bus Architecture Methodology Abstract ports refined to Bus ports Bus : Data, Address, Control terminals Protocol : No-, Enable-, Full-Handshake Processors/Bus controllers are synchronized using clock Modules are modeled bus cycle-accurately, but some behavior System Design Flow Cycle Accurate (CA) Level Synthesizable RTL 14

16 Getting Started Compiler gcc (version ) native compiler Visual C++, SUN cc Debugger gdb, ddd lint, profiler, memory access checking quantify, purify Compile and Run class library and simulation kernel header files libraries executable specification your standard C/C++ development environment compiler linker debugger... make a.out... executable = simulator DSP Interface IP-Core ASIC source files for system and testbenches 15

17 SystemC Design Unit Module Ports and Signals Constructor for Process Sensitize to signals Hierarchy of Module Module instaciat Port mapping Module Module Basic building block of design partitioned C++ Class, similar to entity (VHDL) or module (Verilog) SC_MODULE(module_name) { } // Declare Module Ports // Declare Module Signals, Member functions // Module Construct : SC_CTOR // Process Construct and Sensitize to signal: // SC_METHOD, SC_THREAD, SC_CTHREAD // Sub-Module Instantiate and Port Mapping // Initialize of Module Signals 16

18 Module Ports Pass data to or from processes of a module Input port sc_in<type> port_name; Output port sc_out<type> out_port_name; Bi-Directional port sc_inout inout<type> inout_port_name _port_name; Module Signals Local to a Module Used to connect ports of sub-modules sc_signal<type> signal_name; 17

19 Internal Data Storage Local variable Cannot be used to connect ports Storage types C++ type SystemC type User defined type Module Constructor Similar to architecture or module body Processes and/or Sub-module instantiated module_name passed when instantiated to identify the module SC_MODULE(module_name) { } SC_CTOR(module_name) // Create Module { } // Processes and Senstize // Sub-Module Instantiate // Initialize Local signals and Internal storage 18

20 Sub-Module Instantiate Module Instantiate module_type Inst_module ( label ); Module Instantiate as pointer module_type *pinst_module _module; // Instanciate in the Module constructor SC_CTOR pinst_module = new module_type( label label ); Sub-Module Port Mapping Positional Port Mapping Inst_module << s << c << q; (*pinst_module _module)( )(s,c,q); Named Port Mapping Inst_module.a(s); Inst_module.b(c); Inst_module.q(q); pinst_module -> a(s); pinst_module -> b(c); pinst_module -> q(q); 19

21 Hierarchy of Modules sample din s1 coeff c1 dout cout c s q filter filter mult a b m1 q SC_MODULE(filter) { // Sub-modules : component sample *s1; coeff *c1; mult *m1; sc_signal<sc_ sc_uint 32> > q, s, c; // Signals // Module constructor : architecture body SC_CTOR(filter) { // Instantiate Sub-Modules and Port mapping s1 = new sample ( s1 ); s1->din(q); // Named Mapping s1->dout(s); } } c1 = new coeff( c1 ); c1->out(c); m1 = new mult ( m1 ); (*m1)(s, c, q); // Positional Mapping Processes Member function of SC_MODULE Provides functionality of Module Identify to SystemC kernel (Simulator) Call and Execute : Sensitive to Type of Processes (execute method) Method : SC_METHOD Thread : SC_THREAD Clocked Thread : SC_CTHREAD 20

22 Process and Sensitize to System C VHDL #include systemc.h SC_MODULE(dff) { sc_in<bool> sc_in<bool> sc_out<bool> }; din; clock; dout; void doit(); // Member function SC_CTOR(dff dff) ) { SC_METHOD(doit doit); // Process sensitive_pos << clock; // Sensitize to } void dff::doit() { // Member function as Process body dout = din; } entity dff is port ( din, clock : in bit; dout : out bit ); end dff; architecture dff of dff is begin doit : process(clock) Sensitivity List begin if (clock( clock event and clock= 1 ) ) then dout <= din; end if; end process; end dff; Initialize Module When a Module instantiated, Module name passed to identify module Module Constructor creates and initializes this Module SC_MODULE(ram) { sc_in<int> addr; // Input port sc_in<int> datain; // Input port sc_in<bool> rwb; // Input port sc_out<int> dout; // Output port int memdata[64]; // Local memory storage, Created when instantiated int i; void ramread(); void ramwrite(); SC_CTOR(ram) { SC_METHOD(ramread) // Memory Read Process sensitive << addr << rwb; SC_METHOD(ramwrite) // Memory Write Process sensitive << addr << datain << rwb; } } for (i=0; i++; i<64) // Initialize Local Storage when instantiated memdata[i] = 0; 21

23 Lab1. Counter count u_count u_count sc_clock() din dout load clock 20 DIN DOUT LOAD CLOCK TestBench : count_tb TestBench : count_tb count_stim din dout load clock u_count_stim u_count_stim display dout u_display u_display Components DUT Module: count Up counter Init. Data Loadable Stimuli Generator : count_stim Load control Init. Data DUT monitor : display Monitor DUT output TestBench : count_tb Clock generator : sc_clock() Run Simulator : sc_start() Lab1. Count How to Compile and Link Requirement (PC version) Win32 (Windows NT/9x/2000) MicroSoft Visual C/C SystemC 1.0 To compile and Link with MicroSoft Visual C/C Create a project count as Win32 consol application Add preprocessor definition : /D SC_INCLUDE_FX Enable C++ RTTI(Run-Time Type Information) option : /GR Add SystemC include path : /I your_systemc/src Link with SystemC Library systemc.lib To get Lab1. Count source 22

24 SystemC IP: Ans_RISC817 Feature 55 single word 16-bit instruction 8-bit data interrupt capability Stack on data memory Direct,indirect and relative addressing mode 64Kx16(banked) program memory 256x16(banked) data memory 32 IO Address space(expandable) Ans_RISC817 RISC IP designed with SystemC Ans_RISC817 Core Timing accurate model Program ROM Data RAM Expandable Custom peripheral Dynamic linking with core executable Software environment Assembler Debugger embedded into core executable 23

25 Development System Core Monitoring VCD Peripheral (DLL) Ans_RISC Core Debugger Line Assembler Dis-Assembler Trace/Go Prog. Download Command Line User Interface Program ROM Executable Executable Program ROM Image Assembler TestBench RISC Simulator Test Modules RISC Core Peripheral Monitor (Trace) Debugger Basic Tool for RISC Test & S/W Development User interface Embedded in the executable int sc_main(int argc, char* argv[]) { sc_clock CLK("clk", CLK_PERIOD); sc_signal<sc_bit> rst; sc_signal<sc_bv<8> > io_in; // UUT : Ans_RISC817 Core ans_risc817 u_ans ans_risc817("u risc817("u_ans ans_risc817"); u_ans_risc817.clk(clk); u_ans_risc817.clk_ext(clk_ext); u_ans_risc817.rst(rst); // Peripheral ans_risc817 risc817_peri u_ans ans_risc817 risc817_peri peri("u_ ("u_ans ans_risc817 risc817_peri peri"); u_ans_risc817_peri.clk(clk_adc); u_ans_risc817_peri.rst(rst); u_ans_risc817_peri.int1(int1); // Monitor monitor u_monitor("u_monitor"); u_monitor.clk(clk); // Debugger Debug( &u_ans ans_risc817, &p_download, &rst& rst); return(0); } 24

26 Debugger Command Line UI get command string: gets() command line interpreter Generate Stimuli Reset Program ROM download Initialize/Run sc_initialize() sc_start() void Debug( &u_ans ans_risc817, &p_download, &rst& rst); { *p_download = false; *rst = (sc_bit)'1'; sc_start(clk_period); *p_download = true; sc_start(clk_period); sc_initialize(); *rst = (sc_bit)'0'; sc_start(clk_period*4); while(true) // Command line loop forever { printf(" ("Ans Ans_RISC817>"); // Prompt Str. gets(buff); // Read Command Line switch(buff[0]) { case 'A' : case 'a' : // Assemble... break; case 'q': return; break; } } return; default: } break; Executing Ans Ans_RISC817 _RISC817 25

27 Waveform Trace VCD output Hierarchical Tracing // VCD Monitor ///////////////////////////////////// sc_trace_file* tf; tf = sc_create_vcd_trace_file("ans_risc817"); sc_trace(tf, t_rst, "RST"); sc_trace(tf, t_clk, "CLK"); sc_trace(tf, u_ans_risc817.u_prog_count->pc, "PC"); View Waveform :GTKWave 26

28 Runtime Demo-Q&A Tracing Signal sc_signal Tracing Variable Understanding Simulation Kernel Debugging methodology Q&A 27

29 File: Edit , 10:09: SystemC Example 6 "Counter" Contents: count_tb.cpp - TestBench count.h, count.cpp - Core "counter" count_stim.h, count_stim.cpp - Stimili generator for Test display.h, display.h - Output debug ///////////////////////////////////////////////////////////////// 21 // Filename : count_tb.cpp 22 // Comment : SystemC example - Counter Stimulus 23 // #include "count.h" 26 #include "count_stim.h" 27 #include "display.h" int sc_main(int argc, char* argv[]) 30 { 31 sc_signal<bool> LOAD; 32 sc_signal<int> DIN, DOUT; 33 sc_clock CLOCK("clock", 20); // clock int sim_time = 0; if (argc==2) 38 sim_time = atoi(argv[1]); if (sim_time==0) 41 sim_time = 1000; count u_count ("count"); 44 u_count.load(load); 45 u_count.din(din); 46 u_count.dout(dout); 47 u_count.clock(clock); count_stim u_count_stim("count_stim"); 50 u_count_stim.load(load); 51 u_count_stim.din(din); 52 u_count_stim.dout(dout); 53 u_count_stim.clock(clock); display u_display("display"); 56 u_display.load(load); 57 u_display.din(din); 58 u_display.dout(dout); 59 u_display.clock(clock); // VCD Monitor ///////////////////////////////////// 63 sc_trace_file* tf; 64 tf = sc_create_vcd_trace_file("counter"); sc_trace(tf, CLOCK, "CLOCK"); 67 sc_trace(tf, LOAD, "LOAD"); 68 sc_trace(tf, DIN, "DIN"); 69 sc_trace(tf, DOUT, "DOUT"); sc_initialize(); 72 sc_start(sim_time); sc_close_vcd_trace_file(tf); return(0); 77 } ///////////////////////////////////////////////////////////////// 81 // Filename : count.h 82 // Comment : SystemC example - Counter 83 // #include "systemc.h" #ifndef COUNT_H 88 #define COUNT_H SC_MODULE(count) 91 { 92 sc_in<bool> load; Page: 1

30 File: Edit , 10:09:28 93 sc_in<int> din; 94 sc_in<bool> clock; // input ports 95 sc_out<int> dout; // output port int count_val; // internal data storage void count_up(); SC_CTOR(count) 102 { 103 SC_METHOD(count_up); // Method process 104 sensitive_pos << clock; // Sensitive to Rising edge clock 105 } 106 }; #endif ///////////////////////////////////////////////////////////////// 112 // Filename : count.cpp 113 // Comment : SystemC example - Counter 114 // #include "count.h" void count::count_up() 119 { 120 if (load) 121 { 122 count_val = din; 123 } 124 else 125 { 126 count_val = count_val + 1; // Read/Write of local storage 127 } 128 dout = count_val; // Write to Output port 129 } ///////////////////////////////////////////////////////////////// 133 // Filename : count_stim.h 134 // Comment : SystemC example - Counter Stimulus 135 // #include "systemc.h" SC_MODULE(count_stim) 140 { 141 sc_out<bool> load; 142 sc_out<int> din; 143 sc_in<bool> clock; 144 sc_in<int> dout; void stimgen(); SC_CTOR(count_stim) 149 { 150 SC_THREAD(stimgen); 151 sensitive_pos(clock); 152 } 153 }; ///////////////////////////////////////////////////////////////// 157 // Filename : count_stim.cpp 158 // Comment : SystemC example - Counter Stimulus 159 // #include "count_stim.h" void count_stim::stimgen() 164 { 165 while(true) // infinite loop 166 { 167 load = true; 168 din = 0; // counter load zero wait(); // count up, value = 1; 171 load = false; wait(); // count up, value = 2; 174 wait(); // count up, value = 3; 175 wait(); // count up, value = 4; 176 wait(); // count up, value = 5; 177 wait(); // count up, value = 6; 178 wait(); // count up, value = 7; 179 } 180 } ///////////////////////////////////////////////////////////////// 184 // Filename : display.h Page: 2

31 File: Edit , 10:09: // Comment : SystemC example - Counter 186 // #include "systemc.h" SC_MODULE(display) 191 { 192 sc_in<bool> load; 193 sc_in<int> din; 194 sc_in<bool> clock; // input ports 195 sc_in<int> dout; // output port void display_count(); SC_CTOR(display) 200 { 201 SC_METHOD(display_count); 202 sensitive(dout); 203 } 204 }; ///////////////////////////////////////////////////////////////// 208 // Filename : display.cpp 209 // Comment : SystemC example - Counter 210 // #include "display.h" void display::display_count() 215 { 216 cout << "Count = " << dout << " at " << sc_time_stamp() << "\n"; 217 } Page: 3