PowerSC: a SystemC Framework for Power Estimation

Transcription

1 6th NASCUG Meeting February, 2007 San Jose, CA PowerSC: a SystemC Framework for Power Estimation Felipe Klein (speaker) Guido Araujo Rodolfo Azevedo Computer Systems Laboratory Institute of Computing UNAMP 1

2 Outline The Power Consumption Concern PowerSC Methodology Power Modeling with PowerSC Technology Libraries Support Experimental Results Conclusions and Ongoing Work 2

3 Power Consumption: A Growing Concern SOC Consumer Stationary Power Consumption Trends Switching Power, Logic Leakage Power, Logic Switching Power, Memory Leakage Power, Memory Source: ITRS Update

4 PowerSC Overview SystemC has no support for power modeling Power aware extension of SystemC classes Constructs for power modeling Automatic gathering of switching activity transition density, static probability, spatial correlation 4

5 PowerSC Methodology Design Refinement PowerSC Library SystemC Design Config. Files SystemC Library C++ Compiler PowerSC Exec. Specification SystemC Exec. Specification Simulation for Power Usual Simulation Reports Reports 5

6 PowerSC Methodology Design Refinement SystemC Design PowerSC Library Config. Files SystemC Library C++ Compiler PowerSC Exec. Specification SystemC Exec. Specification Simulation for Power Usual Simulation Reports Reports PowerSC Flow 6

7 Using PowerSC is Painless No code rewriting sc to psc data types Include the powersc.h Set a compiler directive g++ DPOWER_SIM Call to some PSC_* macros 7

8 Usage Example main.cpp example.h #include "example.h" #include <systemc.h> #include <powersc.h> SC_MODULE(MyDesign) { sc_in<sc_uint<32> > input; sc_out<sc_uint<16> > output; sc_signal<sc_uint<32> > temp; }; SC_MODULE(testbench) { sc_in_clk clk; MyDesign *dut; sc_signal<sc_uint<32> > in; sc_signal<sc_uint<16> > out; SC_CTOR(testbench) { // instantiate and bind } }; void go(const char *infile) { sc_clock clk("clk", ); } testbench tb0("tb0"); tb0.clk(clk); sc_start( 1); int sc_main(int argc, char **argv) { const char *infile; PSC_FULL_SAMPLING; go(infile); PSC_REPORT_SWITCHING_ACTIVITY; PSC_REPORT_POWER; } 8

9 Usage Example example.h #include <systemc.h> #include <powersc.h> no data types main.cpp redeclared #include "example.h" SC_MODULE(MyDesign) { sc_in<sc_uint<32> > input; sc_out<sc_uint<16> > output; sc_signal<sc_uint<32> > temp; }; SC_MODULE(testbench) { sc_in_clk clk; MyDesign *dut; sc_signal<sc_uint<32> > in; sc_signal<sc_uint<16> > out; SC_CTOR(testbench) { // instantiate and bind } }; void go(const char *infile) { sc_clock clk("clk", ); } testbench tb0("tb0"); tb0.clk(clk); sc_start( 1); int sc_main(int argc, char **argv) { const char *infile; PowerSC PSC_FULL_SAMPLING; macros go(infile); PSC_REPORT_SWITCHING_ACTIVITY; PSC_REPORT_POWER; } 9

10 Usage Example (contd.) powersc.h #include "debug_power.h" #include "psc_uint.h" #include "psc_int.h" #include "psc_signal.h" using psc_dt::psc_uint; using psc_dt::psc_int; #ifdef POWER_SIM #define sc_uint psc_uint #define sc_int psc_int #define sc_signal psc_signal #define PSC_REPORT_SWITCHING_ACTIVITY \ psc_objinfo_base::repository.print_entries() #define PSC_REPORT_POWER \ psc_objinfo_base::cells.power_report() #else #define PSC_REPORT_SWITCHING_ACTIVITY #define PSC_REPORT_POWER #endif 10

11 Usage Example (contd.) powersc.h #include "debug_power.h" #include "psc_uint.h" #include "psc_int.h" #include "psc_signal.h" PowerSC flow g++ DPOWER_SIM using psc_dt::psc_uint; using psc_dt::psc_int; #ifdef POWER_SIM #define sc_uint psc_uint #define sc_int psc_int #define sc_signal psc_signal Usual flow g++ DNO_POWER_SIM #define PSC_REPORT_SWITCHING_ACTIVITY \ psc_objinfo_base::repository.print_entries() #define PSC_REPORT_POWER \ psc_objinfo_base::cells.power_report() #else #define PSC_REPORT_SWITCHING_ACTIVITY #define PSC_REPORT_POWER #endif 11

12 Power Modeling Support C++ classes for power modeling different levels of abstraction psc_macromodel: base class to be derived get_power() init_power_map() psc_macromodel_parms macromodeling technique specific PSC_* macros 12

13 Power Modeling Overview Base classes Modeling power for technique #1 Modeling power for technique #2 SystemC design 13

14 Power Modeling Overview Base classes Modeling power for technique #1 Modeling power for technique #2 SystemC design design instrumentation ~mydesign() { } repository registration 14

15 Macromodeling Example Add32 Add32 design #include "rtl_macromodel Add32.h" SC_MODULE(Add32) { sc_in<sc_uint<32> > a; sc_in<sc_uint<32> > b; sc_out<sc_uint<32> > out1; void thread_combo(); PSC_MACROMODEL_Add32; SC_CTOR(Add32); }; 15

16 Macromodeling Example Add32 Add32 design #include "rtl_macromodel Add32.h"defined within SC_MODULE(Add32) { sc_in<sc_uint<32> > a; sc_in<sc_uint<32> > b; sc_out<sc_uint<32> > out1; void thread_combo(); PSC_MACROMODEL_Add32; SC_CTOR(Add32); }; this file #ifdef POWER_SIM #define PSC_MACROMODEL_Add32\ static const char *celltype;\ static psc_macromodel_add32_eqtab power_model;\ ~Add32() #else #define PSC_MACROMODEL_Add32 #endif 16

17 Technology Libraries in C++ Goals: multiple levels of abstraction unified modeling framework power characterization process in SystemC Libraries in Synopsys Liberty format Helper tools for automatic translation 17

18 Tools for Automatic Conversion Tech. Library (e.g., tsmc.lib) tsmc.h lib2psclib tsmc.psclib psclib2sc tsmc.cpp Part Library Base Part Library SC_RTL vlog2sc SC_RTL SC_GATES V_GATES 18

19 SystemC Gate level Example Add32 #include "tsmc.h" technology library SC_MODULE(Add32) { sc_in<bool> a[32]; sc_in<bool> b[32]; sc_out<bool> out1[32]; xor2_1 *I330; and2_1 *I331; SC_CTOR(Add32) { I330 = new xor2_1( "I330" ); I330 >op( out1[0] ); I330 >ip1( a[0] ); I330 >ip2( b[0] ); more PSC macros cells from the technology library I331 = new and2_1( "I331" ); I331 >op( N305 ); I331 >ip1( b[0] ); I331 >ip2( a[0] ); } PSC_OBJ_ALIAS(N305, "N305"); }; #define Add32 Add32_wrapper 19

20 Experimental Results Design (RTL) Add32 MulS16 DiffEq Crossover1 Crossover2 Crossover3 Technique (Avg. Error) EqTab 3DTab ehd 15% 13% 25% 12% 24% 57% 16% 26% 87% 16% 21% 48% 13% 22% 61% 13% 21% 62% Gate level errors: ~4% for approximately 20 different FUs as compared to Synopsys Power Compiler Simulation overhead: ~7 times slower than pure functional descriptions 20

21 Conclusions Power consumption is a key metric for real life designs SystemC has been extended to support power modeling PowerSC A unified modeling framework was proposed Integration to ArchC simulators is an ongoing work 21

22 Thank You! By the way 1st LASCUG Meeting (tentative) co located with SBCCI September 2007 Rio de Janeiro Brazil 22

23 EXTRAS 23

24 Macromodeling Example (contd.) Specializing classes for a technique class psc_macromodel_parms_add32_eqtab : public psc_macromodel_parms { protected: double m_d_pin; double m_d_din; vector<double> m_bitwise_dens; }; parameters for this technique class psc_macromodel_add32_eqtab : public psc_macromodel { public: overloaded void init_power_map(); double get_power(const psc_macromodel_parms & p); methods }; continued from slide 16 24

25 Macromodeling Example (contd.) Repository registration upon destruction Add32::~Add32() { psc_macromodel_parms_add32_eqtab parms(pin, din, bitwise_dens); power = power_model.get_power(parms); psc_cell_power_info info(name(), celltype); info.set_level(psc_rt_level); info.set_power( power ); psc_pin_power_info pwr_a(_p_a >get_id()); psc_pin_power_info pwr_b(_p_b >get_id()); psc_pin_power_info pwr_out1(_p_out1 >get_id()); info.add(pwr_a); info.add(pwr_b); info.add(pwr_out1); } PSC_INSERT_CELL(info); 25

26 Gate level Add32_wrapper a multiport (one bit for each signal) Add32_wrapper a b a[0] a[31] Add32 (gates) exec_i b out1 exec_o 32 out1 32 a, b and out1 are declared as sc_uint<32>! Modules using Add32 cannot bind directly to the gate level description's ports! continued from slide 19 26

27 Modeling a SoC (Example) I Cache ASIP core SRAM Main Memory (DRAM) IP core Bus D Cache IP core Bus Processor (e.g., PowerPC Cache ArchC SystemC (TLM) SystemC (RTL/Behavioral) SystemC (TLM) 27