Assertion-Based Verification

Transcription

1 Assertion-Based Verification Introduction to SVA Harry Foster Chief Scientist Verification

2 Session Overview After completing this session you will... Learn the structure of the SVA language Lean how to construct sequence Lean how to construct properties

3 Specifying Design Intent Assertions allow us to specify design intent in a way that lends itself to automation reset_n req0 req1 Arbiter grant0 grant1 // Assert that the grants for our simple arbiter are mutually exclusive

4 Identifying the Error Condition For our arbiter example, we can write a Boolean expression for the error condition, as follows: reset_n req0 req1 Arbiter grant0 grant1 (grant0 & grant1) // error condition

5 Checking the Error Condition before Assertions Doesn t lend itself to automation. module arbiter (, rst_n, req0, req1, grant0, grant1);... or negedge rst_n) begin if (rst_n!= 1 b0) if (grant0 & grant1) $display ( ERROR: Grants not mutex );... endmodule Error Condition Boolean Expression

6 IEEE 1800 SystemVerilog Mutex Example grant0 and grant1 must be mutually exclusive grant0 grant1 error assert property ) disable iff (rst_n)!(grant0 & grant1));

7 Assertion Units Directives (assert, cover) Properties Sequences (Sequential Expressions) Boolean Expressions Checker packaging assert, assume, cover Specification of behavior; desired or undesired How Boolean events are related over time True or false

8 assert property ) disable iff (~rst_n)!(grant0 & grant1)); Assertion Units Directives (assert, cover) Properties Sequences (Sequential Expressions) Boolean Expressions rst_n!(grant0 & grant1) error

9 assert property ) disable iff (~rst_n)!(grant0 & grant1)); Assertion Units Directives (assert, cover) Properties Sequences (Sequential Expressions) Boolean Expressions rst_n!(grant0 & grant1) error

10 assert property ) disable iff (~rst_n)!(grant0 & grant1)); Assertion Units Directives (assert, cover) Properties Sequences (Sequential Expressions) Boolean Expressions rst_n!(grant0 & grant1) error

11 SVA provides a mechanism to asynchronously disable a property during a reset using the SVA disable iff clause assert property (@(posedge ) disable iff (~rst_n)!(grant0 & grant1));

12 Sequences So far we have examined simple assertions A Boolean expression must hold at every clock We now we introduce SVA sequences Multiple Boolean expressions are evaluated in a linear order of increasing time Assertion Units Directives (assert, cover) Properties Sequences (Sequential Expressions) Boolean Expressions

13 Sequence Temporal delay ## with integer start ##1 transfer start transfer

14 Sequence Temporal delay ## with integer start ##2 transfer start transfer

15 Sequence Temporal delay ## with range [m:n] start ##[0:2] transfer start transfer

16 Sequence Temporal delay ## with range [m:n] start ##[0:2] transfer start transfer

17 Sequence Temporal delay ## with range [m:n] start ##[0:2] transfer start transfer

18 Sequence Consecutive repetition [*m] or range [*m:n] Use $ to represent infinity start[*2] ##1 transfer start transfer

19 Sequence Consecutive repetition [*m] or range [*m:n] Use $ to represent infinity start[*1:2] ##1 transfer start transfer

20 Sequence Consecutive repetition [*m] or range [*m:n] Use $ to represent infinity start[*1:2] ##1 transfer start transfer

21 Sequence Consecutive repetition [*m] or range [*m:n] Use $ to represent infinity start[*1:2] ##1 transfer start transfer Note: This also matches the sequence specification!!!!

22 Sequence Non-consecutive repetition [=m] or [=m:n] start[=2] ##1 transfer start transfer [*0:$] represents zero to infinity start[=2]!start[*0:$] ##1 start ##1!start[*0:$] ##1 start ##1!start[*0:$]

23 Sequence Goto non-consecutive repetition [->m] or [->m:n] start[->2] ##1 transfer start transfer [*0:$] represents zero to infinity start[->2]!start[*0:$] ##1 start ##1!start[*0:$] ##1 start

24 Properties Assertion Units Directives (assert, cover) Properties Sequences (Sequential Expressions) Boolean Expressions

25 Properties Overlapping sequence implication operator -> ready ##1 start -> go ##1 done ready start go done assertion property ) ready ##1 start -> go ##1 done );

26 Properties Non-overlapping sequence implication operator => ready ##1 start => go ##1 done ready start go done NOTE: A => B is the same as A -> ##1 B

27 Fair Arbitration Scheme Example Asserting that an arbiter is fair To be fair, a pending request for a particular client should never have to wait more than two arbitration cycles Otherwise, the arbiter unfairly issued multiple grants to a different client req[0] req[1] Arbiter gnt[0] gnt[1]

28 Fair Arbitration Scheme Example a_0_fair: assert property ) disable iff (reset_n) not ( $rose(req[0]) ##1 (!gnt[0] throughout (gnt[1])[->2]))); req[0] req[1] Arbiter gnt[0] gnt[1] req[0] gnt[0] gnt[1]

29 Named properties and sequences To facilitate reuse, properties and sequences can be declared and then referenced by name Can be declared with or without parameters sequence s_op_retry; (req ##1 retry); endsequence sequence s_cache_fill(req, done, fill); (req ##1 done [=1] ##1 fill); endsequence

30 Named properties and sequences sequence s_op_retry; (req ##1 retry); endsequence sequence s_cache_fill(rdy, done, fill); (rdy ##1 done [=1] ##1 fill); endsequence assert property ) disable iff (!reset_n) s_op_retry => s_cache_fill (my_rdy,my_done,my_fill));

31 Named properties and sequences property p_en_mutex(en0, ) disable iff (~reset_n) ~(en0 & en1); endproperty assert property (p_en_mutex(en[0], en[1]));

32 Action blocks An SVA action block specifies the actions that are taken upon success or failure of the assertion The action block, if specified, is executed immediately after the evaluation of the assert expression assert property ) disable iff (reset)!(grant0 & grant1) ) else begin // action block fail statement $error( Mutex violation with grants. ); end

33 System functions $onehot (<expression>) - Returns true if only one bit of the expression is high $onehot0 (<expression>) - Returns true if at most one bit of the expression is high $isunknown (<expression>) - Returns true if any bit of the expression is X or Z - This is equivalent to ^<expression> === bx

34 System functions $rose( expression ) $fell( expression ) $stable( expression ) $past( expression [, number_of_ticks] )

35 The need for $rose system function You must be precise when specifying! assertion property ) start -> ##2 Transfer); start transfer

36 Eliminates multiple matches You must be precise when specifying! assertion property ) $rose(start) -> ##2 Transfer); start transfer $rose(start) is a short cut for the sequence!start ##1 start

37 Introduction to SVA Some assertions require additional modeling code In addition to the assertion constructs rst_n Controller put get rst_n data_in FIFO data_out full empty // Assert that the FIFO controller cannot overflow nor underflow

38 Introduction to SVA // assertion modeling code not part of the design `ifdef ASSERT_ON int cnt = 0; ) if (!rst_n) cnt <= 0; else cnt <= cnt + put get; // assert no overflow assert property (@posedge disable iff (!rst_n)!((cnt + put get) > `DEPTH)); // assert no underflow assert property (@posedge disable iff (!rst_n)!((cnt + put) < get)); `endif

39 SVA Does and Don ts Never assert a sequence! assert property (@posedge ) (req ##1 grnt ##1 done)); This says every clock we see req, followed by gnt, followed by done The correct way to do this is with an implication operator: assert property (@posedge ) (req => grnt ##1 done)); It s ok to cover a sequence It s ok to assert a forbidden sequence using not assert property (@posedge ) not (req ##1 grnt ##1 done));

40 Session Recap In this session we discussed... The structure of the SVA language How to construct sequences How to construct properties

41 Training and Consulting Resources Mentor Graphics Training Scalable Verification Courses - A wide range of instructor led classes - Located in public training centers in major cities or onsite at your workplace - Web-based events with live instructors are also available. Mentor Graphics Consulting Questa Verification Methodology JumpStart Knowledge-Sourcing Model - Infuse knowledge into your organization while addressing your immediate product development challenges

42 Other Resources Assertion-Based Design Harry Foster, Adam Krolnik, David Lacey Springer, 2004 Creating Assertion-Based IP Harry Foster, Adam Krolnik Springer, 2008

43 Assertion-Based Verification Introduction to SVA Harry Foster Chief Scientist Verification