Using SystemVerilog Assertions for Functional Coverage
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1 Using SystemVerilog Assertions for Functional Coverage Mark Litterick (Verification Consultant)
2 2 Outline Demonstrate capability of SVA for implementing a complex functional coverage monitor Coding style and syntax applicable to more typical application of SVA coverage: to define designer s key corner cases Related to SNUG Europe 2005 paper ( Utilizing Vera Functional Coverage in the Verification of a Protocol Engine for the FlexRay TM Automotive Communication System Overview of FlexRay TM protocol engine testbench architecture role of functional coverage overview of protocol engine architecture and specification requirements for functional coverage model SVA implementation, structure and coding Conclusion
3 Protocol Engine Testbench Architecture 3 CLUSTER & NODE CONFIGURATION HOST INTERFACE CHECKERS CLUSTER CONFIG FRONT-END TRANSACTORS & RESPONDERS SCOREBOARD & CHECKER CONFIGURATION LIBRARY DRIVERS & MONITORS SCOREBOARD & CHECKER ASSERTIONS GLOBAL PARAMETERS & SERVICE FUNCTIONS PROTOCOL ENGINE CODE CONSTRAINED RANDOM SCENARIO GENERATOR DRIVERS & MONITORS TRANSACTORS & RESPONDERS STIMULUS RESPONSE SVA DIRECTED TESTCASES FLEXRAY CLUSTER STATE STIMULUS FUNCTIONAL
4 Protocol Engine Architecture 4 CONTROLLER HOST INTERFACE POC DC POC PROTOCOL ENGINE C R H START SDL WL CL IL SYNC STATE 0 WS WD CCR IS ICC ICY MAC FSP I/P A I/P B CCC CJ vmode? false CG CODEC true zcount? = 0 else NA NP CHANNEL INTERFACE BUS GUARDIAN INTERFACE O/P X = VAR Y := STATE 1 STATE 2 POC = Protocol Operation Control SYNC = Clk Sync and Macrotick Gen MAC = Media Access Control FSP = Frame and Symbol Processing CODEC = Coding/Decoding
5 Functional Coverage Model Requirements 5 Variety of coverage points states state transitions multi-state transition sequences conditional state (path) transitions SDL trigger events Check for illegal states and transitions RTL implementation independent Coding style closely reflects SDL for maintenance and debug Capability to query coverage results from testbench environment for closed loop constrained random stimulus or functional checking
6 State Coverage 6 POC WL CL DC C R IL H `define DEFAULT_CONFIG (vstate =?= 7'b000_xxxx) `define INTEGRATION_LISTEN (vstate =?= 7'b111_0101) state_dc : cover property clk) `DEFAULT_CONFIG); state_il : cover property clk) `INTEGRATION_LISTEN); WS WD CCR CCC CG IS ICC CJ NA ICY NP property clk) (`DEFAULT_CONFIG `CONFIG `READY `NORMAL_PASSIVE `HALT ); endproperty : prop_legal_state assert_legal_state : assert property (prop_legal_state) else $error("%m: illegal state");
7 Transition Coverage 7 POC WL CL DC C R IL H sequence clk) `HALT ##1 `DEFAULT_CONFIG; endsequence : seq_h_dc sequence clk) `COLDSTART_LISTEN ##1 `INITIALIZE_SCHEDULE; endsequence : seq_cl_is WS WD CCR IS ICC ICY trans_h_dc : cover property ( seq_h_dc ); trans_cl_is : cover property ( seq_cl_is ); CCC CG CJ NA NP property clk) disable iff (rst) (!$stable(vstate) -> (seq_h_dc.ended seq_cl_is.ended )); endproperty : prop_legal_trans assert_legal_trans : assert property (prop_legal_trans) else $error("%m: illegal transition");
8 Multi-Transition Coverage 8 POC WL WS CL DC C R IS IL H sequence clk) `READY ##1 `COLDSTART_LISTEN [*1:$] ##1 `INITIALIZE_SCHEDULE [*1:$] ##1 `INTEGRATION_COLDSTART_CHECK [*1:$] ##1 `COLDSTART_JOIN [*1:$] ##1 `NORMAL_ACTIVE ; endsequence : seq_poc_csa_csi WD CCR ICC ICY trans_poc_csa_csi : cover property ( seq_poc_csa_csi ); CCC CJ CG NA NP
9 Conditional Transition Coverage 9 else COLDSTART_CON- SISTENCY _CHECK coldstart consistency check F F vcyclecounter? even zstartupnodes? = 0 vremainingcold - StartAttempts? > 0 F F vpoc!startupstate := COLDSTART_CONSISTENCY_CHECK; SyncCalcResult ( zsynccalcresult, zstartupnodes, zrefnode) odd else F F F POC: ColdstartConsistencyCheck else F F zcoldstartaborted := true; else zstartupnodes? > 0 zsynccalcresult? WITHIN_BOUNDS F vpoc!coldstartnoise = zcoldstartnoise ; F F07_13_007 : cover property clk) seq_ccc_il.ended && (zstartupnodes <= 0) && (vcyclecounter[0] === 1) ); F07_13_009 : cover property clk) seq_ccc_il.ended && (zsynccalcresult!== `WITHIN_BOUNDS) && (zstartupnodes > 0) && (vcyclecounter[0] === 1) ); F07_13_011 : cover property clk) seq_ccc_il.ended && (vremainingcoldstartattempts === 0) && (zstartupnodes === 0) && (vcyclecounter[0] === 0) ); enter coldstart gap abort startup enter operation //etc coldstart gap integration listen normal active
10 SDL Trigger Event Coverage 10 coldstart listen POC:ColdstartListen header received on A, header received on B set ( tstartupnoise); F symbol decoded on A, symbol decoded on B set ( tstartupnoise); F CHIRP on A CHIRP on B CE Start on A CE Start on B zchannelidle(a) := true; zchannelidle(a) AND zchannelidle(b) true set ( tstartup); F false zchannelidle(b) := true; F F F F F zchannelidle( A) := false; zchannelidle(b) := false; F07_11_003_A : cover property clk) `COLDSTART_LISTEN && $rose(header_received_on_a)); F07_11_003_B : cover property clk) reset(startup) `COLDSTART_LISTEN && $rose(symbol_decoded_on_b)); tstartup tstartupnoise F07_11_005 : cover property clk) `COLDSTART_LISTEN && $rose(chirp_on_a)); integration started on A integration started on B F07_11_011 : cover property clk) `COLDSTART_LISTEN && $rose(tstartup)); F F F F
11 SVA Coverage Monitor Architecture 11 CLUSTER & NODE CONFIGURATION CLUSTER CONFIG FRONT-END CONFIGURATION LIBRARY GLOBAL PARAMETERS & SERVICE FUNCTIONS CONSTRAINED RANDOM SCENARIO GENERATOR DIRECTED TESTCASES STIMULUS HOST INTERFACE TRANSACTORS & RESPONDERS DRIVERS & MONITORS SYNC PROTOCOL ENGINE FSP MAC CONTROLLER HOST INTERFACE POC CODEC CHANNEL INTERFACE DRIVERS & MONITORS TRANSACTORS & RESPONDERS FLEXRAY CLUSTER PROTOCOL ENGINE BUS GUARDIAN INTERFACE bind CHECKERS testbench.protocol_engine.poc FRPocCovMon_sva SCOREBOARD FRPocCovMon_sva_i &( CHECKER.clk (clk),.rst (rst) SCOREBOARD,.vState (vstate) &, CHECKER.pWakeupChannel (pwakeupchannel),.vremainingcoldstartattempts (),.zsynccalcresult (zsynccalcresult) ASSERTIONS,.header_received_on_A (header_received[0])...); CODE module FRPocCovMon_sva ( input clk, input rst, input [6:0] vstate STIMULUS, input pwakeupchannel, input [4:0] vremainingcoldstartattempts, input RESPONSE [1:0] zsynccalcresult, input header_received_on_a...); // cover STATEproperty statements endmodule : FRPocCovMon_sva FUNCTIONAL
12 SystemVerilog Coverage API 12 SystemVerilog Coverage API real-time access system functions integer num; if ($coverage_control( `SV_COV_CHECK, `SV_COV_ASSERTION, `SV_COV_MODULE, $root.tb.pe.poc.trans_poc_csa_csi) == `SV_COV_OK ) begin num = $coverage_get(`sv_cov_assertion, `SV_COV_MODULE, $root.tb.pe.poc.trans_poc_csa_csi); case(num) `SV_COV_OVERFLOW : $fatal( non-integer coverage value ); `SV_COV_ERROR : $fatal( error extracting coverage value ); default : $display( trans_poc_csa_csi coverage = %0d,num); endcase end else $fatal( coverage cannot be obtained for trans_poc_csa_csi );
13 13 Conclusion Possible to generate a complex functional coverage monitor completely in SVA demonstrates coverage capability of SystemVerilog Assertions language Pros: mixed language simulators enable SVA to be mixed with any HDL or HVL can be used in testbench environments with no HVL coverage implementation and use requires no OO skills Cons: not scalable for all coverage in system, e.g. abstract data in stimulus Provides coding guidelines for typical SVA coverage applications mark.litterick@verilab.com
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