Unifying Design and Verification

Transcription

1 Unifying Design and Verification SystemVerilog Overview

2 Agenda SystemVerilog Introduction Synopsys SystemVerilog Solution SystemVerilog Features and Successful Stories 2006 Synopsys, Inc. (2)

3 Agenda SystemVerilog Introduction Synopsys SystemVerilog Solution SystemVerilog Features and Successful Stories 2006 Synopsys, Inc. (3)

4 Language And Tools Fragmentation Have Led To Verification Inefficiencies C/C++ System Coverage Constraints Assertion/ Property Language Assertions Assertions Simulation Formal Formal Testbench HVL VIP VHDL, Verilog Wasted Time and Productivity 2006 Synopsys, Inc. (4)

5 SystemVerilog: Unifying Design and Verification Coverage Coverage System System Simulation Simulation Formal Formal Assertions Assertions Testbench Testbench VIP VIP Fragmented Verification Single, Unified Language 2006 Synopsys, Inc. (5)

6 SystemVerilog Increases Productivity Netlist RTL SystemVerilog RTL Designer Performance Extends Verilog to Higher Abstraction 2-5x less code No change in synthesis flow HDL Simulation SystemVerilog Co-Sim Overhead Testbench Verification Speed Full native testbench 2-5X faster verification Simulation Coverage Assertions Formal Analysis Testbench Better VerificationV Built-in in assertions Capture intent in RTL code Pinpoint design errors quickly 2006 Synopsys, Inc. (6)

7 SystemVerilog Standardization Approved as IEEE Std SystemVerilog Standardized under IEEE Corporate Program Broad industry support with over 75 products Rapid user momentum 2006 Synopsys, Inc. (7)

8 IEEE Approves SystemVerilog Standard 2006 Synopsys, Inc. (8)

9 Over 30 Supporting Vendors Quotes Synopsys Mentor Graphics Cadence Magma Real Intent Novas Bluespec Denali Ace Verification BluePearl Software ComputerBasedEducation Doulos HDL Design House Interra Systems Jasper LOA Technology NoBug nsys Paradigm Works Perftrends PSI-Electronics & MU-Electronics Sequence Design Silicon Interfaces SiMantis Sunburst Design Sutherland HDL SynaptiCAD Verific Design Automation Verilab VhdlCohen Publishing XtremeEDA Yogitech 2006 Synopsys, Inc. (9)

10 IEEE SystemVerilog LRM Available 2006 Synopsys, Inc. (10)

11 Over 75 Products Announced with SystemVerilog Support* * Synopsys, Inc. (11)

12 Authors and Publishers Recognize Importance of SystemVerilog 2006 Synopsys, Inc. (12)

13 SystemVerilog User Momentum Confirmed by ESNUG Surveys SystemVerilog Use Growing SVA Adoption Increasing Verilog SystemVerilog VHDL SystemC 15% 17% 20% 8% 4% 44% 80% 94% Within One Year Current PSL SVA OVA OVL 0-In 7% 7% 8% 21% 18% 12% 14% 17% 18% % 0% 20% 40% 60% 80% 100% 0% 20% 40% Whose SystemVerilog tools are you using? Mentor 15% Cadence 6% Synopsys 79% With such dominance it is obvious why people use the phrase Synopsys SystemVerilog John Cooley 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 2006 Synopsys, Inc. (13) Source:

14 Agenda SystemVerilog Background Synopsys SystemVerilog Solution SystemVerilog Features and Successful Stories 2006 Synopsys, Inc. (14)

15 Synopsys SystemVerilog Solution Industry s First Complete Design Methodology Over 150 customers using SystemVerilog In production today SystemVerilog for Design Higher productivity Faster time to market Evolutionary improved methodology Same or Better QoR as Verilog 2006 Synopsys, Inc. (15)

16 Agenda SystemVerilog Introduction Synopsys SystemVerilog Solution SystemVerilog Features and Successful Stories 2006 Synopsys, Inc. (16)

17 SystemVerilog for Design Support : Design Compiler, VCS, Leda, and Formality Interface as a signal container and module port replacement Interface ports and modports Interface bundles of ANSI module ports "\" multi-line macro continuation Macro arguments in strings Attributes extended to SystemVerilog User-defined Types (typedef) Structures. Operator Support for scoping Logic (4-value) Data Type Integer Data Types (int, bit) Enumerations Unsized literal ('0, '1, 'x, 'z) Matching end block name Datatype parameter SystemVerilog Assertion parsing Always_comb, always_ff, always latch Return statement in functions Unique/priority case, casex, casez Arrays of structures Packed arrays of packed data Expression Size System Function ($bits) All types as legal module ports All types a legal task/function argument types and legal function return types Implicit.name and.* port connections Unions (packed) Auto-operators: "+= -= &= I= ^=" Auto-operators: <<=>>=<<<=>>>=" Parameterized Interfaces Interface Tasks & Functions Void functions Logic default task/function argument type Input default task/function argument direction Array Querying ($length, $left, $right) Array Querying ($low, $high, $increment, $dimensions) Looping constructs Casting 2006 Synopsys, Inc. (17)

18 Higher Level of Abstraction Verilog module fifo (clk, rstp, din_src, din_dst, din_data,readp,writep, dout_src,dout_dst, dout_data, emptyp, fullp); input clk; input rstp; input [7:0] din_src; input [7:0] din_dst; input [31:0] din_data; input readp; input writep; output [7:0] dout_src; output [7:0] dout_dst; output [31:0] dout_data; output emptyp; output fullp;... SystemVerilog Define Once typedef struct { logic [7:0] src, dst; logic [31:0] data; } packet_t; module fifo ( input input input packet_t input input clk, rstp; din, readp; writep; output packet_t dout; output logic output logic ); emptyp; fullp Use many times packet_t is a port 2006 Synopsys, Inc. (18)

19 SystemVerilog Interfaces Encapsulate communication Define once and reuse Signal declarations Define and check protocol Can be designed & verified separately Block-based design of communication Synthesizable Assertions for built-in protocol checking Supports multiple levels of abstraction Include logic processes if necessary interface ChBus (input bit clk); bit req, gnt, rdy; bit [31:0] addr; pkt_t data; modport master(...); modport slave(...); task read(...); task write(...); assert property(...); endinterface module foo(interface ChBus);... Assertion ChBus clk data addr req gnt rdy write read 2006 Synopsys, Inc. (19)

20 SystemVerilog Interfaces Example interface simple_bus; logic req,gnt; logic [7:0] addr,data; logic [1:0] mode; logic start,rdy; endinterface: simple_bus module memmod(interface a, input bit clk); logic avail; clk) a.gnt <= a.req & avail; endmodule module cpumod(interface b, input bit clk); endmodule Bundle signals in interface Use interface keyword in port list Refer to intf signals module top; bit clk = 0; simple_bus sb_intf; memmod mem(sb_intf, clk); cpumod cpu(.b(sb_intf),.clk(clk)); endmodule Top CPU clk sb_intf interface instance Connect interface Mem 2006 Synopsys, Inc. (20)

21 Consumer Electronics Company SystemVerilog Assertions Success Conventional simulation Debugging with waveform viewer RTL description Simulation with VCS Find bug from image file Simulation With SVA Find the bug with assertion during the simulation Confirm the cause of the bug with waveform viewer Unnecessary read/write operations found & corrected Power consumption reduced 10% 2006 Synopsys, Inc. (21)

22 ARM-Synopsys Verification Methodology Manual (VMM) for SystemVerilog SystemVerilog building block library VMM Standard Library included with VCS Now also available in Japanese language 2006 Synopsys, Inc. (22)

23 Industry s First Verification Library with Support for SystemVerilog and VMM VCS Verification Library 5X higher verification performance with VCS and Pioneer-NTB Supports industry s popular bus standards VMM-compliant Reference Verification Methodology 2006 Synopsys, Inc. (23)

24 SystemVerilog Summary Industry-Standard Hardware Description & Verification Language Broad Industry Support & User Adoption Synopsys Offers Strongest SystemVerilog Design & Verification Solution Start Benefiting from SystemVerilog s Higher Productivity Today! 2006 Synopsys, Inc. (24)

25 AMCC Speeds Verification with VCS SystemVerilog Testbench 2006 Synopsys, Inc. (25)

26 Exar Triples Verification Productivity with VCS SystemVerilog Testbench 2006 Synopsys, Inc. (26)

27 ARM-Synopsys Verification Methodology Manual (VMM) for SystemVerilog Published 2006 Synopsys, Inc. (27)

28 Synopsys Announces Source-Code License for SystemVerilog Verification Library 2006 Synopsys, Inc. (28)

29 Synopsys Introduces Pioneer-NTB for SystemVerilog Testbench Automation 2006 Synopsys, Inc. (29)

30 ARM-Synopsys VMM Endorsed by Leading Japanese Companies 2006 Synopsys, Inc. (30)

31 Synopsys Delivers First Complete SystemVerilog Design & Verification Flow 2006 Synopsys, Inc. (31)

32 Industry s First Verification IP Library for SystemVerilog & VMM 2006 Synopsys, Inc. (32)

33 S3 Adopts Synopsys VCS Verification Solution and the Verification Methodology Manual for SystemVerilog 2006 Synopsys, Inc. (33)