DESIGN PROJECT TOY RPN CALCULATOR

Transcription

1 April 8, 1998 DESIGN PROJECT TOY RPN CALCULATOR ECE/Comp Sci 352 Digital System Fundamentals Semester II Due Tuesday, April 28, 1998; 10% of course grade. This project is to be submitted and will be graded. It is to be performed by teams of two students to permit a more significant project and foster collaboration on difficult parts and in Mentor Graphics usage. The team is not to copy designs or results from others. However, sharing knowledge and tips on how to use Mentor Graphics with other teams is allowed and encouraged. As a part of the project report, a table is to be included that reports in detail what parts of the project were performed by each team member; the table to be completed and submitted is included at the end of this write-up. Ordinarily the same grade will be given to each team member, but if there is a significant imbalance in overall contribution, individual grades will be given. This project write-up is organized as follows. Initially, we will give specifications for the Toy RPN Calculator. The specifications will be followed by a number of design exercises that will lead you through the design and CAD tool usage. You are strongly encourage to study this entire write-up before beginning. SPECIFICATIONS EXTERNAL SPECIFICATIONS RPN stands for Reverse Polish Notation otherwise referred to as Postfix notation. EXERCISE: Surf the Web to find out how what RPN is, why the name, and how an RPN calculator works. A good starting point Enter: Reverse Polish Notation into the search engine at and then select: as a phrase. 1

2 SPECIFICATIONS Power/Reset 0 ENTER 1 DROP + The Toy RPN Calculator is shown above. In addition to the Power/Reset button, the calculator has two digit buttons, 0 and 1, for entering binary digits, and five operation buttons, ENTER, DROP,, +, and. There is a 4-digit binary LCD display for displaying intermediate values and results. Instead of the memories used for storage of temporary results and operands in a typical calculator, the RPN calculator uses a Last-In, First-Out (LIFO) queue also called a down stack. This stack operates like a plate stack in a cafeteria. When you add a plate to the stack, the plates currently in the stack move downward so that the Top Of Stack (TOS) is always the same location. When you remove a plate from the stack, the plates remaining move upward so that the TOS is in the same position. The same principle applies to the down stack in the calculator. All entries into the stack of operands, temporary values and results occur on the TOS. All removal of operands, temporary values and results also occur on the TOS. When an entry is made on the stack, the contents in the stack is ed downward by one location. This entry and the downward movement of the stack content is called a PUSH operation. When an entry is removed from the stack, the contents in the stack is moved upward by one location. This removal and upward movement of the stack content is called a POP operation. The operation buttons have the following functions: ENTER PUSH operation in which up to four binary digits entered least significant digit first using the 0 and 1 buttons become the TOS entry. DROP POP operation in which the value in the TOS is discarded. POP the value in TOS and multiply it times the new value in TOS; replace the new value in TOS with the product. + POP the value in TOS and add it to the new value in TOS; replace the new value in TOS with the sum. POP the value in TOS and subtract it from the new value in TOS; replace the new value in TOS with the difference. 2 DESIGN PROJECT TOY RPN CALCULATOR

3 SPECIFICATIONS Suppose we wish to perform the following calculation given in normal notation: (1 + 11) (100 10) The simplest string of operations to do this in the toy RPN calculator is: 1, ENTER, 11, ENTER, +, 100, ENTER, 10, ENTER,, The end result displayed on the display after the is entered. (Note that alternative strings in RPN in which +,, and are performed on TOS and the keyed in data as well, such as 1, ENTER, 11, +, 100, ENTER, 10,,, are not permitted in the toy RPN calculator!) As a design simplification, no inputs, temporary operands, or results are permitted to be negative. In other words, all numbers are unsigned. Care must be taken not to subtract a larger number from a smaller one. INTERNAL SPECIFICATION The top level of the design of the Toy RPN Calculator appears below. Power/ Reset 0 1 ENTER DROP + inp(3:0) I/0 Logic and Circuitry CORE LOGIC CK Reset entr drop mul add sub CONTROL sel31(1:0) en ent ens done DATAPATH dis(3:0) Display You are to design the CORE LOGIC. The I/O Logic and Circuitry is specified functionally as follows and is not to be designed. This description of the interface to the outside world will permit you to understand the environment for the CORE LOGIC. DESIGN PROJECT TOY RPN CALCULATOR 3

4 SPECIFICATIONS The external buttons and the display connect to the I/O Logic and Circuitry which does the following: 1) Provides a clock signal, CK. 2) Provides a master reset signal, Reset, that is activated when the power is turned on. 3) Debounces and otherwise conditions signals from the buttons. 4) Enters the 0 and 1 values from the 0 and 1 buttons least significant bit first into a register that provides 4-bit input inp(3:0) to the CORE LOGIC. 5) Takes the 4-bit output dis(3:0) from the CORE LOGIC and provides the display drivers for driving the 4-bit display. 6) Converts any operation button to a signal on the corresponding line (entr, drop, mul, add, and sub) that goes to 1 and remains 1 until the positive clock edge after done becomes 1. The CORE LOGIC is divided into two pieces, the DATAPATH and the CONTROL. You will design the DATAPATH first, followed by the CONTROL. DATAPATH SPECIFICATION A block diagram for the 4-bit wide DATAPATH appears next. inp B sub A B A 4-bit Adder - Subtractor 4-bit Multiplier S PROD I0 I1 I2 sel31 4-bit 31 Multiplexer Y Q 4-bit en Register CLR D CK Reset dis din ent ens TOS CLR CK Reset 9 4 Stack LIFO 4 DESIGN PROJECT TOY RPN CALCULATOR

5 SPECIFICATIONS Note that the DATAPATH contains a number of components, notably, a 4-bit Multiplier, a 4-bit Adder-Subtractor, 4-bit 31 Multiplexer, a 4-bit Register, and a 9 4-bit Stack. Each of these components will be described next and illustrations will be given to show how they are used to perform stack operations. The 4-bit Multiplier has been predesigned and is available in Mentor Graphics genlib as part 4bit_multi. The input is BA(7:0) and the output is PROD(0:7). The input BA(3:0) = A(3:0) and input BA(7:4) = B(3:0). Functionally, the multiplier multiplies B by A with the product appearing on PROD. Since the DATAPATH is only 4-bits wide, you will use only PROD(3:0) and ignore the upper half of the product, PROD(4:7). The 4-bit Adder-Subtractor places the sum of B(3:0) and A(3:0) on S(3:0) for sub = 0 and subtracts B(3:0) from A(3:0) placing the result on S(3:0) for sub = 1. The 4-bit Multiplexer places one of three inputs, I0(3:0), I1(3:0) and I2(3:0) on its output Y(3:0) based on the values of sel31(1:0) as shown by the following table. sel31(1:0) Y(3:0) 0 0 I0(3:0) 0 1 I1(3:0) 1 X I2(3:0) The 4-bit Register has a load enable input en, data inputs D(3:0) and data outputs Q(3:0) This register loads the value from D(3:0) for en = 1 and stores its current value for en = 0. The 9 4-bit Stack is the most complex of the components. It has a 4-bit data input DIN(3:0) and a 4-bit data output TOS(3:0). There are 9 registers in the stack with the top register referred to as TOS. The stack has three active operations controlled by the signals ent, ens and. The active operations are REPLACE, POP and PUSH, as describe by the following table. ent ens Operation Action in Response to Positive Edge on CK 0 0 X HOLD Stack contents is unchanged REPLACE The value in TOS is replaced by the value on din(3:0), i.e. TOS is loaded from din(3:0). The content of the rest of the stack is unchanged POP The contents of the stack moves upward by one location with the contents of TOS discarded PUSH The contents of the stack moves downward by one location with din(3:0) loaded into TOS. CONTROL SPECIFICATION The control is a sequential circuit that uses inputs entr, drop, mul, add, and sub to generate outputs sel31(1:0), en, ent, ens,, and done. Note that at most one of entr, drop, mul, add, and sub can equal 1 at any time. In addition, Reset and CK influence the sequential behavior of the circuit. The Mealy model state diagram shown at the top of the next page has only two states. State 0 is the state entered by using Reset. The DESIGN PROJECT TOY RPN CALCULATOR 5

6 SPECIFICATIONS Reset 0 1 ENTER and DROP operations are performed in state 0 1. Performance of, + and use both state 0 and state 1. For these three operations, in state 0, a POP is applied to the stack, the value from TOS is copied into the 4-bit Register, and the new state becomes 1 is entered. In state 1, the new TOS value and the value in the 4-bit Register are combined by the specified operation, a REPLACE places the result in TOS, and the new state becomes 0, completing the operation. The next state and output behavior of the control can be derived from prior description of its operation and the description of the control inputs and outputs. We illustrate a part of this derivation by two examples. Suppose we wish to do an ENTER operation, i.e., PUSH the value on inp(3:0) onto the stack. The state is initially 0 and input entr = 1. To pass inp(3:0) to the stack, sel31(1:0) = 00. To cause a PUSH to occur on the stack, ent = ens = 1 and = 1. en is not used for this operation, so en = X (don t care). Since the operation will be completed on the next positive clock edge, done = 1 to cause entr to return to 0 and the next state will be 0 so the calculator is ready to perform the next operation. As an additional illustration, suppose we wish to do a + operation, i.e., POP the value in TOS, add it to the new TOS value, and REPLACE the new TOS value with the result. We will use the 4-bit Register to save the initial TOS value temporarily. In state 0 with input add = 1, we do a POP to remove the initial TOS value from the stack and simultaneously load the TOS output from the stack into the 4-bit Register. The control signal values needed for this are ent = ens = en = 1 and = 0. Also, since the operation is not complete, done = 0 and the next state is 1. The remaining control signal is a don t cares, sel31(1:0) = X. In state 1, to add the new TOS value and the value in the 4-bit Register and REPLACE the TOS value with the result, we need to do an add in the 4- bit Adder-Subtractor, select the output of the adder with the 4-bit 31 Multiplexer, and do a REPLACE on the stack. The control signal values required are sel31(1:0) = 01, ent = 1, ens = 0 and = 1. Note that, by definition of the inputs, the signal sub which bypasses the control = 0 as required to do an add. Since the operation is complete, done = 1, and the next state becomes Saying that something is performed is state 0 means that it occurs at the positive clock edge that ends the clock cycle during which state 0 is the state. 6 DESIGN PROJECT TOY RPN CALCULATOR

7 DATAPATH DESIGN The information from the above example can be placed in a table describing the control: Inputs Present Next Outputs entr drop mul add sub State State sel31(1:0) en ent ens done 1 X X X X X X X X 1 X 0 1 X X X X 1 X X Since only one of the inputs can be 1 at any time, the other inputs need not be used to define the input combination, so are shown as X s to simplify the logic. By going through the same process for each of the other operations, we can come up with the table for the entire control. Any combination not represented in the table will have the next state and output as don t cares. This table can be used to derive the equations (including don t cares) for the outputs and the D input to the flip-flop for the control by using cafe. DATAPATH DESIGN Use the specifications above to obtain the data path components and the datapath. If a simulation of any component designed indicates an error, rework the design until it functions correctly. 4-bit Register. The 4-bit register has been predesigned for you. Open a new sheet in da called R4 and enter the schematic given at the end of this writeup as Attachment 1. The name for the D flip-flop used is dff and the name for the 2-to-1 multiplexer feeding each D flip-flop is mux21. Generate a symbol for R4. Validate R4 by applying the force file R4.frc to it using Quicksim and checking the Quicksim output to make sure the outputs are correct. All force files are available on the course Web site in the Project section. Submit: Logic schematic and Quicksim output waveforms. 8-bit Bidirectional Shift Register. The stack uses four 8-bit bidirectional shift registers called SRG8. SRG8 has been predesigned for you. Open a new sheet in da called SRG8 and enter the schematic given at the end of this writeup as Attachment 2. The name for the D flip-flop used is dff and the names for the 2-to-1 multiplexers used are mux21. Generate a symbol for SRG8. Validate SRG8 by applying the force file SRG8.frc to it using Quicksim and checking the Quicksim output to make sure the outputs are correct. All force files are available on the course Web site in the Project section. Submit: Logic schematic and Quicksim output waveforms. DESIGN PROJECT TOY RPN CALCULATOR 7

8 DATAPATH DESIGN Full Adder/Subtractor Design Design a full adder/subtractor bit by generating the truth table and then using cafe to obtain the equations for the full adder/subtractor from the truth table. Name the inputs a, b, cin and sub and the outputs cout and s. See course Web site under Project for sample cafe input file that shows the format to do this. Note that in cafe, all variable names must be single letters! From the connection array, open a new sheet called fas in Mentor Graphics da and enter the full adder/subtractor design based on the equations using components from genlib. Generate a symbol for fas. Validate your design by applying all 16 possible input combinations to it using Quicksim and checking the Quicksim output to make sure the outputs are correct. Submit: cafe equation output including the input truth table, the logic schematic, and the Quicksim force file and output waveforms. 4-bit Adder/Subtractor Open a new sheet in da called AS4 and connect together four fas symbols to form the 4- bit Adder/Subtractor. Name the inputs sub, A(3:0) and B(3:0) and the output S(3:0). Generate a symbol for AS4. Validate your design by applying input combinations that verify that both a 1 and 0 carry passes properly between the four fas modules in your design. Submit: Logic schematic, and Quicksim force file and output waveforms. 4-bit 31 Multiplexer Open a new sheet in da called MUX314 which will be the 4-bit 31 Multiplexer. The data inputs to the mux are I0(3:0), I1(3:0) and I2(3:0) and the 2-bit select input is sel31(1:0). Design and enter the multiplexer by interconnecting eight mux21 parts from genlib. Generate a symbol for MUX314. Validate your design by applying each of the following two sets of vectors to the inputs I0, I1, and I2 combined with sel31(1:0) = 00, 01, and 10 for a total of six input combinations and comparing to correct values. Data Input Set 1 Set 2 I I I Submit: Logic schematic, Quicksim force file and output waveforms. 9 4-bit Stack The stack LIFO will consist of a 4-bit register TOSR for the TOS and four 8-bit shift registers SRG8 for the other eight stack locations. A block diagram of the stack appears at the top of the next page. 8 DESIGN PROJECT TOY RPN CALCULATOR

9 DATAPATH DESIGN ent din(3:0) sin(3:0) TOS(3:0) TOSR CK Reset ens sid sou ens sid sou en sid sou en sid sou en SRG8 SRG8 SRG8 SRG8 CK Reset Note that the shift registers are vertical rather than horizontal to provide a hardware stack. When the stack is ed, the output of the TOSR is transferred into the top bits of the shift registers. When the stack is popped, the top bits of the shift registers are transferred into TOSR. The behavior of the TOSR is described by the following table: ent Action 0 X Register content remains unchanged 1 0 The value on sin(3:0) is loaded into TOSR 1 1 The value on din(3:0) is loaded into TOSR DESIGN PROJECT TOY RPN CALCULATOR 9

10 CONTROL DESIGN The behavior of the SRG8 is described by the following table: ens Action 0 X The contents of SRG8 remains unchanged. 1 0 SRG8 shifts upward by one position. 1 1 SRG8 shifts downward by one position filling the vacant position from input sid. TOSR. Open a new sheet in da called TOSR and use R4 and mux21 s from genlib to design the TOSR. Generate a symbol for TOSR. Validate TOSR by applying force file TOSR.frc to it using Quicksim and checking the Quicksim output to make sure the outputs are correct. All force files are available on the course Web site in the Project section. Submit: Logic schematic and Quicksim output waveforms. STACK INTEGRATION. Open a new sheet in da called LIFO and interconnect TOSR and four SRG8 s as shown earlier to implement LIFO. Generate a symbol for LIFO. Validate LIFO by applying force file LIFO.frc to it using Quicksim and checking the Quicksim output to make sure the outputs are correct. All force files are available on the course Web site in the Project section. Submit: Logic schematic and Quicksim output waveforms. Data Path Integration Open a new sheet in da called DATAPATH and interconnect the components developed thus far to implement DATAPATH. Generate a symbol for DATAPATH. Validate DATAPATH by applying force file DATAPATH.frc to it using Quicksim and checking the Quicksim output to make sure the outputs are correct. All force files are available on the course Web site in the Project section. Submit: Logic schematic, and Quicksim force file and output waveforms. CONTROL DESIGN Control State and Output Table Complete the state and output table begun in the control specification part for all of the operations. Include in the table as well all don t care conditions you can think of. For example, entr will never be 1 when in state 1. Control Equation Generation Use cafe to find the equations for the control from the state and output table. Recall that in cafe, all variable names must be single letters! 10 DESIGN PROJECT TOY RPN CALCULATOR

11 CORE LOGIC INTEGRATION Control Implementation Open a new sheet in da called CONTROL and implement the logic represented by the connection array including the D flip-flop with Reset for state storage as the CON- TROL. Validate CONTROL by applying force file CONTROL.frc to it using Quicksim and checking the Quicksim output to make sure the outputs are correct. All force files are available on the course Web site in the Project section. Submit: The cafe equation output including the input truth table, logic schematic, and Quicksim output waveforms. CORE LOGIC INTEGRATION Open a new sheet in da called RPN and interconnect the DATAPATH and the CON- TROL to implement the Toy RPN Calculator. Validate RPN by applying force file RPN.frc to it using Quicksim and checking the Quicksim output to make sure the outputs are correct. All force files are available on the course Web site in the Project section. Submit: The logic schematic and Quicksim force files and output waveforms. DESIGN PROJECT TOY RPN CALCULATOR 11

12 CORE LOGIC INTEGRATION 12 DESIGN PROJECT TOY RPN CALCULATOR

13 Attachment 1 Attachment 1 DESIGN PROJECT TOY RPN CALCULATOR 13

14 Attachment 2 Attachment 2 14 DESIGN PROJECT TOY RPN CALCULATOR

15 TEAM EFFORT REPORT TEAM EFFORT REPORT Submit: This page as the last page of your project report. Each row of the table containing the task contributions must sum to 100%. Team Member Names: 4-bit Register: Entry % % 4-bit Register: Validation % % 8-bit Bidirectional Shift Register: Entry % % 8-bit Bidir. Shift Register: Validation % % Full Adder/Subtractor: Design/Entry % % Full Adder/Subtractor: Validation % % 4-bit Adder/Subtractor: Design/Entry % % 4-bit Adder/Subtractor: Validation % % 4-bit 31 Multiplexer: Design/Entry % % 4-bit 31 Multiplexer: Validation 9 x 4 Stack: TOSR: Design/Entry % % 9 x 4 Stack:TOSR: Validation % % Stack Integration: Design/Entry % % Stack Integration: Validation % % Data Path Integration: Design/Entry % % Data Path Integration: Validation % % Control State and Output Table % % Control Equation Generation % % Control Implementation: Design/Entry % % Control Implementation: Validation % % Core Logic Integration: Design/Entry % % Core Logic Integration: Validation % % Other: % % Other: % % Comments: DESIGN PROJECT TOY RPN CALCULATOR 15