Computer Architecture and System Software Lecture 12: Review. Instructor: Rob Bergen Applied Computer Science University of Winnipeg

Transcription

1 Computer Architecture and System Software Lecture 12: Review Instructor: Rob Bergen Applied Computer Science University of Winnipeg

2 Announcements Assignment 5 due today Assignment 5 grades will be ed ASAP

3 Exam Information Date: April11th Time: 6:00 pm Room: 3D04 Duration: 3 hours

4 Exam Information We covered the following sections from the text Ch1: Sections Ch2: Sections (except 2.1.7) Ch6: Sections Ch8: Sections Ch9: Sections (except 9.4) + Fig 9.22 Exam will be more weighted towards assembly + Chapters 6 and onwards

5 Supplementary Notes 8086/88 Architecture Addressing modes Instruction set Assembly language programming Parallel Programming

6 Review The following slides will review and highlight key concepts from FP notation, assembly programming and chapters 6, 8, and 9 This review is not exhaustive please also review the other lectures, examples, labs and assignments

7 Floating Points

8 Floating Point Representation Encode values as (-1) s M 2 E Sign bit s determines whether number is negative or positive Bit representation Single bit encodes sign exp contains k bits encoding E frac contains n bits encoding M Total number of bits = 1+k+n s exp frac

9 Converting from decimal to FP Notation Step 1: Convert to binary Step 2: Normalize (convert to scientific notation) ( x 2 2 for example) Step 3: Compare with (-1) s x M x 2 E Step 4: Calculate exp and convert to unsigned Step 5: Put it all together Floating point to decimal: Reverse process

10 Floating Point Multiplication Multiply significands (M s) and add exponents (E) (add E not exp) Decimal (3 10^1) (5 10^2) = (1.5 10^4) Binary (1.001x2^2)(1.1x2^3) = (1.1011x2^5) Continue with conversion after this step

11 Floating Point Division Perform unsigned division on significands (M) Multiply both sides by same amount to get rid of decimal Subtract exponent (subtract E not exp) Decimal (5 10^2) / (2 10^1) = (2.5 10^1) Binary (1.10x2^2)/(1.0x2^1) = (1.10/1.00) x2^1 = (110/100) x2^1

12 Floating points - Key Areas Do not confuse E with exp! Treat all binary numbers (exp,frac) as unsigned. The sign bit exists for a reason. Show your work! Study examples in class, worksheets Only multiplication and division will be tested

13 Assembly

14 8086 / 8088 Architecture Two main units Bus interface unit (BIU) Execution unit (EU) 8086 Data bus size: 16 bit Instruction queue: 6 bytes 20 bit address bus

15 General Purpose Registers Used for arithmetic, logical, and other operations Can be configured as: Four 16-bit registers Eight 8-bit registers

16 Index and Pointer Registers BP, SI, DI, SP Can only be used as 16 bit registers SI, DI used for addressing, and string op. BP, SP are used for maintaining the stack

17 Segment Registers 16 bit registers labelled DS, CS, SS, ES Used to indicate the start of different segments in memory

18 Flag Register 16-bit register containing 9 1-bit flags Gives status of the last instruction and the processor

19 Segments Memory can be thought of as an array of bytes A program needs storage space within memory We partition memory into segments DS SS CS ES IP DATA SEGMENT STACK SEGMENT CODE SEGMENT

20 Summary of Addressing Modes Operand needed for an instruction may be located: Immediately in the operand field, e.g. MOV AX, 1234h In a register (register addressing), e.g. MOV DS, AX In memory at a an offset specified by one of the following (disp is a constant): The segment address is in DS (by default, except when BP is used) In memory locations given implicitly by string instructions At input/output ports specified by a register or a constant

21 BYTE PTR Example: Assume register si holds the address of the first character in a string mov byte ptr [si], 7 ;replaces first character of ;string in si with 7 BYTE PTR specifies that we want to move a byte of data into memory

22 BYTE PTR Without size specification, it is ambiguous what we want the assembler to do 7 in byte representation = in 16-bit (word) representation = Usually size specification is not necessary since registers are of fixed size

23 Buffered Keyboard Input Structure of buffered keyboard input in memory: max count Buffer 1 byte 1 byte N bytes where max = max number to characters read count = number of characters returned (not including enter) Buffer = contents of string

24 Buffered Keyboard input With this structure in mind, what do the following registers point to if mybstr is a buffered string? a) Lea dx, mybstr dx points to maximum # of chars to read b) Lea dx, mybstr inc dx dx points to total number of characters (not including enter) c) Lea dx, mybstr add dx, 2 dx points to first char of input string

25 Jumps, Conditionals, Loops Two types of jumps: Conditional, unconditional Conditional jumps + update scheme = loop Jumps always point to a label Conditions are checked through flags register If condition is met, jump instruction is ignored and code proceeds as normal

26 Procedures call myproc mov ax, bx ;call (procedure name) ;instruction returned to after ret myproc proc mov ah, 02h mov dl, S int 21 h ret myproc endp ; procedure defined here ;(procedure name) proc ;code for displaying S ;return to instruction after call ;(procedure name) endp

27 Procedures (Background) Stack Pointer (SP) points to the top of the stack Stack Segment (SS) points to the start of the stack segment in memory Call Return address (IP) is pushed to stack Jump to effective address given by operand Return address is the address of the instruction following the call Return Pop return address from stack Jump to that address

28 Parameter Passing There is little/no support for passing parameters to procedures When it comes to implementation Its up to the programmer to follow conventions Procedures are written to assume input data stored in default registers/stack Interrupts also follow these conventions (int 21h)

29 Assembly Language - Key Areas Practice, practice, practice Study labs, assignments 3, 4 & 5 (Q1) Know the names of all the registers, what they do, how big they are. Without this foundation, you can t get far. If you get stuck, try writing the same program in C (or any language of your choice). Converting to assembly may be easier once you figure out the general structure of your program. Don t forget to comment

30 Memory Hierarchy

31 SRAM vs DRAM Static RAM (SRAM) Each bit is stored in bistable memory Memory will store values unless disturbed 1 bit = 6 transistors Fast and expensive Dynamic RAM (DRAM) Stores each bit as a charge on a capacitor Has to be refreshed on regular basis Uses 1 transistor per bit Can be made very dense (lots of bits per inch) 100X cheaper 10X slower

32 Conventional DRAMs

33 Memory Module

34 Memory Module Example Module stores a total of 64 MB Uses eight 64-Mbit 8M x 8 DRAM chips Numbered 0-7 Each supercell consists of one byte of main memory Each 64-bit quadword at address A in main memory is represented by 8 supercells i.e. the supercells whose corresponding address is (i,j)

35 Memory Module To retrieve a 64-bit quadword at address A Memory controller converts A to a supercell address (i,j) Sends address to memory module Memory module broadcasts i and j to each DRAM DRAM outputs 8-bit contents of its (i,j) supercell Module collects these outputs and forms them into a 64-bit quadword Quadword returned to memory controller

36 Memory Module Main memory is an aggregate of multiple memory modules Each memory module stores part of the address space A module consists of DRAM chips DRAM chips consist of supercells containing a number of bits 4 GB of memory example: 1024 Mb (128 MB) DRAM chip 8 chips on a module (128MB x 8 chips = 1024 MB = 1GB) 1GB Requires 30 address lines Only ¼ of address spaces Need 4 banks of modules (32 DRAM chips) to get 4GB Memory controller determines which module to use based on last 2 lines

37 Components of a Memory System Memory Controller Manages memory chips Executes store/load requests Memory Chips: store actual data Two types of operations: Read transaction Write transaction

38 Read Transaction: mov ax, A Bus interface initiates a read transaction on the bus CPU places address A on the system bus via bus interface I/O bridge interprets request as memory read Forwards it on to memory bus Register file ax ALU Bus interface I/O bridge A Main memory x 0 A

39 Read Transaction: mov ax, A Main memory controller Senses the address signal on memory bus and reads it Fetches the data word from DRAM and writes it to memory bus I/O bridge translates the memory bus signal into a system bus signal and passes it along to the system bus Register file ax ALU Bus interface I/O bridge Main memory x 0 x A

40 Read Transaction: mov ax, A CPU: Senses data on system bus Reads it from the bus Copies it to register ax Register file ax x ALU I/O bridge Main memory 0 Bus interface x A

41 Disk Geometry Track: Partitioned into a collection of sectors Sector Contains an equal number of bits (typically 512 bytes) Separated by gaps where no data is recorded Gaps store formatting bits that identify sectors Cylinder A collection of tracks Located in the same location on each surface # of tracks per cylinder = # of surfaces Numbering Surfaces, tracks (cylinders), and sectors are numbered Location is defined as (surface, cylinder, sector)

42 Disk Capacity Maximum # of bits that can be recorded on the HD depends on Recording density (bits/in): # of bits in 1-inch of surface segment of a track Track density (tracks/in) : # of tracks in a 1-inch segment of the radius extending from the center of the patter Areal density (bits/in 2 ): The product of the recording density and the track density

43 Access Time How long to read or write a sector? Seek time: time to move head to correct cylinder Depends on previous position of head Speed of actuator arm Average seek time: measured by averaging time of several thousand seeks Max seek time can be as high as 20ms Rotational latency: time to wait before sector passes head Depends on rotation speed of disk Location of sector at time of operation Worst case: head just missed sector and must wait for complete rotation Average case: worst case divided by 2 Max. rotational latency in seconds (1/RPM) x 60 seconds

44 Access Time Transfer time (throughput): amount of time to r/w a sector Depends on rotation speed of disk & # of sectors per track Approx = (1/RPM) x (1/avg. # sectors per track) x 60 seconds Estimate the avg. time to access the contents of a disk sector as the sum of the avg. seek time, avg. rotational latency, and avg. transfer time Example: Disk 7200 RPM, 9ms seek, 400 sectors/track Access time = ms

45 Access Time Observations Seek time and rot. lat. dominate access time 2x seek time is good estimate of access time Access time to read 512-byte sized block: SRAM = 256 ns DRAM = 4000 ns Disk = 10 ms Disk access time is roughly 40000X greater than SRAM, and 2500X greater than DRAM

46 Solid State Disks Can provide an alternative to rotation disk

47 SSD Advantages/Disadvantages Advantages No moving parts Use less power More rugged Disadvantages SSDs have potential of wearing out More expensive

48 Direct Memory Access (DMA) Disk drives can sometimes directly access memory, bypassing CPU (See diagrams from Lecture 10) Short version: CPU sends r/w request with memory address to disk Disk controller communicates with memory controller until job is done More efficient for large amounts of data

49 Cache Hits and Misses Three types of cache misses: Compulsory misses: are those misses caused by an empty cache Empty cache is called a cold cache Conflict misses: Are those misses that could have been avoided, had the cache not evicted an entry earlier Capacity misses: Misses that occur solely due to finite size of the caches When a block is loaded into cache, it must have a place Ideal: a flexible policy to place block anywhere in cache

50 Summary of Memory Concepts Exploiting Temporal Locality: Objects will be accessed many times First time object is loaded into cache In the future object is accessed from the cache faster Exploiting Spatial Locality: Blocks contain multiple data objects First object causes block to be loaded into cache Next object accessed after first object will already be in the cache

51 Generic Cache Structure

52 Summary Of Cache Parameters

53 Example (pg. 601) Let (S,E,B,m) = (4, 1, 2, 4)

54 Types of Cache Caches are grouped into different classes based on E (# of cache lines per set) Direct-mapped caches: easiest to understand and implement Set associative caches: hard to implement Fully associative caches: hard to implement

55 Set Associative Caches Key characteristic: 1 < E < C/B Called E-way set associative caches Each set contains multiple lines

56 Fully Associative Caches Key Characteristic: E = C/B (S = 1) Cache is a single set with C / B lines Address is divided into tag and offset No s bits Analogous to a huge hash table Valid Tag Cache block Set 0: Valid Tag Cache block E = C/B lines in the one and only set Valid Tag Cache block

57 Which cache is best? Depends: Easy replacement policy increases speed at cost of hit rate Small caches have faster access time but they may thrash Large caches increase hit rate at expense of access time (more entries to search) Level of storage hierarchy determines which feature is most important

58 Memory Mountain

59 Memory Hierarchy Key Concepts Physical structure of DRAM, Disk What is the memory/disk controller s role? What is the relationship of bus size to address space size? What factors affect cache performance (Either positively or negatively)? Be able to explain the above. Example: A complicated replacement policy requires more sophisticated logic, therefore the caching process is slower, but the hit rate is higher. This type of replacement policy is suitable for a storage level low on the hierarchy (DRAM or disk), where cache misses are extremely expensive.

60 Memory Hierarchy Key Concepts Memory mountain Be able to reproduce sketch of 2D cross-sections (Read throughput vs stride) Read throughput vs working set size) Be able to explain prominent features Be able to identify how spatial and temporal locality play a role in computer performance

61 Processes, OS, Virtual Memory

62 Exceptions CPU is executing instruction I curr A significant change in the processor s state occurs (called an event) Examples: Divide by 0 Virtual memory page fault Arithmetic overflow I/O request completes Hardware timer

63 Exception Table When exception occurs (CPU detects an event) CPU determines ID of exception Uses ID to index into exception table Locates reference to corresponding handler Uses reference to make a procedure call to handler Exception table base register Exception number (x 4) + Address of entry for exception # k n-1 Exception table...

64 Class of Exceptions There are four classes of exceptions: Interrupts: caused by normal hardware events Traps: caused by program service requests Faults: caused by repairable program errors Aborts: caused by unrepairable program errors and HW errors

65 Processes A process consists of Program code and data Logical control flow of the program Private address space Information about a process is stored in a Process Control Block (PCB) Allocated by the OS when a process is created Is only accessible to the OS Used to store parts of the process context

66 Logical Control Flow Each process executes a portion of its flow and then is preempted A & B and A & C run concurrently, but B and C do not Process A Process B Process C Time

67 Exceptions Key Concepts Know the types of exceptions Be able to give one or two examples of each What is an exception handler? Logical control flow and processes How is control transferred from one process to another? Why is this important?

68 Virtual Memory

69 Private Address Space Each process has illusion of exclusive use of system s address space In actuality, a process provides each program with its own private address space Private address spaces have similar layouts: Code, data, heap, stack, kernel space Why do we need this abstraction? To multitask

70 Virtual Memory and Caching At any point in time, virtual memory consists of the following types of pages: Unallocated: Contains no data and does not occupy any disk space Cached: Page contains data Page is assigned to a frame (physical page in memory) Uncached: Page contains data Page is not assigned to a frame (physical page in memory) Page is stored on disk

71 Paging Tables Task: The MMU has to translate addresses for each running process Basic approach: for each virtual address determine Which virtual page corresponds to the address Whether virtual page is allocated and cached Determine location of frame containing the page

72 Page Allocation Pages are allocated under three conditions When a process is created Enough pages are allocated to hold code, data, stack, and small heap When a process needs more heap memory Process uses system call to request pages from OS OS responds by Allocating pages for the heap Returns to the process # of pages that were added When process needs more stack OS automatically detects when a process needs more stack Allocates more pages to the stack

73 Address Translation Page Hit Page Miss

74 TLB Problem: this process requires accessing more memory (to read PTE) Solution: use a special cache called Translation Lookaside Buffer Most programs have good locality i.e. accesses are spatially and temporally localized Many accesses will occur within the same set of virtual pages and hence within the same set of physical frames

75 TLB Idea: Cache PTEs of recently accessed virtual pages in a cache Located in the MMU Called TLB Instead of looking up PTE in page table first check TLB If PTE is in TLB, use it Else look in page table Load TLB with new PTE (may need to evict another one) TLBs are efficient (95% hit rates)

76 Virtual Addressing Example

77 Example Page table for 8 VP 1, 2, 4, and 7 are cached 0 and 5 not allocated 3 and 6 are not cached Note: any physical page can contain any virtual page

78 Memory Protection Page tables with permission bits Process i: VP 0: VP 1: VP 2: SUP No No Yes READ WRITE Address Yes No PP 6 Yes Yes PP 4 Yes Yes PP 2 Physical memory PP 0 PP 2 PP 4 Process j: SUP VP 0: No VP 1: Yes VP 2: No READ WRITE Address Yes No PP 9 Yes Yes PP 6 Yes Yes PP 11 PP 6 PP 9 PP 11

79 Address Translation

80 TLBs Translation Lookaside Buffer is used as a cache for page table entries Indexing into a TLB is done through tag (TLBT) and index (TLBI) bits Very similar to caching in chapter 6

81 Virtual Memory Key Concepts Why is virtual memory useful? Keeps processes separate Allows us to have an ordered, contiguous block of memory space for each process Memory protection Know how the MMU translates from virtual to physical addresses Be able to put it all together (Ch6 + Ch9) From virtual addressing to supercell addressing and all the steps along the way

82 Parallel Computing

83 Recall: Threads Processes with multiple executions A process can have more than one execution Each execution is called a thread Threads execute concurrently as well Differences: Process do not share memory Threads view: it does not have the whole machine to itself

84 Multi-threading

85 CPU: Multi-threading Single-core CPU manages multiple threads at once using flow of control Threads on different cores of the CPU can truly execute in parallel However, an X-core processor does not multiply processing power by X

86 Why? There must be some level of communication between cores Cores have their own private memory, as well as shared memory storage between all cores Therefore: threads on separate cores are not truly independent

87 GPUs Graphics Processing Units Used to process pixel and texture data Relies heavily on parallel execution Becoming more and more popular in scientific and general purpose computing

88 Serial Vs. Parallel A computer program can be separated into two parts Serial part Parallel part Size of each part determines amount of speed up that can be gained

89 Amdahl s Law Maximum achievable speed up: B: Fraction of algorithm that is serial n: Number of threads S n = 1 B + 1 (1 B) n

90 Amdahl s Law Example: 16 threads, ½ serial S = 1.83 (83% speed up) 32 threads, ½ serial S = threads, ½ serial S = 2

91 GPU Grid

92 GPU Grid In actuality, blocks and threads are abstractions. In reality, multi/stream processors manage one or more blocks/threads, respectively Blocks can never be divided into more than one multiprocessor

93 Why Massively Parallel Processing? GPU: Designed for massive throughput of one task Little flexibility required (less branching) Architecture is less complex CPU: Handles wide variety of tasks, so lots of flexibility required Architecture is more complex In other words, GPUs will not replace CPUs.

94 Parallel Computing - Key Concepts Know basic GPU architecture Grids, blocks, threads, and if/how they share memory Know general process of GPU computing How do the CPU and GPU interact with one another? Be able to compare CPUs and GPUs with specific examples Matrix addition You will only be asked conceptual questions You can ignore slides on matrix multiplication and programming examples

95 Lab Lab is tomorrow (make up day for Good Friday) Review caching process in Chapter 6