Virtual Memory. Computer Systems Principles
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1 Virtual Memory Computer Systems Principles
2 Objectives Virtual Memory What is it? How does it work? Virtual Memory Address Translation /7/25 CMPSCI 23 - Computer Systems Principles 2
3 Problem Lots of executing programs Take up lots of space! Memory is comparatively small Not enough room! Solution: Pretend we have lots of memory Use disk to store programs & data Use RAM as a cache! /7/25 CMPSCI 23 - Computer Systems Principles 3
4 Overview Virtual Memory An elegant interaction of: hardware exceptions hardware address translation main memory disk files kernel /7/25 CMPSCI 23 - Computer Systems Principles 4
5 Overview Provides: A process with a large, uniform, and private address space. Three Important Capabilities. Main/real memory is cache. 2. Uniform address space. 3. Protects process address space /7/25 CMPSCI 23 - Computer Systems Principles 5
6 Overview A major reason for its success is that it works silently, behind the scenes, and automatically, without intervention by the programmer /7/25 CMPSCI 23 - Computer Systems Principles 6
7 Overview So why is it important to understand virtual memory? A major reason for its success is that it works silently, behind the scenes, and automatically, without intervention by the programmer /7/25 CMPSCI 23 - Computer Systems Principles 7
8 Overview So why is it important to understand virtual memory? There are several reasons A major reason for its success is that it works silently, behind the scenes, and automatically, without intervention by the programmer /7/25 CMPSCI 23 - Computer Systems Principles 8
9 Basic Idea Main Memory Organized as an array of M contiguous bytesized cells. Each byte has a unique physical address (PA) First byte has address, next, next 2, Natural Access Access main memory using PA This is called physical addressing Sometimes also called real addresses, real addressing, real memory /7/25 CMPSCI 23 - Computer Systems Principles 9
10 Physical Addressing CPU executes load instruction at address 4 /7/25 CMPSCI 23 - Computer Systems Principles
11 Physical Addressing CPU executes load instruction at address 4 Generates a physical address /7/25 CMPSCI 23 - Computer Systems Principles
12 Physical Addressing CPU executes load instruction at address 4 Generates a physical address Passes it to main memory over the memory bus /7/25 CMPSCI 23 - Computer Systems Principles 2
13 Physical Addressing CPU executes load instruction at address 4 Generates a physical address Passes it to main memory over the memory bus Main memory fetches 4 byte word at physical address 4 and returns it to the CPU /7/25 CMPSCI 23 - Computer Systems Principles 3
14 Physical Addressing CPU executes load instruction at address 4 Generates a physical address Passes it to main memory over the memory bus Main memory fetches 4 byte word at physical address 4 and returns it to the CPU The CPU stores it in a register for quick access /7/25 CMPSCI 23 - Computer Systems Principles 4
15 Physical Addressing CPU executes load instruction at address 4 Generates a physical address Passes it to main memory over the memory bus Main memory fetches 4 byte word at physical address 4 and returns it to the CPU The CPU stores it in a register for quick access Early PCs used physical addressing Microcontrollers & Cray super computers Still use physical addressing /7/25 CMPSCI 23 - Computer Systems Principles 5
16 Virtual Addressing With virtual addressing CPU accesses main memory by generating a virtual address (VA) The VA is converted into a corresponding PA before it is sent to main memory /7/25 CMPSCI 23 - Computer Systems Principles 6
17 Virtual Addressing With virtual addressing CPU accesses main memory by generating a virtual address (VA) The VA is converted into a corresponding PA before it is sent to main memory Virtual Address > Physical Address Is known as address translation Requires close cooperation between CPU and OS Dedicated Hardware: Memory Management Unit (MMU) /7/25 CMPSCI 23 - Computer Systems Principles 7
18 VM Organization VM organized as Array of N contiguous byte size cells stored on disk Each byte has a unique address to index array Contents of array are cached in main memory Data on Disk Represents memory of entire program. Parts of program that are being actively used are in physical/real/main memory. /7/25 CMPSCI 23 - Computer Systems Principles 8
19 VM Partitioning Virtual Memory Partitioning Partitioned into fixed sized blocks called virtual pages Each virtual page is P = 2 p bytes in size Physical Memory Partitioning Partitioned into fixed sized blocks called physical pages Each physical page is also P bytes in size Physical pages may reside on disk! /7/25 CMPSCI 23 - Computer Systems Principles 9
20 VM Allocation Allocation VM pages are allocated and cached At any point in time, the set of virtual pages is partitioned into three disjoint subsets Unallocated Pages that have not yet been allocated. No data associated with them, do not occupy space on disk or main memory Cached (also: Resident, Swapped in) Allocated pages that are currently cached in physical memory May or may not (yet) have a copy on disk Uncached (also: Non resident, Swapped out) Allocated pages that are not cached in physical memory /7/25 CMPSCI 23 - Computer Systems Principles 2
21 Page Tables Where is my page? VM needs a way to find a page if it is cached, find it on disk if a miss, cache it, and handle eviction Provided by OS, software, & Memory Management Unit (address translation) /7/25 CMPSCI 23 - Computer Systems Principles 2
22 Page Tables Where is my page? VM needs a way to find a page if it is cached, find it on disk if a miss, cache it, and handle eviction Provided by OS, software, & Memory Management Unit (address translation) Page Table Data structure that maps VA to PA OS managed; OS transfers pages: DISK< >RAM /7/25 CMPSCI 23 - Computer Systems Principles 22
23 Page Tables Structure Array of page table entries (PTE) Each page in VA space has a PTE (conceptually, anyway) PTE consists of: Valid bit n bit address field Each page in VA space has a PTE at a fixed offset /7/25 CMPSCI 23 - Computer Systems Principles 23
24 Page Tables Structure Array of page table entries (PTE) Each page in VA space has a PTE (conceptually anyway) PTE consists of: Valid bit n bit address field Each page in VA space has a PTE at a fixed offset Valid Bit Indicates if VP is cached in RAM /7/25 CMPSCI 23 - Computer Systems Principles 24
25 Page Tables Structure Array of page table entries (PTE) Each page in VA space has a PTE (conceptually anyway) PTE consists of: Valid bit n bit address field Each page in VA space has a PTE at a fixed offset Valid Bit Indicates if VP is cached in RAM Address Field Physical page in RAM where VP is stored Null if VP has not been allocated yet (or simply ignored) /7/25 CMPSCI 23 - Computer Systems Principles 25
26 PTE PTE 7 Physical page number or es valid Memory resident page table Page Tables Physical Memory VP Virtual Memory (disk) VP VP 3 VP 5 VP 6 VP 8 /7/25 CMPSCI 23 - Computer Systems Principles 26
27 PTE PTE 7 Physical page number or es valid Memory resident page table Page Tables Fully Associative Physical Memory VP Virtual Memory (disk) VP VP 3 VP 5 VP 6 VP 8 /7/25 CMPSCI 23 - Computer Systems Principles 27
28 PTE PTE 7 Physical page number or es valid Memory resident page table Page Tables Fully Associative VP can go anywhere! Physical Memory VP Virtual Memory (disk) VP VP 3 VP 5 VP 6 VP 8 /7/25 CMPSCI 23 - Computer Systems Principles 28
29 PTE PTE 7 Physical page number or es valid Memory resident page table Page Tables Imagine CPU reads word in : va Physical Memory VP Virtual Memory (disk) VP VP 3 VP 5 VP 6 VP 8 /7/25 CMPSCI 23 - Computer Systems Principles 29
30 PTE PTE 7 Physical page number or es valid Memory resident page table Page Tables va translated into PTE index (more later) Physical Memory VP Virtual Memory (disk) VP VP 3 VP 5 VP 6 VP 8 /7/25 CMPSCI 23 - Computer Systems Principles 3
31 PTE PTE 7 Physical page number or es valid Memory resident page table Page Tables va translated into PTE index (more later) Physical Memory VP Virtual Memory (disk) VP VP 3 VP 5 VP 6 VP 8 /7/25 CMPSCI 23 - Computer Systems Principles 3
32 PTE PTE 7 Physical page number or es valid Memory resident page table Check the valid bit Page Tables Physical Memory VP Virtual Memory (disk) VP VP 3 VP 5 VP 6 VP 8 /7/25 CMPSCI 23 - Computer Systems Principles 32
33 PTE PTE 7 Physical page number or es valid Memory resident page table Page Tables Valid bit is, so is cached HIT! Physical Memory VP Virtual Memory (disk) VP VP 3 VP 5 VP 6 VP 8 /7/25 CMPSCI 23 - Computer Systems Principles 33
34 Page Tables What happens on a miss? Page Faults These are complicated Requires a precise interaction between hardware exceptions and kernel code The hardware exception is called a: segmentation violation /7/25 CMPSCI 23 - Computer Systems Principles 34
35 iclicker question A segmentation violation exception (as distinguished from a signal) should be: a) Ignorable b) Blockable c) Restartable d) Continue at the next instruction e) Fatal (kill the process) /7/25 CMPSCI 23 - Computer Systems Principles 35
36 Page Faults In this example, VP, 2, 4, & 7 are cached in RAM PTE PTE 7 Physical page number or es valid Memory resident page table Physical Memory VP Virtual Memory (disk) VP VP 3 VP 5 VP 6 VP 8
37 Page Faults If we receive a virtual address in VP, 2, 4, or 7: we have a hit! PTE PTE 7 Physical page number or es valid Memory resident page table Physical Memory VP Virtual Memory (disk) VP VP 3 VP 5 VP 6 VP 8
38 Page Faults What if we receive a virtual address that maps to PTE 3? PTE PTE 7 Physical page number or es valid Memory resident page table Physical Memory VP Virtual Memory (disk) VP VP 3 VP 5 VP 6 VP 8
39 Page Faults What if we receive a virtual address that maps to PTE 3? Virtual Address PTE PTE 7 Physical page number or es valid Memory resident page table Physical Memory VP Virtual Memory (disk) VP VP 3 VP 5 VP 6 VP 8
40 Page Faults What if we receive a virtual address contained in PTE 3? Virtual Address PTE PTE 7 Physical page number or es valid Memory resident page table Valid bit indicates that VP 3 is not cached! Physical Memory VP Virtual Memory (disk) VP VP 3 VP 5 VP 6 VP 8
41 Page Faults What if we receive a virtual address contained in PTE 3? Virtual Address PTE PTE 7 Physical page number or es valid Memory resident page table PAGE FAULT! Physical Memory VP Virtual Memory (disk) VP VP 3 VP 5 VP 6 VP 8
42 Page Faults What if we receive a virtual address contained in PTE 3? OS Kernel Virtual Address PTE PTE 7 Physical page number or es valid Memory resident page table Exception Handler Invokes exception handler in kernel Physical Memory VP Virtual Memory (disk) VP VP 3 VP 5 VP 6 VP 8
43 Page Faults What if we receive a virtual address contained in PTE 3? OS Kernel Virtual Address PTE PTE 7 Physical page number or es valid Memory resident page table Exception Handler Invokes exception handler in kernel Physical Memory VP Virtual Memory (disk) VP VP 3 VP 5 VP 6 VP 8 Victim
44 Page Faults What if we receive a virtual address contained in PTE 3? OS Kernel Virtual Address PTE PTE 7 Physical page number or es valid Memory resident page table Exception Handler Invokes exception handler in kernel Physical Memory VP Virtual Memory (disk) VP VP 3 VP 5 VP 6 VP 8 Copy
45 Page Faults What if we receive a virtual address contained in PTE 3? OS Kernel Virtual Address PTE Victim PTE 7 Physical page number or es valid Memory resident page table Exception Handler Invokes exception handler in kernel Physical Memory VP Virtual Memory (disk) VP VP 3 VP 5 VP 6 VP 8 Copy
46 Page Faults What if we receive a virtual address contained in PTE 3? OS Kernel Virtual Address PTE PTE 7 Physical page number or es valid Memory resident page table Exception Handler Invokes exception handler in kernel Physical Memory VP VP 3 Virtual Memory (disk) VP VP 3 VP 5 VP 6 VP 8 Copy
47 Page Faults What if we receive a virtual address contained in PTE 3? OS Kernel Virtual Address PTE valid PTE 7 Physical page number or es valid Memory resident page table Exception Handler Invokes exception handler in kernel Physical Memory VP VP 3 Virtual Memory (disk) VP VP 3 VP 5 VP 6 VP 8
48 Page Faults What if we receive a virtual address contained in PTE 3? OS Kernel Virtual Address PTE PTE 7 Physical page number or es valid Memory resident page table Exception Handler Continue execution from faulting instruction Physical Memory VP VP 3 Virtual Memory (disk) VP VP 3 VP 5 VP 6 VP 8
49 Page Faults This process is called paging or swapping. OS Kernel PTE PTE 7 Physical page number or es valid Memory resident page table Exception Handler Physical Memory VP VP 3 Virtual Memory (disk) VP VP 3 VP 5 VP 6 VP 8
50 Page Allocation What if we need to allocate a new page: malloc(sizeof(foo)); OS Kernel PTE PTE 7 Physical page number or es valid Memory resident page table Exception Handler Physical Memory VP VP 3 Virtual Memory (disk) VP VP 3 VP 5 VP 6 VP 8
51 Page Allocation Imagine we need to allocate more space, because we are full OS Kernel PTE PTE 7 Physical page number or es valid Memory resident page table Exception Handler Physical Memory VP VP 3 Virtual Memory (disk) VP VP 3 VP 5 VP 6 VP 8
52 Page Allocation Need to allocate a new page, say VP 5 OS Kernel PTE PTE 7 Physical page number or es valid Memory resident page table Exception Handler Physical Memory VP VP 3 Virtual Memory (disk) VP VP 3 VP 5 VP 6 VP 8
53 Page Allocation Need to allocate a new page, say VP 5, and do page fault process OS Kernel PTE PTE 7 Physical page number or es valid Memory resident page table Exception Handler Physical Memory VP VP 3 Virtual Memory (disk) VP VP 3 VP 5 VP 6 VP 8
54 Page Allocation Need to allocate a new page, say VP 5, and do page fault process OS Kernel PTE PTE 7 Physical page number or es valid Memory resident page table Exception Handler Physical Memory VP 5 VP 3 Virtual Memory (disk) VP VP 3 VP 5 VP 6 VP 8
55 Locality A page fault is very expensive! So, why do this at all? Locality to the rescue! Programs tend to work on the same data for long periods of time: small set of active pages This is known as the working set or resident set As long as our programs have good temporal locality, VM systems work very well If the working set exceeds the size of physical memory: thrashing
56 Address Translation We saw that virtual address magically index to a PTE. So, how are virtual addresses translated into physical addresses anyways?
57 Address Translation Virtual Address n- p p- Virtual Page Number (VPN) Virtual Page Offset (VPO) n-bit virtual address has two components
58 Address Translation Virtual Address n- p p- Virtual Page Number (VPN) Virtual Page Offset (VPO) A p-bit virtual page number (VPN) n-bit virtual address has two components
59 Address Translation Virtual Address n- p p- Virtual Page Number (VPN) Virtual Page Offset (VPO) A (n-p)-bit virtual page offset (VPO) n-bit virtual address has two components
60 Address Translation Page Table Base Register (PTBR) Virtual Address n- p p- Virtual Page Number (VPN) Virtual Page Offset (VPO) A control register in the CPU points to the current page table
61 Address Translation Page Table Base Register (PTBR) Virtual Address n- p p- Virtual Page Number (VPN) Virtual Page Offset (VPO) Valid Physical Page Number (PPN) Page Table A control register in the CPU points to the current page table
62 Address Translation Page Table Base Register (PTBR) Virtual Address n- p p- Virtual Page Number (VPN) Virtual Page Offset (VPO) Valid Physical Page Number (PPN) The VPN acts as an index into the page table Page Table The MMU uses the VPN to select the PTE
63 Address Translation Page Table Base Register (PTBR) Virtual Address n- p p- Virtual Page Number (VPN) Virtual Page Offset (VPO) Valid Physical Page Number (PPN) The VPN acts as an index into the page table Page Table If valid = then page not in memory: page fault The MMU uses the VPN to select the PTE
64 Address Translation Page Table Base Register (PTBR) Virtual Address n- p p- Virtual Page Number (VPN) Virtual Page Offset (VPO) Valid Physical Page Number (PPN) The VPN acts as an index into the page table Page Table m- p p- If valid = then page not in memory: page fault Physical Page Number (PPN) Physical Page Offset (PPO) Physical Address The physical address is created from concatenating PPN with VPO
65 Page Hit CPU chip Processor MMU Cache/Memory
66 Page Hit CPU chip Processor MMU Cache/Memory. Processor generates VA and sends to MMU
67 Page Hit CPU chip Processor MMU Cache/Memory. Processor generates VA and sends to MMU 2. The MMU generates the PTE address and requests it from the cache/main memory
68 Page Hit CPU chip Processor MMU Cache/Memory. Processor generates VA and sends to MMU 2. The MMU generates the PTE address and requests it from the cache/main memory 3. The cache/main memory returns the PTE to the MMU
69 Page Hit CPU chip Processor MMU Cache/Memory. Processor generates VA and sends to MMU 2. The MMU generates the PTE address and requests it from the cache/main memory 3. The cache/main memory returns the PTE to the MMU 4. The MMU constructs the PA and sends it to cache/main memory
70 Page Hit CPU chip Processor MMU Cache/Memory. Processor generates VA and sends to MMU 2. The MMU generates the PTE address and requests it from the cache/main memory 3. The cache/main memory returns the PTE to the MMU 4. The MMU constructs the PA and sends it to cache/main memory 5. The cache/main memory returns the requested data to the processor
71 Page Miss CPU chip Processor MMU Cache/Memory
72 Page Miss CPU chip Processor MMU Cache/Memory. Processor generates VA and sends to MMU
73 Page Miss CPU chip Processor MMU Cache/Memory. Processor generates VA and sends to MMU 2. The MMU generates the PTE address and requests it from the cache/main memory
74 Page Miss CPU chip Processor MMU Cache/Memory. Processor generates VA and sends to MMU 2. The MMU generates the PTE address and requests it from the cache/main memory 3. The cache/main memory returns the PTE to the MMU
75 Page Miss CPU chip Processor MMU Cache/Memory Page Fault Exception Handler. Processor generates VA and sends to MMU 2. The MMU generates the PTE address and requests it from the cache/main memory 3. The cache/main memory returns the PTE to the MMU 4. Valid bit is, triggers exception, CPU transfers control to fault handler
76 Page Miss CPU chip Processor MMU Cache/Memory Page Fault Exception Handler Victim. Processor generates VA and sends to MMU Disk 2. The MMU generates the PTE address and requests it from the cache/main memory 3. The cache/main memory returns the PTE to the MMU 4. Valid bit is, triggers exception, CPU transfers control to fault handler 5. Fault handler identifies victim page and sends to disk (if modified)
77 Page Miss CPU chip Processor MMU Cache/Memory Page Fault Exception Handler. Processor generates VA and sends to MMU Disk 2. The MMU generates the PTE address and requests it from the cache/main memory 3. The cache/main memory returns the PTE to the MMU 4. Valid bit is, triggers exception, CPU transfers control to fault handler 5. Fault handler identifies victim page and sends to disk (if modified) 6. Fault handler pages in new page and updates PTE in memory Victim New Page
78 Page Miss CPU chip Processor MMU Cache/Memory Resend offending VA Page Fault Exception Handler Disk. Processor generates VA and sends to MMU 2. The MMU generates the PTE address and requests it from the cache/main memory 3. The cache/main memory returns the PTE to the MMU 4. Valid bit is, triggers exception, CPU transfers control to fault handler 5. Fault handler identifies victim page and sends to disk (if modified) 6. Fault handler pages in new page and updates PTE in memory 7. Fault handler returns to process and restarts offending instruction Victim New Page
79 Previous slides were a (small) lie Most caches use the virtual address Cache access can happen during translation Gives address in case of a cache miss PTEs also include access protection bits Indicate whether read, write, execute allowed on bytes of that page PTEs also include dirty bit To know if a page needs write back to disk Caches need scrubbing when swapping /7/25 CMPSCI 23 - Computer Systems Principles 79
80 but these are just refinements Basic idea is to use main memory as a cache for pages, whose natural home is disk Also called the swap file Address translation can be sped up Using a cache of PTEs! Usually fully associative Called a translation lookaside buffer (TLB) Separate ones for instructions and data, similar to split L instruction and data caches: ITLB, DTLB /7/25 CMPSCI 23 - Computer Systems Principles 8
81 But what about SIGSEGV? A process needs to ask for most pages to be allocated Stack will grow automatically, within bounds Otherwise, mmap (memory map) system call Access to an unasked for page SIGSEGV An exception (fault) causes and OS response Only sometimes is that response a signal Improper access to a protected page? Also SIGSEGV, reflected as signal to process /7/25 CMPSCI 23 - Computer Systems Principles 8
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