Basic characteristics & features of 8086 Microprocessor Dr. M. Hebaishy

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1 Basic characteristics & features of 8086 Microprocessor Dr. M. Hebaishy Digital Logic Design Ch1-1

2 8086 Microprocessor Features: The 8086 microprocessor is a 16 bit microprocessor. The term 16 bit means that its arithmetic logic unit, internal registers and most of its instructions are designed to work with 16 bit binary words. The 8086 microprocessor has a 16 bit data bus. It can read data from or write data to memory or ports either 16 bits or 8 bits at a time. The 8086 microprocessor has a 20 bit address bus, so it can directly access 220 or 1,048,576 (1M) locations. The 8086 microprocessor can generate 16 bit I/O address; hence it can access 216 or ports. It is possible to perform bit, byte, word, and block operations in the 8086 microprocessor. It performs the arithmetic and logical operations on bit, byte, word and decimal numbers including multiplication and division. The 8086 microprocessor is designed to operate in two modes, the minimum mode and the maximum mode. When only one CPU is used in the system, the 8086 microprocessor operates in the minimum mode. In multiprocessor system, 8086 microprocessor operates in the maximum mode. Digital Logic Design Ch1-2

3 The 8086 microprocessor supports multiprogramming ability. The code for two or more processes is in the memory at the same time and is executed in time multiplexed fashion. Software architecture of the 8086 microprocessor The 8086 microprocessor is divided into two functional units, the Bus Interface Unit (BIU) and the Execution Unit (EU). These two units can work simultaneously to increase system efficiency. The efficiency is a measure of number of instructions executed per unit time. Bus Interface Unit (BIU) The BIU is the 8086 microprocessor interface to the outside world. It provides a full 16 bit bidirectional data bus and 20 bit address bus. The BIU is responsible for performing all external bus operations. Digital Logic Design Ch1-3

4 Functions of BIU Sends address to the Memory or I/O unit. Fetches instructions from Memory. Reads data from ports or Memory. Writes data on ports or Memory. Supports instruction queuing. Provides address relocation facility. Execution Unit (EU) The EU contains ALU, CU and number of registers. This feature enables the EU to execute instructions and perform arithmetic and logical operations. Digital Logic Design Ch1-4

5 Components of EU Control Circuit. Instruction Decoder. Arithmetic Logic Unit (ALU). Flag Registers. General purpose registers. Pointers and Index Registers. Digital Logic Design Ch1-5

6 Software architecture of the 8086 microprocessor Digital Logic Design Ch1-6

7 Addressing Data in Memory Depending on the model, the processor can access one or more bytes of memory at a time. Consider the Hexa value (0529H) which requires two bytes or one word of memory. It consist of high order (most significant) byte 05 and a low order (least significant) byte 29. The processor store the data in memory in reverse byte sequence i.e. the low order byte in the low memory address and the high order byte in the high memory address. For example, the processor transfer the value 0529H from a register into memory addresses 04A26 H and 04A27H like this: Digital Logic Design Ch1-7

8 When programming in assembly language, you have to distinguish between the address of a memory location and its contents. In the above example the content of address 04A26H is 29, and the content of address 04A27H is 05. There are two types of addressing schemes: 1. An Absolute Address, such as 04A26H, is a 20 bit value that directly references a specific location. 2. A Segment Offset Address, combines the starting address of a segment with an offset value. Segments and Addressing Segments are special area defined in a program for containing the code, the data, and the stack. Segment Offset within a program, all memory locations within a segment are relative to the segment starting address. The distance in bytes from the segment address to another location within the segment is expressed as an offset (or displacement). Digital Logic Design Ch1-8

9 To reference any memory location in a segment, the processor combine the segment address in a segment register with the offset value of that location, that is, its distance in byte from the start of the segment. Active segments of memory Digital Logic Design Ch1-9

10 Only four 64 KB segments are active at a time, these are Code Segment (CS), Stack Segment (SS), Data Segment (DS) and Extra Segment (ES). Specifying Addresses To represent a segment address and its relative offset we use the notation: Segment: offset A segment base and an offset describe the logical address; both of them are 16 bit. However, the physical address that is used to access memory is 20 bits in length. Physical Address = Segment Register (shifted by 1 digit left) + Offset Register Segment Registers are CS, DS, SS and ES. Offset Registers are BP, SP, BX, SI, DI and IP. Digital Logic Design Ch1-10

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12 The actual address it refers to is obtained in the following way: 1- Add zero to the right hand side of the segment address. 2- Add to this the offset. Hence the actual address referred to by 020A:1BCD is 03C6D. Digital Logic Design Ch1-12

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17 Pin Diagram of 8086 and Pin description of 8086 Digital Logic Design Ch1-17

18 The Microprocessor 8086 is a 16-bit CPU available in different clock rates and packaged in a 40 pin CERDIP or plastic package. The 8086 operates in single processor or multiprocessor configuration to achieve high performance. The pins serve a particular function in minimum mode (single processor mode) and other function in maximum mode configuration (multiprocessor mode). The 8086 signals can be categorized in three groups. The first are the signal having common functions in minimum as well as maximum mode. The second are the signals which have special functions for minimum mode The third are the signals having special functions for maximum mode. The following signal descriptions are common for both modes. AD15-AD0: These are the time multiplexed memory I/O address and data lines. Address remains on the lines during T1 state, while the data is available on the data bus during T2, T3, Tw and T4. These lines are active high and float to a tristate during interrupt acknowledge and local bus hold acknowledge cycles. A19/S6, A18/S5, A17/S4, and A16/S3: These are the time multiplexed address and status lines. Digital Logic Design Ch1-18

19 80X86 ADDRESSING MODES Direct addressing mode: address of the data in memory comes immediately after the instruction operand is a constant The address is the offset address. The offset address is put in a rectangular bracket Ex: MOV DL,[2400] ; move contents of DS:2400H into DL Ex: Find the physical address of the memory location and its content after the execution of the following operation. Assume DS=1512H MOV AL,99H MOV [3518],AL Physical address of DS:3518 => =18638H The memory location 18638H will contain the value 99H Digital Logic Design Ch1-19

20 QUIZ Q1 Calculate the value of the following physical addresses. a) 1000:1234 b) 0100:ABCD c) A200:12CF d) B2C0:FA12 Q2. Find the Physical Address (PA) if the Code Segment (CS) = 1B21h and the instruction Pointer (IP) = EFF0h. Q3. Find the Data Segment (DS) if the Physical Address (PA) = 1CA5Dh and the Destination Index (DI) = 167Dh. Q4. Find the Instruction Pointer (IP) if the Physical Address (PA) =25000h and the Code Segment (CS) =2300. Digital Logic Design Ch1-20

21 Which is not part of the execution unit (EU)? A. Arithmetic logic unit (ALU) B. Clock C. General registers D. Flags Ans.: B Which of the following is not an arithmetic instruction? A. INC (increment) B. CMP (compare) C. DEC (decrement) D. ROL (rotate left) Ans.: D. Define instruction cycle? Instruction cycle is defined, as the time required completing the execution of the instruction. Digital Logic Design Ch1-21

22 Draw and discuss the architecture of Mention the jobs performed by BIU and EU. units Bus Interface Unit (BIU) and Execution Unit (EU) architecture employs parallel processing i.e., both the units (BIU and EU) work at the same time. This is Unlike 8085 in which Sequential fetch and execute operations take place. Thus in case of 8086, efficient use of system bus takes place and higher performance (because of reduced instruction time) is ensured. BIU has segment registers, instruction pointer, address generation and bus control logic block, instruction queue EU has general purpose registers, ALU, control unit, instruction register, flag (or status) register. The main jobs performed by BIU are:» BIU is the 8086 s interface to the outside world, i.e., all External bus operationsare done by BIU.» It does the job of instruction fetching, reading/writing of data/operands for memory and also the inputting/outputting of data for peripheral devices.» It does the job of filling the instruction queue.» Does the job of address generation. The main jobs performed by the execution unit are:» Decoding/execution of instructions.» It accepts instructions from the output end of instruction queue (residing in BIU) and data from the general purpose registers or memory.» It generates operand addresses when necessary, hands them over to BIU requesting it (BIU) to perform read or write cycle to memory or I/O devices. Digital Logic Design Ch1-22

23 » EU tests the status of flags in the control register and updates them when executing instructions.» EU waits for instructions from the instruction queue, when it is empty.» EU has no connection to the system buses. Digital Logic Design Ch1-23

24 CPU model for the 8086 microprocessor. A separate execution unit (EU) and bus interface unit (BIU) are provided. Digital Logic Design Ch1-24

25 Mention the total number of registers of 8086 and show the manner in which they are grouped. There are in all fourteen numbers of 16-bit registers. The different groups are made as here under: Data group, pointers and index group, status and control flag group and segment group. z The data group consists of AX (accumulator), BX (base), CX (count) and DX (data). Pointer and Index group consist of SP (Stack pointer), BP (Base pointer), SI (Source Index), DI (Destination index) and IP (Instruction pointer). Segment group consists of ES (Extra Segment), CS (Code Segment), DS (Data Segment) and SS (Stack Segment). Control flag group consists of a single 16-bit flag register. Digital Logic Design Ch1-25

26 Describe, in detail, the general purpose of data registers. four data group registers and their functions Digital Logic Design Ch1-26

27 Describe the status register of It is a 16-bit register, also called flag register or Program Status Word (PSW). Seven bits remain unused while the rest nine are used to indicate the conditions of flags. Describe in brief the four segment registers. The four segment registers are CS, DS, ES and SS standing for code segment register, data segment register, extra segment register and stack segment register respectively. When a particular memory is being read or written into, the corresponding memory address is determined by the content of one of these four segment registers in conjunction with their offset addresses. The contents of these registers can be changed so that the program may jump from one active code segment to another one. The use of these segment registers will be more apparent in memory segmentation schemes. Digital Logic Design Ch1-27

28 Show, in tabular form, the default and alternate segment registers for different types of memory references. Table shows the default and alternate register segments which can be used for different types of memory references. Digital Logic Design Ch1-28

Program controlled semiconductor device (IC) which fetches (from memory), decodes and executes instructions.

8086 Microprocessor Microprocessor Program controlled semiconductor device (IC) which fetches (from memory), decodes and executes instructions. It is used as CPU (Central Processing Unit) in computers.