Lecture 2: Pipelining Basics. Today: chapter 1 wrap-up, basic pipelining implementation (Sections A.1 - A.4)

Transcription

1 Lecture 2: Pipelining Basics Today: chapter 1 wrap-up, basic pipelining implementation (Sections A.1 - A.4) 1

2 Defining Fault, Error, and Failure A fault produces a latent error; it becomes effective when activated; it leads to failure when the observed actual behavior deviates from the ideal specified behavior Example I : a programming mistake is a fault; the buggy code is the latent error; when the code runs, it is effective; if the buggy code influences program output/behavior, a failure occurs Example II : an alpha particle strikes DRAM (fault); if it changes the memory bit, it produces a latent error; when the value is read, the error becomes effective; if program output deviates, failure occurs 2

3 Defining Reliability and Availability A system toggles between Service accomplishment: service matches specifications Service interruption: services deviates from specs The toggle is caused by failures and restorations Reliability measures continuous service accomplishment and is usually expressed as mean time to failure (MTTF) Availability measures fraction of time that service matches specifications, expressed as MTTF / (MTTF + MTTR) 3

4 Amdahl s Law Architecture design is very bottleneck-driven make the common case fast, do not waste resources on a component that has little impact on overall performance/power Amdahl s Law: performance improvements through an enhancement is limited by the fraction of time the enhancement comes into play Example: a web server spends 40% of time in the CPU and 60% of time doing I/O a new processor that is ten times faster results in a 36% reduction in execution time (speedup of 1.56) Amdahl s Law states that maximum execution time reduction is 40% (max speedup of 1.66) 4

5 Principle of Locality Most programs are predictable in terms of instructions executed and data accessed The Rule: a program spends 90% of its execution time in only 10% of the code Temporal locality: a program will shortly re-visit X Spatial locality: a program will shortly visit X+1 5

6 Exploit Parallelism Most operations do not depend on each other hence, execute them in parallel At the circuit level, simultaneously access multiple ways of a set-associative cache At the organization level, execute multiple instructions at the same time At the system level, execute a different program while one is waiting on I/O 6

7 The Assembly Line Unpipelined Start and finish a job before moving to the next Jobs Time A B C A B C Break the job into smaller stages A B C Pipelined A B C 7

8 Quantitative Effects As a result of pipelining: Time in ns per instruction goes up Number of cycles per instruction goes up (note the increase in clock speed) Total execution time goes down, resulting in lower time per instruction Average cycles per instruction increases slightly Under ideal conditions, speedup = ratio of elapsed times between successive instruction completions = number of pipeline stages = increase in clock speed 8

9 A 5-Stage Pipeline Source: H&P textbook 9

10 A 5-Stage Pipeline Use the PC to access the I-cache and increment PC by 4 10

11 A 5-Stage Pipeline Read registers, compare registers, compute branch target; for now, assume branches take 2 cyc (there is enough work that branches can easily take more) 11

12 A 5-Stage Pipeline ALU computation, effective address computation for load/store 12

13 A 5-Stage Pipeline Memory access to/from data cache, stores finish in 4 cycles 13

14 A 5-Stage Pipeline Write result of ALU computation or load into register file 14

15 Conflicts/Problems I-cache and D-cache are accessed in the same cycle it helps to implement them separately Registers are read and written in the same cycle easy to deal with if register read/write time equals cycle time/2 (else, use bypassing) Branch target changes only at the end of the second stage -- what do you do in the meantime? Data between stages get latched into registers (overhead that increases latency per instruction) 15

16 Hazards Structural hazards: different instructions in different stages (or the same stage) conflicting for the same resource Data hazards: an instruction cannot continue because it needs a value that has not yet been generated by an earlier instruction Control hazard: fetch cannot continue because it does not know the outcome of an earlier branch special case of a data hazard separate category because they are treated in different ways 16

17 Structural Hazards Example: a unified instruction and data cache stage 4 (MEM) and stage 1 (IF) can never coincide The later instruction and all its successors are delayed until a cycle is found when the resource is free these are pipeline bubbles Structural hazards are easy to eliminate increase the number of resources (for example, implement a separate instruction and data cache) 17

18 Data Hazards 18 Source: H&P textbook

19 Bypassing Some data hazard stalls can be eliminated: bypassing 19

20 Example add R1, R2, R3 lw R4, 8(R1) 20

21 Example lw R1, 8(R2) lw R4, 8(R1) 21

22 Example lw R1, 8(R2) sw R1, 8(R3) 22

23 Summary For the 5-stage pipeline, bypassing can eliminate delays between the following example pairs of instructions: add/sub R1, R2, R3 add/sub/lw/sw R4, R1, R5 lw sw R1, 8(R2) R1, 4(R3) The following pairs of instructions will have intermediate stalls: lw R1, 8(R2) add/sub/lw R3, R1, R4 or sw R3, 8(R1) fmul fadd F1, F2, F3 F5, F1, F4 23

24 Lecture 2: Advanced Pipelines Data hazards, control hazards, multi-cycle in-order pipelines (Appendix A.4-A.8) 24

25 A 5-Stage Pipeline 25 Source: H&P textbook

26 Hazards Structural hazards: different instructions in different stages (or the same stage) conflicting for the same resource Data hazards: an instruction cannot continue because it needs a value that has not yet been generated by an earlier instruction Control hazard: fetch cannot continue because it does not know the outcome of an earlier branch special case of a data hazard separate category because they are treated in different ways 26

27 Data Hazards SUB R2 R1, R3 Uses R2 Uses R2 Uses R2 Uses R2 27

28 Bypassing Some data hazard stalls can be eliminated: bypassing 28

29 Bypassing 29

30 Pipeline Implementation Signals for the muxes have to be generated some of this can happen during ID Need look-up tables to identify situations that merit bypassing/stalling the number of inputs to the muxes goes up 30

31 Detecting Control Signals Situation Example code Action No dependence LD R1, 45(R2) DADD R5, R6, R7 DSUB R8, R6, R7 OR R9, R6, R7 No hazards Dependence requiring stall Dependence overcome by forwarding LD R1, 45(R2) DADD R5, R1, R7 DSUB R8, R6, R7 OR R9, R6, R7 LD R1, 45(R2) DADD R5, R6, R7 DSUB R8, R1, R7 OR R9, R6, R7 Detect use of R1 during ID of DADD and stall Detect use of R1 during ID of DSUB and set mux control signal that accepts result from bypass path Dependence with accesses in order LD R1, 45(R2) DADD R5, R6, R7 DSUB R8, R6, R7 OR R9, R1, R7 No action required 31

32 Example add R1, R2, R3 lw R4, 8(R1) 32

33 Example lw R1, 8(R2) lw R4, 8(R1) 33

34 Example lw R1, 8(R2) sw R1, 8(R3) 34

35 Summary For the 5-stage pipeline, bypassing can eliminate delays between the following example pairs of instructions: add/sub R1, R2, R3 add/sub/lw/sw R4, R1, R5 lw sw R1, 8(R2) R1, 4(R3) The following pairs of instructions will have intermediate stalls: lw R1, 8(R2) add/sub/lw R3, R1, R4 or sw R3, 8(R1) fmul fadd F1, F2, F3 F5, F1, F4 35

36 Control Hazards Simple techniques to handle control hazard stalls: for every branch, introduce a stall cycle (note: every 6 th instruction is a branch!) assume the branch is not taken and start fetching the next instruction if the branch is taken, need hardware to cancel the effect of the wrong-path instruction fetch the next instruction (branch delay slot) and execute it anyway if the instruction turns out to be on the correct path, useful work was done if the instruction turns out to be on the wrong path, hopefully program state is not lost 36

37 Branch Delay Slots 37

38 Slowdowns from Stalls Perfect pipelining with no hazards an instruction completes every cycle (total cycles ~ num instructions) speedup = increase in clock speed = num pipeline stages With hazards and stalls, some cycles (= stall time) go by during which no instruction completes, and then the stalled instruction completes Total cycles = number of instructions + stall cycles Slowdown because of stalls = 1/ (1 + stall cycles per instr) 38

39 Pipelining Limits Gap between indep instrs: T + Tovh Gap between dep instrs: T + Tovh A B C A B C Gap between indep instrs: T/3 + Tovh Gap between dep instrs: T + 3Tovh A B C D E F A B C D E F Gap between indep instrs: T/6 + Tovh Gap between dep instrs: T + 6Tovh Assume that there is a dependence where the final result of the first instruction is required before starting the second instruction 39

40 Multicycle Instructions Functional unit Latency Initiation interval Integer ALU 1 1 Data memory 2 1 FP add 4 1 FP multiply 7 1 FP divide

41 Effects of Multicycle Instructions Structural hazards if the unit is not fully pipelined (divider) Frequent RAW hazard stalls Potentially multiple writes to the register file in a cycle WAW hazards because of out-of-order instr completion Imprecise exceptions because of o-o-o instr completion Note: Can also increase the width of the processor: handle multiple instructions at the same time: for example, fetch two instructions, read registers for both, execute both, etc. 41

42 Precise Exceptions On an exception: must save PC of instruction where program must resume all instructions after that PC that might be in the pipeline must be converted to NOPs (other instructions continue to execute and may raise exceptions of their own) temporary program state not in memory (in other words, registers) has to be stored in memory potential problems if a later instruction has already modified memory or registers A processor that fulfils all the above conditions is said to provide precise exceptions (useful for debugging and of course, correctness) 42

43 Dealing with these Effects Multiple writes to the register file: increase the number of ports, stall one of the writers during ID, stall one of the writers during WB (the stall will propagate) WAW hazards: detect the hazard during ID and stall the later instruction Imprecise exceptions: buffer the results if they complete early or save more pipeline state so that you can return to exactly the same state that you left at 43