System Development Tools for Excalibur Devices

Transcription

1 System Development Tools or Excalibur Devices January 2003, ver. 1.0 Application Note 299 Introduction The Excalibur embedded processor devices achieve a new level o system integration rom the inclusion o an embedded processor system within a ield programmable gate array (FPGA). Such an integration increases the demands placed on the system development tools and the resulting programming iles. To utilize the Excalibur embedded processor device ully, both programmable logic development tools and embedded sotware development tools are used. This document describes the low o the system development tools or generating programmable logic coniguration iles and the embedded processor sotware iles to create a single system-level device programming ile. Preliminary Inormation An Excalibur-based system contains three sections: The digital logic design o the FPGA The embedded sotware application running on the processor The parameterization and instantiation o the embedded processor stripe On power-up, Excalibur devices can either be viewed as an embedded processor within an FPGA, or as an FPGA within an embedded processor. As an embedded processor, the development tool low acilitates the creation and downloading o a single system ile containing both the coniguration o the FPGA logic and the embedded sotware, in an appropriate ormat or storing in an external lash memory device. In this mode, the embedded stripe parameters are integrated into the boot section o the embedded sotware application. As an FPGA, the development tool low acilitates the creation o a single system ile containing all three sections. The ile ormats provided are standard FPGA conigurations ile to be stored in an external coniguration device, such as an EPC2 serial EPROM. Altera Corporation 1 AN

2 FPGA Logic Design Embedded Sotware Design Parameterization and Instantiation o the Embedded Processor Stripe The development o digital logic or the programmable logic section o the devices ollows the same low as any other design or an Altera APEX device. The FPGA designs are provided in either VHDL or Verilog hardware descriptions languages (HDL). The creation o this HDL can be through tools such as Altera s SOPC Builder, provided by third parties in the orm o IP cores, or created by the user in a text editor. The HDL must be synthesized into a orm that can be placed and routed by the Quartus II development tools. Typically, the Altera Quartus II sotware development tools are used in conjunction hardware simulation tools rom Altera or a third party partner. A variety o simulation models are provided, which can be used to model the device behavior at varying levels o detail. The development o embedded sotware or the embedded processor section ollows the same low as any other embedded sotware design or an ARM processor. Altera provides GNUPro compilation and debug tools or embedded sotware development with Quartus II sotware subscriptions. With the use o SOPC Builder, a graphical user interacebased system design tool, all necessarry header and coniguration iles are generated automatically. The Altera MegaWizard Plug-in Manager (a graphical user interace utility) provides the designers the ability to set the operational parameters or the embedded processor. The MegaWizard outputs a system build descriptor ile (.sbd), which describes the set-up o the device, including the ollowing characteristics. whether the device boots rom an external lash device or an external FPGA coniguration device processor endian-ness the device memory map whether or not the bridges between the stripe and the PLD are used coniguration o integrated peripherals (timers, UART, SDRAM, EBI) peripheral input-voltage levels peripheral output conigurations the requency o operation (settings or the PLLs) or Processor and SDRAM controller 2 Altera Corporation

3 The.sbd ile produced by the MegaWizard Plug-In is used in both the hardware and sotware design lows. In addition to parameterization o the embedded stripe, the MegaWizard Plug-In produces iles used in the FPGA logic design and veriication, as well as instantiating simulation models or the hardware and sotware cosimulation. The iles produced are the ollowing..v or.vhd iles containing instantiations o the embedded processor and dual-port RAM blocks and header iles, as ollows: or Verilog iles, module instance containing stripe structural code, plus an include ile or VHDL iles, entity instance containing stripe structural code, plus.vhd package, plus additional template component declaration (VHDL 87 only) a C language header ile, containing deinitions o the memory map an assembly language header ile, containing deinitions o the memory map a block symbol ile, needed or instantiation in a Quartus II sotware Block Design File Whenever the Excalibur MegaWizard Plug-In updates the.sbd ile, it automatically recreates these iles. Figure 1 shows the Excalibur MegaWizard process. Ater running the Excalibur MegaWizard Plug-In, the system development low varies slightly, based on the method o coniguration. The remainder o this document describes the low or creating system iles or coniguring the devices as a processor, ollowed by coniguring the device as an FPGA. Altera Corporation 3

4 Figure 1. Excalibur MegaWizard Process Excalibur MegaWizard Plug-in GUI HDL/H Generator System Build Descriptor File (.sbd) HDL Template C/C++ Header File (.h) Stripe Declaration File and Header File (.v or.vhd) Block Symbol File (.bs) Booting rom Flash Via the Altera Bootloader Altera provides a bootloader or use when booting rom external lash memory. The bootloader initializes the device registers according to the MegaWizard output, including setting up the memory map o the device; and then loads the sotware into RAM. It resets the watchdog timer and inally sets the endian-ness o the processor, beore passing control to the user s code. Figure 2 shows the toollow or coniguration rom lash memory. 4 Altera Corporation

5 Figure 2. Coniguration rom Flash SOPC Builder (optional) Excalibur MegaWizard Plug-in Sotware Design Entry HDL Template.v or.vhd stripe declaration System Build Descriptor File (.sbd).h.h,.c,.ccc Hardware Design Entry.v or.vhd chip design Sotware Build Environment Synthesize (ater satisactory simulation).ed Intel.hex Filter.sbi MakeProgFile.o Loader Library Link and convert object ile to.hex.hexout Altera Corporation 5

6 When a device is conigured using the Altera lash bootloader, the required output at the end o a successul design compilation is an Intel.hex ile. To run a hardware compilation and produce a.hex ile or coniguring a device rom lash memory, proceed as ollows. 1. Run the Excalibur MegaWizard Plug-In to conigure the embedded logic. 2. Create an Intel.hex ile or the sotware image using either the compiler/linker provided with the Quartus II sotware in sotware mode or a preerred utility. 1 Sample startup code or Excalibur is provided with the EPXA10 or EPXA1 Development Board Getting Started User Guides available on The code provides examples o initializing stack pointers, setting up interrupt handlers, enabling caches and MMU, and linking to C runtime libraries. See the Hello World design ile descriptions in the user guides to ind the speciic ile containing the example code. I the.hex ile does not contain an entry point, it is assumed to be the irst address in the.hex ile. The ARM FromEl utility does not speciy an entry point in the.hex ile, even i it is non-zero, so the irst address is always used. 3. Use the Quartus II sotware to compile the design, generating a slave binary image (.sbi) ile. 4. Use the MakeProgFile command-line utility to merge the.hex ile, the.sbd ile, and the.sbi PLD image into an object ile. Makeprogile, one o the Excalibur utilities, is an application that allows you to create programming iles and generate memory initialization iles. Other Excalibur utilities allow you to set up the programming hardware, and download applications to lash memory. See Excalibur Device Utilities on page 11 or additional details on the these Utilities. 6 Altera Corporation

7 5. Use the GNUPro linker arm-el-ld, or the ADS linker armlink, to link the object ile produced by MakeProgFile, with the boot library boot.a, to produce an executable and linkable ormat (.el) ile. 6. Use the GNUPro tool arm-el-objcopy, or the ADS tool romel to create a.hex programming ile. Steps 4 through 6 can also be accomplished by using Quartus II sotware mode and selecting the FLASH coniguration option. Alternatively, the steps can be speciied in a makeile to be called rom the Quartus sotware command line ater the build. Reer to The XA10 or XA1 Development Board Getting Started User Guides or sample makeiles. Ater the programming ile has been loaded into the device, and at the instant when execution is transerred to the user s code, the device is conigured as ollows. Reer to The EPXA1 or EPXA10 Development Board Getting Started User Guide or details on coniguring the devices. The device registers have been initialized to the coniguration requested in the Excalibur MegaWizard Plug-in Manager. The embedded processor is in SVC mode. IRQ and FIQ are disabled; the status lags are undeined The processor is executing ARM code The instruction and data caches, and the MMU are disabled; the cache contents are invalid The embedded processor's registers are undeined The watchdog timer is running, unless DEBUG_EN is asserted. The watchdog is reset immediately beore execution is transerred to the user's code. See the Excalibur Device Hardware Reerence Manual or more inormation. Altera Corporation 7

8 Coniguration rom an External Source Figure 3 shows the sequence o tool use or coniguration rom an external coniguration device, via passive coniguration schemes. Figure 3. Passive-Serial or Passive-Parallel Coniguration Schemes SOPC Builder (optional) Excalibur MegaWizard Plug-in Sotware Design Entry HDL Template.v or.vhd stripe declaration System Build Descriptor File (.sbd).h.h,.c,.ccc Hardware Design Entry.v or.vhd chip design Sotware Build Environment Synthesize (ater satisactory simulation).ed Intel.hex Filter.sbi MakeProgFile.po,.so 8 Altera Corporation

9 When a device is conigured using a passive-serial or passive-parallel coniguration scheme, the required output at the end o a successul hardware compilation is one or more o the ollowing ile types..po.so.rb.tt.hexout The ollowing steps explain how to create a programming ile o the hardware design. 1. Run the Excalibur MegaWizard Plug-in to conigure the embedded logic. 2. Create and synthesize the RTL, using either the Quartus II sotware or third-party hardware development tools. 3. Speciy a sotware image (in Intel.hex ormat) to be merged into the programming ile at the itting stage. The Quartus II sotware always produces a.po and a.so ile. Optionally,.rb,.tt, and.hexout iles are also produced. The ollowing steps explain how to generate a coniguration ile or the sotware design. 1. Create an Intel.hex ile or the sotware image using either the compiler/linker provided with the Quartus II sotware in sotware mode, or a preerred utility. I the.hex ile does not speciy an entry point, it is assumed to be the irst address in the.hex ile. 1 The ARM FromEl utility does not speciy an entry point in the.hex ile, even i it is non-zero, so the irst address is always used. 2. Use the Quartus II MakeProgFile command-line utility to merge the.hex ile, the.sbd ile, and the partial SRAM object ile (.pso) PLD image into the appropriate types o programming ile. Altera Corporation 9

10 Makeprogile, one o the Excalibur utilities, is an application that allows you to create programming iles and generate memory initialization iles. Other Excalibur utilities allow you to set up the programming hardware and download applications to lash memory. See Excalibur Device Utilities on page 11 or additional details on the Excalibur Utilities. You can also use Quartus II sotware mode, to generate the programming ile. Speciy the.pso PLD image to be merged with the.hex ile and the Quartus II sotware then produces.po,.so,.rb, and.tt iles. Ater the programming ile has been loaded into the device, and at the instant when execution is transerred to the user's code, the device is conigured as ollows. Reer to The EPXA1 or EPXA10 Development Board Getting Started User Guide or details on coniguring the devices. The device registers have been initialized to the coniguration requested in the Excalibur MegaWizard Plug-in Manager. I no application has been loaded, the processor is held in reset; i an application is present, the processor is released rom reset, with the ollowing characteristics. the embedded processor is in SVC mode IRQ and FIQ are disabled; the status lags are undeined the processor is executing ARM code the instruction and data caches, and the MMU are disabled; the cache contents are invalid the embedded processor's registers are undeined The watchdog timer is running, unless DEBUG_EN is asserted. See the Excalibur Device Hardware Reerence Manual or more inormation. 10 Altera Corporation

11 Excalibur Device Utilities This section presents descriptions and usage guidelines or the our Excalibur device utilities, Makeprogile, Exc_ lash_programmer, Jtagconig, and Memimagedecoder. These utilities are installed automatically when you install the Quartus II sotware. I you do not need to modiy the hardware portions o the design and do not require the Quartus II sotware, you can install the utilities separately via the standalone installer available on the SOPC Builder CD-ROM. Makeprogile Makeprogile is a command line utility that merges the hardware logic image with the sotware application to generate a boot data ile, serial programming iles, or simulation model initialization iles. Usage [-h/--help] [-v/--version] Displays help message Displays version o makeprogile {passive programming ile options} <project>.sbd [<ilename>.pso] [<ile>.hex] {lash programming ile options} <project>.sbd [<ilename>.sbi] [<ile>.hex] {simulation init ile options} <project>.sbd [<ile>.hex] Passive programming ile options are: -e/--serial-eprom <EPC2/EPC4/EPC8/EP16> [-s/--so <ilename>.so] [-p/--po <ilename>.po] [-r/--rb <ilename>.rb] [-t/--tt <ilename>.tt] Generates.SOF ile Generates.POF ile(s) Generates.RBF ile Generates.TTF ile [-x/--hexout <ilename>.hexout]generates.hexout ile [-a/--hexout-addr <address>] Speciies start address or.hexout Altera Corporation 11

12 Flash programming ile options are: -b/--bootdata <ilename>.o -nc/--no-compression data Suppress the compression o preload Simulation initialization ile options are: -m/--model-init <basename> Base name o model initialization iles I the target system is to operate in boot-rom-lash mode, you can use the makeprogile utility to create a boot data ile. I you speciy a Slave Binary Image File (.sbi) as an input ile on the command line, the bootloader conigures the programmable logic device using the data rom that SBI File. I the target system is to operate in boot-rom-serial mode, the makeprogile utility is used to generate any Programmer Object Files (.po), SRAM Object Files (.so) Raw Binary Files (.rb), Tabular Text Files (.tt), or Hexadecimal (Intel-Format) Output Files (.hexout) that you speciy. In boot-rom-serial mode, the memory initialization data rom the hexadecimal (Intel-Format) ile(s) (.hex) that you speciy as input ile(s) is merged with the programmable logic Partial SRAM Object File (.pso) that was generated by the Quartus II Compiler when you compiled a hardware design. This produces the coniguration bitstream, which is ouput as.po,.so,.rb,.tt and/or.hexout iles. You must speciy the type o serial EEPROM you are going to use, using the --serial-eprom command-line option described below. You can also use the makeprogile utility to generate initialization iles or the Excalibur embedded processor stripe simulation model, using the --model-init <basename> command-line option described below. When the makeprogile utility is used to generate simulation model initialization iles, the --model-init <basename> command-line option described below speciies the non-extension part o each ile name. For example, the "simtest" part o simtest.dpram0. The extension o each simulation model initialization ile name is provided by the makeprogile utility. The makeprogile utility reads inormation rom the iles you speciy, and writes any output iles that you speciy with the command-line options below. 12 Altera Corporation

13 A System Build Descriptor ile (.sbd), speciied with the Excalibur MegaWizard Plug-In, which is available rom the MegaWizard Plug-In Manager (Tools menu), is used by the makeprogile utility to generate register writes to set up the stripe. I hexadecimal (Intel-ormat) iles (.hex) are speciied as input iles or memory initialization, the SRAM, DPSRAM and/or SDRAM is initialized using the hexadecimal ile contents. Addresses in.hex iles are interpreted as physical addresses. Exc_lash_programmer The Exc_ lash_programmer is a stand-alone command line utility or programming Flash connected to the Expansion Bus Interace o the EPXA devices. The utility uses the ByteBlaster download cable via the JTAG interace. Version 2.2 o the lash programmer supports 16-bit lash devices, which are compatible with either the Intel 28FXX0C3 (primary OEM command set 0003) or the AMD AM29DL32XD (primary OEM command set 0002) advanced boot-block amilies. For more inormation on the Excalibur Flash Programmer and supported devices, reer to Application Note 143: Using the Expansion Bus Interace. Usage: exc_lash_programmer {options} <hexile.hex> The ollowing options are available: -a All the blocks are erased. The application quits ater executing this command -c <cable name> Selects which JTAG cable to use -n <n> Selects device number (or chains with two or more Excalibur devices) -e <n> Sets which EBI block to use -p Programs the lash rom the input ile -v Veriies contents o lash with input ile - Fast mode. Each used block is erased without compare. Old data is deleted (This option is especially appropriate or the EPXA1 device.) Altera Corporation 13

14 -r <256 byte aligned hex read size> Reads lash contents into ile -t <64-bit protection code> Sets 64-bit protection code -g Starts processor ater successul programming -o <64K aligned oset> Oset is subtracted rom every input hex address -h Help Jtagconig The JTAG Coniguration utility, jtagconig, allows you conigure the JTAG server on the host machine. It can also detect a JTAG chain and setup the download hardware coniguration. Usage: The ollowing options are available: --version --enum Displays version o jtagconig Enumerates devices present in the JTAG chain attached to the hardware. Names o devices are indicated or known devices. For example, with a ByteBlaster download cable present on LPT1 and other devices in the JTAG chain, typing jtagconig <return> generates the ollowing output: 1. ByteBlaster on LPT DD EPXA DD EPXA-ARM ! DD! EP20K1000E ! DD EPC DD EPC DD EPC2 2. MasterBlaster on COM2 Unable to lock chain (hardware not attached) 14 Altera Corporation

15 Devices that cannot be used because the jtagconig utility does not have enough data or the JTAG chain, are indicated with an exclamation mark. Although the EP20K1000E above has been recognized, it cannot be used because the jtagconig utility does not recognize devices on either side o it. --add <type> <port> Tells the JTAG server that the speciied hardware type is attached to the speciied port. USB devices are auto-detected and thereore do not need to be added using the jtagconig utility. For example, typing --add byteblaster LPT1, or --add masterblaster com2, adds the speciied devices to the JTAG chain. --remove <id> Removes the hardware speciied by the ID number. The ID is the listed number o the device ater typing jtagconig -- enum. In the example above, ByteBlaster is listed as device 1, and MasterBlaster as device 2. Thus, typing jtagconig --remove 2, would remove the MasterBlaster rom the JTAG chain. --help Displays help message Memimagedecoder Memimagedecoder is a command line utility that retrieves the Excalibur embedded processor stripe initialization data rom an SRAM object ile (.so), and boot data rom the boot data ile <project name>_bootdata.o respectively. Memimagedecoder then displays the data in readable ormat to allow the code to be examined. Usage: memimagedecoder [-h/--help/] Displays help message memimagedecoder[-v/--version]displays the version o memimagedecoder memimagedecoder <ilename>.so [output-option] Load Excalibur stripe initialization data rom an SOF and output the data in a readable ormat. Altera Corporation 15

16 memimagedecoder <ilename>o [output-option] Load Excalibur stripe initialization data rom a bootdata object ile and output the data in a readable ormat. The ollowing output option is available. When the output option is not speciied, all the data interpreted rom the input ile is displayed in the command window. -o/--output ilename Output ile 101 Innovation Drive San Jose, CA (408) Applications Hotline: (800) 800-EPLD Literature Services: lit_req@altera.com Copyright 2003 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, speciic device designations, and all other words and logos that are identiied as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks o Altera Corporation in the U.S. and other countries. All other product or service names are the property o their respective holders. Altera products are protected under numerous U.S. and oreign patents and pending applications, maskwork rights, and copyrights. Altera warrants perormance o its semiconductor products to current speciications in accordance with Altera s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out o the application or use o any inormation, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version o device speciications beore relying on any published inormation and beore placing orders or products or services. All rights reserved. 16 Altera Corporation