ASL: Auburn Simulation Language and AUSIM: Auburn University SIMulator. Chuck Stroud Professor Electrical & Computer Engineering Auburn University
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1 ASL: Auburn Simulation Language and AUSIM: Auburn University SIMulator Chuck Stroud Professor Electrical & Computer Engineering Auburn University
2 Example of Digital System Design The integrated circuit design process Note all the simulation Ensure design works and assists in debugging design errors (design verification) Detect defects in manufacturing process or faults in system (testing) To simulate a circuit, we must describe it in a manner that can be interpreted and understood by the simulator System Level Register Level Gate Level Fault Simulation (gate level fault model) Fault Simulation (transistor level fault model) Transistor Level Requirements & Specifications Architectural Design Functional Design Logic Design Physical Design Fabrication Process Wafer Level Testing Saw Apart Packaging & Testing Behavioral Simulation (VHDL) Functional Simulation (RTL VHDL or Verilog) Logic Simulation (AUSIM) Circuit Simulation (PSPICE) C. E. Stroud (/5) ASL and AUSIM 2
3 Design Capture with HDLs All of these captured design descriptions can go to simulation: Netlist Connections of components made via signal name ASL for example Schematic Connections explicit (via wires) or via signal name Produces a netlist for simulation Higher level language (VHDL or Verilog) Synthesis to gate level netlist C. E. Stroud (/5) ASL and AUSIM 3
4 Netlist Example Circuit statement: Circuit name Inputs Outputs Component statements: Component type Component instantiation Inputs signals Output signals A S B G SN G2 G3 G2 G3 G4 # ASL description of MUX ; ckt: MUX in: A B S out: Z ; not: G in: S out: SN ; and: G2 in: A SN out: G2 ; and: G3 in: S B out: G3 ; or: G4 in: G2 G3 out: Z ; Z C. E. Stroud (/5) ASL and AUSIM 4
5 Design Verification Schematic (or logic diagram) A SN G2 G2 G G4 Z S G3 B G3 Netlist ckt: MUX in: A B S out: Z ; not: G in: S out: SN ; and: G2 in: A SN out: G2 ; and: G3 in: S B out: G3 ; or: G4 in: G2 G3 out: Z ; Logic Simulation Netlist Logic Simulator Simulation Results Stimuli C. E. Stroud (/5) ASL and AUSIM 5
6 Simulation Design Capture Input Schematic diagram A G2 S B G SN G2 G3 G3 G4 Netlist ckt: MUX in: A B S out: Z ; not: G in: S out: SN ; and: G2 in: A SN out: G2 ; and: G3 in: S B out: G3 ; or: G4 in: G2 G3 out: Z ; Z S Computer Emulation A NOT B AND AND Data structures hold logic values Pointers to source logic values OR Z logical operations performed by computer C. E. Stroud (/5) ASL and AUSIM 6
7 Design Verification Logic simulation results used to: Verify proper operation of design Find & fix problems (errors) in design aka: debugging Input Stimuli (or vectors) # ABS ; Simulation Results # ABS Z ; compare simulation results to truth table Truth Table C. E. Stroud (/5) ASL and AUSIM 7 A B S Z
8 Types of Simulators Compiled Simulator (AUSIM) Simulation continues until circuit is stable No changing logic values within circuit aka: unit delay or logic simulator All gates in circuit have a finite unit delay Good for initial design verification Shorter simulation times Event-Driven Simulator Simulation events scheduled in time Circuit may not be stable when input changes aka: timing simulator Gates have real delays base on intrinsic & extrinsic factors More accurate for real circuits Longer simulation times and more computer intensive C. E. Stroud (/5) ASL and AUSIM 8
9 Overview of ASL ASL: Auburn Simulation Language A positional notation hardware description language for digital logic Also referred to as a netlist Used with AUSIM (Auburn University SIMulator) for Logic simulation and design verification C. E. Stroud (/5) ASL and AUSIM 9
10 Delimiters include: Delimiters Space, tab, and new line Used to separate all: Keywords Some reserved characters Specifically # and ; Names Gate names Signal (net) names Can be used freely Missing delimiter is a frequent source of syntax errors C. E. Stroud (/5) ASL and AUSIM
11 Reserved Characters Can not (or should not) be used in names: # (pound sign) Denotes beginning of comment statement ; (semicolon) Denotes end of statement : (colon) Denotes keyword C. E. Stroud (/5) ASL and AUSIM
12 Keywords include: CKT: (ckt:) Keywords Denotes circuit statements IN: (in:) and OUT: (out:) Denotes inputs and outputs of circuit or gate AND: (and:), OR: (or:), NAND: (nand:), NOR: (nor:), & NOT: (not:) Denotes elementary logic gate component statements Keywords always end with colon : Can be all uppercase or all lowercase letters But not a mixture of upper and lower case C. E. Stroud (/5) ASL and AUSIM 2
13 Three types include: Comment statements Statements Include textual information or remove portions of circuit without deleting Cannot be nested inside circuit or component statements Circuit statements Define attributes of circuit Name of circuit Primary inputs and outputs of circuit Component (gate) statements Defines attributes of gate Unique name of gate Inputs and output connections of gate C. E. Stroud (/5) ASL and AUSIM 3
14 Statements All statements can be multiple lines Good for large comments Good for large number of inputs or outputs In circuit statements In component statements Good for readability and debugging Common mistakes: Missing ; at end of statement Missing delimiter before ; at end of statement C. E. Stroud (/5) ASL and AUSIM 4
15 Statement Formats All statements end with a delimiter then ; Comment statements Begin with # followed by space Example: # this is a valid comment ; Circuit statement CKT: cktname IN: input name(s) OUT: output name(s) ; Example: ckt: FullAdder in: A B Cin out: SUM Cout ; Only one circuit statement per ASL file C. E. Stroud (/5) ASL and AUSIM 5
16 Statement Formats Component statements GATE: name IN: input(s) OUT: output(s) ; where GATE: can be: AND: (and:), OR: (or:), NAND (nand:):, NOR: (nor:) Any number of inputs NOT: (not:) Only one input for NOT: Example: nand: G in: A B C D E F out: Z ; One component statement for every gate in circuit C. E. Stroud (/5) ASL and AUSIM 6
17 Naming Conventions Need unique names for: Circuit, Gates, Signals (nets) Any combination of characters & numbers Except reserved characters & keywords Case sensitive Example: X and x are two different names Signal name can be same as gate name Common practice by designers to: Reduce number of names Aid in debugging Recommend use of short but meaningful names C. E. Stroud (/5) ASL and AUSIM 7
18 ASL Example A S B logic diagram SN G2 G2 G G3 G3 G4 Z AUSIM Simulation.asl.vec ASL # ASL description for MUX ; ckt: MUX in: A B S out: Z ; not: G in: S out: SN ; and: G2 in: A SN out: G2 ; and: G3 in: S B out: G3 ; or: G4 in: G2 G3 out: Z ;.aud AUSIM.out C. E. Stroud (/5) ASL and AUSIM 8
19 Input Stimulus for Simulation aka input vectors or just vectors Vectors are used for design verification The most important part of our work!!! Each vector is a multi-bit binary value to be applied to inputs of circuit during simulation Vectors are chosen to expose design errors Vectors applied one at a time with output responses reported by simulator for each input vector We study output responses to input vectors to find design errors Design verification is only as good as the set of vectors used for simulation C. E. Stroud (/5) ASL and AUSIM 9
20 AUSIM Input Vectors One vector = a string of s and s No delimiters in a vector Comments are optional and can be added between vectors Comments are passed to simulation results file (.out) by AUSIM Bits in vector are applied in ordered of inputs in circuit (CKT:) statement Example vector File for MUX # Z= ; # Z= ; C. E. Stroud (/5) ASL and AUSIM 2
21 Checks for Common Problems Typically part of CAD tool Schematic capture (when generating netlist) Simulator (AUSIM) AUSIM checks for potential design errors Common syntax errors Cannot always identify exact error Actual error may be just before point of complaint Unconnected gate inputs and outputs Multiple gates driving same net C. E. Stroud (/5) ASL and AUSIM 2
22 Other AUSIM Checks Duplicate names for gates, inputs, outputs Reserved characters (#, _, ;) in names Multiple or missing CKT: statement in ASL Missing IN: keyword after circuit/gate name Some rare errors Incorrect number of inputs to inverter Net names too long Maximum length currently 35 characters C. E. Stroud (/5) ASL and AUSIM 22
23 AUSIM Files All all input and output files are ASCII text Any text editor can be used to create files Be sure to save as text file When using default file names be sure to delete.txt suffix from some editors (like NotePad) before executing AUSIM Example: change name.asl.txt to name.asl Suggest turn off hide extensions for file types Windows Explorer -> Tools -> Folder Options -> View Uncheck hide extensions for file types AUSIM checks for missing input files C. E. Stroud (/5) ASL and AUSIM 23
24 AUSIM Files (default names) Input files (files you generate) ASL file (name.asl) Input vector file (name.vec) Output files (files AUSIM generates) Errors and Warnings (ausim_errs.txt) Checks for syntax and potential design errors Generated when processing ASL Circuit audit (name.aud) Circuit statistics and analysis (can help with debug) Generated when processing ASL Simulation results file (name.out) Generated during logic simulation C. E. Stroud (/5) ASL and AUSIM 24
25 Accessing AUSIM L2.2 Go to my ELEC 22 web page Click download AUSIM L2.2 executable for PC download is ausiml22.zip file that contains: ASL and AUSIM version L2.2 manual Windows PC executable (ausim.exe) Multiplexer example files discussed in manual Unzip, extract, and save files on your computer or desktop C. E. Stroud (/5) ASL and AUSIM 25
26 Starting AUSIM L2.2 In My Computer or Windows Explorer, go to directory where you saved ausim.exe ASL & vector files must be in this directory MUX example files should already be there Double click ausim.exe Type file prefix name Using default names Click Process Fix any errors Click Simul8 Results in name.out Use text editor to view C. E. Stroud (/5) ASL and AUSIM 26
27 MUX Example Files # multiplexer ; ckt: mux in: a b s out: z ; not: sn in: s out: sn ; and: a in: a sn out: a ; and: a2 in: b s out: a2 ; or: o in: a a2 out: z ; # vectors give Z= ; # end of vectors ; ASL VEC OUT # AUSIM Simulation Results ; # abs z ; # vectors give Z= ; # end of vectors ; C. E. Stroud (/5) ASL and AUSIM 27
28 AUSIM Audit File Area analysis Number of gates, G Number of gate I/O, G IO Gate usage Loading and delays Nets with no driver help find unconnected gate inputs Also nets with no loads help Intrinsic + extrinsic propagation delay Timing path analysis For all paths Number gate delays, G del Propagation delay, P del Worst case path AUSIM (L2.2) Area/Performance Analysis Results Circuit 'mux' from ASL file 'mux.asl' Area Analysis: Number of primary inputs: Pi= 3 Number of primary outputs: Po= Number of gates: G= 4 Number of gate I/O pins: Gio= Gate type and number of uses: AND: 2 OR: NOT: NAND: NOR: Loading and delays: Name LoadsDriver Delay=intrinsic+extrinsic: a Input =+ b Input =+ s 2 Input 2=+2 z OR 2=2+ Output sn NOT 2=+ a AND 3=2+ a2 AND 3=2+ Worst Case Timing Path Analysis: path= z->a->a: Gdel=2, Pdel=5 path= z->a->sn->s: Gdel=3, Pdel=7 path= z->a2->b: Gdel=2, Pdel=5 path= z->a2->s: Gdel=2, Pdel=5 Worst Case: Gdel=3, Pdel=7 C. E. Stroud (/5) ASL and AUSIM 28
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