Hardware Modelling. Design Flow Overview. ECS Group, TU Wien
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1 Hardware Modelling Design Flow Overview ECS Group, TU Wien 1
2 Outline Difference: Hardware vs. Software Design Flow Steps Specification Realisation Verification FPGA Design Flow 2
3 Hardware vs. Software: Design Flow C-Code VHDL-Code Function counter(int a, int b) { Begin if a=b then count:= 0 else Architecture rtl of Counter is Begin if a=b then count<= 0 else Development tools Development tools Binary code edif - file 3 Memory is loaded, hardware is not changed Gates and connections are configured no software is running on the device
4 Embedded Systems Design Flow System Definition Specification Decomposition Partitioning } Project Management/ System Engineering } Hardware Software CoDesign Software Firmware Hardware Hardware Modelling 4
5 Hardware Modeling 5 Specification Functional specification High-level design description Detailed design description Realisation Hardware description Hardware implementation Verification Review Formal verification Functional verification Effort and Time 1-5 % % %
6 Hardware Modeling 6 Specification Functional specification High-level design description Detailed design description Realisation Hardware description Hardware implementation Verification Review Formal verification Functional verification Effort and Time 1-5 % % 5-10 %
7 Hardware Modeling Specification Functional specification High-level design description Detailed design description Realisation Hardware description Hardware implementation 7 Verification Review Formal verification Functional verification
8 Specification (1) Functional description Operational principle User interface Transaction level description Project proposal / project description 8
9 Specification (2) High-level design description Requirement specification Decomposition in modules Interface definition Physical Interfaces (Module ports, pins, etc). Logical Interfaces (data types, e.g.) Behavioral Interfaces ( reactions on a stimulus) independent implementation of submodules possible Testcase specification Reference document for all implementations 9
10 Specification (3) Detailed Design Description Refinement of the modules Detailed description of structure and functionality Structure: submodules and their interconnection Behavior: State diagrams, Activity diagrams, References to requirements Traceable decisions Modeling languages: UML, SysML Technical manual for hardware description 10
11 Specification - Summary Functional description Incomplete specification High Level Design Decription Common design document Complete specification Submod & IF definition Detailed Detailed Detailed Design Design Description Design Description Description Detailed Design Description Detailed Design Description Requirements must be covered 11 Mod 1 Mod 2 Mod n
12 Hardware Modeling Specification Functional specification High level requirement description Detailed design description Realisation Hardware description Hardware implementation 12 Verification Review Formal verification Functional verification
13 Realisation Hardware Description Design views, levels of abstraction Modeling languages Hardware Implementation Synthesis Technology mapping Place and Route 13
14 Realisation Hardware Description Design views, levels of abstraction Modeling languages Hardware Implementation Synthesis Technology mapping Place and Route 14
15 Hardware Description: Design Entry(1) Design Appraoch Behaviour while input Read Schilling Calulate Euro Display Euro Structure Speicher RS Interface 8 PS/2 µp IO-Ctrl Interface Geometry µp IO-Ctrl PS/2 RS different views describe the same chip Y-diagram
16 Hardware Description: Design Entry (2) Levels of abstraction System level Memory CPU IO Busl 16 Algorithmic level µp IO-Ctrl ROM RS232 Interface 8 PS/2 Interface Register Transfer level MUX Register Counter ALU E >1 Gate level & B A C 16 Transistor level
17 Hardware Description: Design Entry (3) Schematic Entry Gates (AND, OR, INV, FF, ) Modules (ALU, Register, Decoder, ) IP Core (Processor core, communication controller) Text based Entry Boolean equations VHDL, Verilog SystemC, SystemVerilog 17
18 Realisation Hardware Description Design views, levels of abstraction Modeling languages Hardware Implementation Synthesis Technology mapping Place and Route 18
19 Hardware Implementation Synthesis Mapping of a hardware description to hardware components cnt_ntx: process (load,up_down, cnt_val) begin +1-1 cnt_val cnt_val_nxt <= cnt_val; up_down Mux if load ='1' then cnt_val_nxt <= SET_VAL; elsif up_down = '1' then cnt_val_nxt <= cnt_val + 1; else cnt_val_nxt <= cnt_val - 1; end if; end process cnt_ntx; Transformation load + SET_VAL Mux cnt_val_nxt 19
20 Hardware Implementation Technology mapping Mapping of hardware components to the selected library up_down +1-1 Mux cnt_val LUT LUT + SET_VAL LUT load Mux Technology Mapping cnt_val_nxt 20
21 Hardware Implementation Place and Route Mapping of library elements to the real chip LUT LUT LUT LUT Place and Routing LUT LUT 21
22 Hardware Modelling Specification Functional specification High level requirement description Detailed design description Realisation Hardware description Hardware implementation 22 Verification Review Formal verification Functional verification
23 Verification Review High level of abstraction Formal verification Equivalence checking Model checking Functional Verification Simulations Prototype 23
24 Verification Review High levels of abstraction Formal verification Equivalence Checking Model checking Functional Verification Simulations Prototype 24
25 Review (1) Check for correctness High level of abstraction Usually not automated Code review by colleagues 25
26 Review (2) Implementation Specification Prototype Review 26
27 Review (3) The human factor Implementation Specification Interpretation Prototype Review 27 designer reviews design against its own interpretation, not against the specification
28 Verification Review High levels of abstraction Formal verification Model checking Equivalence Checking Functional Verification Simulations Prototype 28
29 Formal Verification (1) Model Checking Identifies generic problems Violation of user defined rules Implementation Specification Interpretation Properties Model Checking Prototype 29
30 Formal Verification (2) Equivalence check Compares to two models +1-1 cnt_val up_down Mux LUT LUT + set_val load Mux LUT cnt_val_nxt generic implementation technology specific gates 30 same functionality, but different models
31 Verification Review High levels of abstraction Formal verification Equivalence Checking Model checking 31 Functional Verification Simulations Prototype
32 Simulation (1) Testbench Generate stimuli, emulate testcases Record / check response Metric: Coverage Testbench Inputs/ Outputs 32 db
33 Simulation (2) Different abstraction levels Behavioural simulation Prelayout simulation Postlayout simulation Refinement 33
34 Simulation (3) Trade-off speed vs. accurancy Simulation time for a SoC Real Hardware Timeless C Model RTL HDL 4 seconds 1 minutes 4 days Gate Level 5 weeks 34
35 Simulation (3) Trade-off speed vs. accurancy Simulation time for a SoC Real Hardware Timeless C Model RTL HDL 4 seconds 1 minutes 4 days Gate Level 5 weeks 35
36 FPGA Design Flow (1) Specification Place & Route, Timing analysis Design documents Netlist, timing annotations Design Entry Bitstream Generation VHDL Bitstream Synthesis & Technology Mapping FPGA configuration Netlist 36
37 FPGA Design Flow (2) Specification Design documents Design Entry VHDL Behavioral simulation Ok? no Synthesis & Technology Mapping yes no Netlist Pre-layout simulation Ok? 37 yes
38 FPGA Design Flow (3) Design Entry Place & Route, Timing analysis Netlist, timing annotations Post-layout simulation Ok? no Bitstream Generation yes Bitstream FPGA configuration Test Ok? no 38
39 The End Questions? 39
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