MIDTERM#1. 2-(3pts) What is the difference between Von Neumann & Harvard processor architectures?

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Tobias Bates
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1 CSE421-Microprocessors & Microcontrollers-Spring 2013 (March 26, 2013) NAME: MIDTERM#1 1- (2pts) What does MSP stand for in MSP430? Why? Mixed Signal Processor. It contains both analog and digital circuitry. 2-(3pts) What is the difference between Von Neumann & Harvard processor architectures? In Harvard Architecture, the volatile (data) and nonvolatile (program) memories are treated as separate systems,each with its own address and data bus. In von Neumann Architecture, there is only a single memory system in the von Neumann or Princeton architecture. Thismeans that only one set of addresses covers both the volatile and nonvolatile memories. 3- (5pts) List the differences between a microprocessor and a microcontroller. A microprocessor contains a complete digital processor,which includes at least the arithmetic logic unit and associated registers. A microprocessor needs many other components to support it. These include a (large) external memory and the other components that can be found on the motherboard of a personal computer. The integration of as many functions as possible on to the same chip as the processor gives rise to the microcontrollers. Microcontrollers have nearly fixed hardware built around a central processingunit (CPU).The CPU controls a range of peripherals, which may provide both digitaland analog functions such as timers and analog-to-digital converters. Small devices usually include both volatile and nonvolatile memory on the chip but larger processorsmay need separate memory. Their operation is usually programmed using a languagesuch as C or C++. Microprocessors have larger address bus (32, 64-bit) whereas microcontrollers can address (8, 16-bit) a small memory with no paging or banking. OS can run on microprocessors whereas small microcontrollers are unlikely to use an OS at all. Sometimes, a specialized real-time OS (RTOS) is used in microcontrollers for real-time apps. 1

2 4- (30pts) For the following machine code, write down the corresponding instruction. Refer to cheat sheet. a. (5pts) 0x B6 MOV.W #0x03b6,SP b. (5pts) 0x8DFB FFF5 c. (5pts) 0xF6EF 4031 d. (5pts) 0xD2E2 002A BIS.B #4, 2Ah(SR) e. (5pts) 0x40B2 5A MOV.W #5A80, 0x0120(SR) f. (5pts) 0x1005 RRC.w R5 5- (10pts) Consider the machine code 0x23FE. You are also given the PC value as 0x312a. a. (5pts) Tell me which jump instruction is being executed. JNE/JNZ offset=0x3fe b. (5pts) Calculate the new PC value for the case when the status register zero bit (Z) is 0. Refer to Fig. 2. If status register zero bit is 0 and no jump happens. Therefore, new PC= 0x312c. If status register zero bit is 1 and jump happens. Therefore, new PC= 0x312a +2+(-4) = 0x3128 because (0x3FE *2 = 0x3FC = -0x004 (two s complement)) 6- (10pts) Write the assembly for the following: while (! (P1IN & 0x01)); go: BIT.B #1, &P1IN JEQ go 2

3 7-(10pts) Convert the following C-code into assembly. Complete the corresponding assembly below the C-code. C-code: #include <msp430xg46x.h> void main (void){ volatile unsigned int i; WDTCTL = WDTPW WDTHOLD; P2DIR = 0x04; //Stop Watchdog Timer //Configure P2.2 as Output } while(1){ i=30000; do (i--); while (i!=0); P2OUT ^= 0x04; } //Infinite loop //Delay //Toggle Port P2.2 using an exclusive-or Assembly: - LOOP mov.w #0x7530,0x0000(SP) DECREMENT dec.w 0x0000(SP) tst.w 0x0000(SP) jne DECREMENT xor.b #4,&P2OUT ;Toggle P2.2 using an exclusive-or jmp LOOP ;Infinite loop 3

4 8-(12pts) Use the assembly that you wrote in question 7. Define a subroutine called DELAY. - bis.b #4,&P2OUT ; Configure P2.2 as Output LOOP call #DELAY xor.b #4,&P2OUT ;Toggle P2.2 using an exclusive-or jmp LOOP ;Infinite loop DELAY sub.w #2,SP ; Allocate 1 word (2 bytes) on stack mov.w #0x7530,0x0000(SP) DECREMENT dec.w 0x0000(SP) tst.w 0x0000(SP) jne DECREMENT add.w #2,SP ; Yes: finished, release space on stack ret 9-(10pts) The assembly in question 8 is re-written such that the delay value is passed as an argument. Fill in the blanks accordingly. - bis.b #4,&P2OUT ; Configure P2.2 as Output push.w #0x7530 ; Push delay parameter on to stack LOOP call #DELAY incd.w SP ; Release space used for parameter xor.b #4,&P2OUT ; Toggle P2.2 using an exclusive-or jmp LOOP ; Infinite loop DELAY; DECREMENT dec.w 0x4(SP) tst.w 0x4(SP) jne DECREMENT ret 10-(8pts) What happens when an interrupt is requested in MSP430? The PC and SR are pushed on the stack. What happens after the interrupt service routine? First SR pops, and next PC pops from the stack. 4

5 CHEAT SHEET Fig.1 Format I (Double Operand Instruction) Fig.2 Jump InstructionFormat Fig.3 Single Operand InstructionFormat Fig.4 Addressing modes Fig.5. MSP430 Instruction Set 5

Block diagram of processor (Harvard)

Block diagram of processor (Harvard) Register transfer view of Harvard architecture Separate busses for instruction memory and data memory Example: PIC 16 load path OP REG AC 16 16 store path rd wr data