LHCb TELL1 VHDL firmware development guide

Transcription

1 LHCb 2004-xxx LPHE 2004-xxx January 18, 2005 LHCb TELL1 VHDL firmware development guide Version 2.4 Guido Haefeli 1 Abstract This document is a guide to the TELL1 VHDL framework installation. 1 Guido.Haefeli@epfl.ch

2 Contents 1 Revision 1 2 TELL1 Framework Quick Installation 1 3 TELL1 FPGA framework 1 4 CVS repository at Cern 2 5 FPGA design development Software Installation of the FPGA Advantage and Quartus Settings for tool invocations Setting up the system variables Library mapping file Altera DDR SDRAM IP-Core To do Check if this is correct now Quartus setup Creating programming file for the TELL Framework updates and user design implementation User VHDL libraries User design hierarchy guideline Testbench stimulus 9 8 Solving problems 10 9 Common synthesis warnings! Quartus place and route common warnings 12 i

3 1 Revision Version 2.4, Small changes in 5.1 Version 2.3, Change the installation root directory of the whole framework software from e:\hdl to <hdl_dir> HDL The directory for the application data of the HDL Designer is now given correctly HDL_Designer_Series. This needs to be changed when copied to the directory named without underscores. Add some comments for the library mapping files (.hdp) how to deal with it by the user. Add CVS user instruction chapter. Add TELL1 mailing list information. 2 TELL1 Framework Quick Installation If you think you will not need any detailed instructions because you know already well how to deal with the TELL1 framework you should just pass through the following: Copy the Tool settings for the HDL Designer into your application data directory (see section 5.1), this is needed for HDL Designer users only. Edit and copy the batch file to do the System Environment Variable settings. The file is located in <hdl_dir>\framework_installation (see section 5.2) and should be copied to a save location in order to save it from being overwritten by a future update. Check that the synthesis invocation runs the Tcl script for the version rom contents assignment at the end of synthesis located at <hdl_dir>\vhdl_export\built_version_script. Check if the Quartus project assignments are correct for your case (eg use optical receiver option for pin assignments) Make an new copy of the user specific libraries if you start from scratch, which means copy <hdl_dir>\template_tell1_vhdl_libraries to <hdl_user_dir>\user_tell1_vhdl_directory After the.sof files of the two FPGAs have been generated use Quartus conversion of programming files to generate the combined.pof file. There is an example stored in <hdl_dir>\programmer_files\tell1_setup_comp.cof 3 TELL1 FPGA framework A large amount of VHDL programming has been done to implement the FPGA functionality on the TELL1 board. This guide should help the users during installation and development for the specific needs of the different sub-detectors. Please report any 1

4 problems concerning the installation to in order to improve and facilitate the task for new users. A mailing list for the TELL1 VHDL developer has been created to supply the interested people with news and issues during the development. Please sign you on the list to get the latest information directly. To read some instructions see: The mailing list is called: lhcb-project-tell1-vhdl@cern.ch 4 CVS repository at Cern To keep up with new versions of the framework software and all files being used in its context, a public accessible CVS repository has been set up at: To download the complete latest framework version you can use the link Download Tarball on the website or use your CVS client. The CVS client has of course many features that can be useful during the development. For the framework development I use TortoiseCVS which is a Windows based CVS client. For installation see: which is the Homepage of the CVS service at Cern. It is not foreseen that the user specific designs are committed to the TELL1 repository. 5 FPGA design development Software It is clear that during the time of the development several changes of the software version will be necessary. It is impossible to guarantee compatibility with older software versions since the evolution of the software is very fast. Regarding the large amount of design blocks, libraries and components used in the TELL1 framework that a text only based development can not be envisaged. The design of the framework has been all written by the support of the Mentor Graphics HDL designer software. The software nevertheless allows to export the automatically generated VHDL text files. For present design of the framework can be completely copied and used with the Mentor software having the advantage of the graphical support. It has to be pointed out, that for designers that do want to use an import procedure into an other graphical environment that each time a new version of framework will be released, a new import procedure has to be done. For the present design the following software has been used: Mentor Graphics FPGA Advantage 6.3 containing HDL Designer Series Version: ModelSim SE Version: 5.8c LeonardoSpectrum Version: 2004a Update 1 Precision Synthesis Version: 2003c Update 1 Altera Quartus II version 4.1 SP2 2

5 Remark that the use of an older version of HDL Designer is not possible since on the pre 6.0 FPGA Advantage version the database is different. The FPGA Advantage is available for universities directly from Mentor Graphics Europe and does cost about 700 CHF including the direct support from Mentor. For more information see or if this link is not valid anymore contact the local Mentor support. 5.1 Installation of the FPGA Advantage and Quartus All necessary instructions for installation and licensing are given by Mentor Graphics and Altera. To import the tool option settings for the Mentor software the Application Data for the HDL Designer Series needs to be replaced with the one from the framework. Therefore, copy the directory <hdl_dir>\hdl_ini_files\hdl_designer_series to the Application Data Directory on your PC which is typically for W2K and XP at C:\Documents and Settings\<your user name>\application Data (if you do not find this directory with the Windows Explorer it is because Windows hides the system files (change the option). and change its name to HDL Designer Series! (The underscores is a fix for the CVS clients and server that do not support blanks in the filenames) The directory has to be called identical as it is given above. Note that the following settings for the tool options are needed: Settings for tool invocations By copying the HDL Designer Series application data directory (see 5.1) to your local machine, the following list of invocation settings are automatically done. You should maybe verify that this is true! The ModelSim simulation time resolution needs to be 1 ps (required for the DDR SDRAM Core). The language option for VHDL has to be set to VHDL-93 since the files used for the simulation stimulus are called with this formalism and the VHDL-87 does not support the assignments for example: data<=x"abcd" (usage of hexadecimal notation for vectors. [ optional ] On starting up the ModelSim simulation a script is called with the command do start.do, where the initialization of the simulation is done. This script is stored in simulation downstream directory of each library. So for example for the user_pp_fpga_lib it is in user_pp_fpga_lib\pp_fpga\work. This might be helpful to add in your own testbenches. [ if Leonardo or Precision is used ] At synthesis invocation set the device to the Altera - Stratix - EP1S20C780 or EP1S25C Speed Grade - 40 MHz. 3

6 [ if Leonardo or Precision is used ] At synthesis invocation the ADD_IO_Pads option is not which means un-set. [ if Leonardo is used ] For Leonard synthesis invocation the Optimization Hierarchy Preserve is set. This leaves an easy way to set a logic lock region around the L1B interface with all its components. [ if Precision is used ] The flatten option is automatically used. 5.2 Setting up the system variables To cope with different installation directories for the framework system variables are used. During the development the design was located in e:\hdl and if you still find some problems where this path appears, you can report on this so it can be replaced with the according variables (I put quite some effort to avoid it the e:\hdl problem!). To make the settings more convenient a script to set the variables is given in: <hdl_dir>\framework_installation\set_environment_variables.bat It takes care to setup the used variables. Copy the script to a location where it is not overwritten by a future update of the framework, so you can use your settings again. The following variables are set (remark that the current settings on my local PC are given as an example: user_tell1_vhdl_libraries ="e:\hdl\template_tell1_vhdl_libraries" Contains the libraries designed by the users. If it points to the template (examples), the HDL Designer library browser will show you the designs made already. It contains the implementations for the specific processing blocks but also the top level chips for pp and synclink FPGAs. This libraries will be updated with every new version and the user should create their own top level designs. If you have not started yet with the design, copy the temlate_tell1_vhdl_ libraries into your implementation directory and start working. Try to compile the design before you change anything to verify if the installation is correct. Take care that the location of your design is not within the <hdl_dir> path, so an new version of the framework will not overwrite your design accidently. common_tell1_vhdl_libraries ="e:\hdl\common_tell1_vhdl_libraries" This is the location of the common libraries vhdl_libraries ="e:\hdl\vhdl_libraries" Contains some FPGA vendor specific libraries as stratix for the back annotation simulation and altera_mf and lpm to simulate the so called Altera mega functions vhdl_algorithms ="e:\hdl\vhdl_algorithms" Contains L1 pre-processor algorithm designs 4

7 vhdl_sim_data ="e:\hdl\vhdl_sim_data" This is where the testbench is accessing files for read and write. It contains also the memory initialization files. memory_ini ="e:\hdl\vhdl_sim_data\memory_ini" This is the location of the memory initialization files. hdl_root ="e:/hdl" This is the root directory of the installation used for Quartus assignment scripts. Remark that this uses the Unix convention for the path definition (slashes instead of backslashes). user_libs_root ="e:/hdl/template_tell1_vhdl_libraries" This is the root directory of the user specific design (default set to the template libraries) ddr_sdram_core_root ="c:/megacore/ddr_sdram-v2.2.0" Also used by Quartus the SDRAM core root directory. 5.3 Library mapping file To import the library mappings from the framework, the TELL1 framework project library mappings needs to be specified in the HDL Designer. The file to point to is hdl\hdl_ini_files\common_tell1_libraries.hdp for the common or team libraries and hdl\hdl_ini_files\template_tell1_libraries.hdp for the user specific design libraries. The mapping can be easily done by clicking on the path written after the My Project in the main window of the HDL Designer. Remark: If you start your own design you should create based on the template_tell1_libraries.hdp an new library mapping file that you store at a save location (not removed by future updates). You would then typically rename it to user_tell1_libraries.hdp and add your special libraries created by you. 5.4 Altera DDR SDRAM IP-Core To develop a custom design for the Pre-Processor FPGAs (PP-FPGAs), the DDR SDRAM IP-Core and its license dongle is needed. This license has to be ordered from ALTERA and cost for with the 90% university discount about 500 CHF. In August 2004 Altera started to give the licenses for several IP Cores for the Quartus users for free. So the DDR SDRAM core can be obtained free of charge but only if you use Quartus as a full paying customer (not a university 10% value customer). For evaluation the core license is also available as a so called OPEN Core license which does allow to simulate the design on RTL level but without programming and backannotation file generation. Since the IP-Cores normally do not come as a source code but are protected by encryption, the usage of the core for simulation and place-and-route is explained in more detail below.follow the instructions below. I strongly recommended to spend some minutes to read the instructions of for the core available on the Altera website. 5

8 5.4.1 To do Read this section first entirely before installing: With the new distribution of DDR SDRAM core version the simulation with ModelSim pre-compiled libraries is again possible. Installation is now much easier then it was with the VIP END USER simulation interface. The IP-Core installation package is available at the ALTERA web site but require a registration ( It is nevertheless also given in <hdl_dir>\ddr_sdram_core_install. The installation has to be performed only once for setting up the system; for updates on the framework the installation remains. Remark that the installation directory of the MegaCore (ddr_ sdram-v2.2.0) does not support any blank space characters in the path name (do not install it in Program Files)! Check if this is correct now After installation, make sure that the system variable DDR_SDRAM_v2.2.0_ROOTDIR is set correctly according to your installation. In the HDL designer the auk_ddr_user_ lib has to be set as a protected library. This is important to allow the synthesis tool to pass the IP Core as a black box to the place-and-route tool (Quartus). In ModelSim the pre-compiled library auk_ddr_lib needs to be imported. The files of the libraries are in: <MegaCore_install_dir>\ddr_sdram-v2.2.0\sim_lib\modelsim\auk_ddr_lib This is done by starting ModelSim (for example try to simulate your design) F ile Import library where you are asked to name the library and its location. Check first if the library mapping to the auk_ddr_lib is not already correctly done. 5.5 Quartus setup To use Quartus with the VHDL framework, the EDIF netlist is imported that has been created by Leonardo or Precision (or any other synthesis tool). This netlist file is specified in the Quartus project. The netlist can be found in the downstream directory of the synthesis tool. For example for Leonardo: for the PP-FPGA : $user_tell1_vhdl_libraries\user_pp_fpga_lib\pp_fpga_ struct\netlist for the SyncLink-FPGA: $user_tell1_vhdl_libraries\user_synclink_fpga_ lib\synclink_fpga_struct\netlist The Quartus projects can be found at: for the PP-FPGA : $user_tell1_vhdl_libraries\user_pp_fpga_lib\quartus for the SyncLink-FPGA: $user_tell1_vhdl_libraries\user_synclink_fpga_ lib\quartus and the assignment scripts for creating all assignment of a project: 6

9 for the PP-FPGA : $user_tell1_vhdl_libraries\user_pp_fpga_lib\quartus_ tcl for the SyncLink-FPGA: $user_tell1_vhdl_libraries\user_synclink_fpga_ lib\quartus_tcl The Tcl scripts run on the Quartus Tcl shell and regenerate the project, pin and timing assignments. The scripts are divided in several file where its name indicate their contents. The pp_fpga_top.tcl and synclink_fpga_top.tcl are the main script files from where the subscripts are called. The project assignments done with the tcl scripts also set the user libraries which can be checked if made correct with the Quartus GUI with Assignents Settings U serlibraries and should be for the PP-FPGA: <hdl_dir>/common_tell1_vhdl_libraries/common_mgwz_generated <MegaCore_install_dir>/ddr_sdram-v2.2.0/lib <hdl_dir>/template_tell1_vhdl_libraries/user_pp_fpga_lib/quartus_tcl <hdl_dir>/vhdl_algorithms/algorithm_mgwz_gen_lib and for the SyncLink-FPGA: <hdl_dir>\vhdl_projects\mgwz_generated <hdl_dir>\vhdl_user_libraries\synclink_fpga_lib\quartus_tcl <hdl_dir>\vhdl_algorithm\algorithm_mgwz_gen_lib This path settings are part of the project assignments of Quartus and normally do only need to be adapted if the path names do not correspond in your case, all settings should be made automatically after the installation script for the framework has been executed. 5.6 Creating programming file for the TELL1 The programming file that goes in the single EEPROM located on the TELL1 needs the combined PP FPGA and SyncLink FPGA programmer file. Use the generated programming files for each chip (located in the Quartus project directory) to combine the two files into one. The settings that are needed are: eprom name = EPC16 output filename = <hdl_dir>\programmer_files\tell1.pof n pages = 1 width = 2 mode = 1 7

10 sof data, page flags = 1,bit0...quartus\synclink_fpga.sof sof data, page flags = 2,bit1...quartus\synclink_fpga.sof jtag user code = ffffffff disable pullups = 1 auto usercode = 0 compression = 1 use internal clock = 1 clock frequency = 10 MHz clock divisor = 1 A conversion setup is located at: <hdl_dir>\programmer_files\tell1_setup_comp. cof (remark that the.sof file path and output file path has to be adapted to your installation - do you know how to use path variables in this file???) 6 Framework updates and user design implementation You have to be aware that each time a new version of the framework is released the VHDL design, the FPGA Advantage and the Quartus settings of the common and the user specific has to be merged. To do so the following strategy will be employed: The Tool settings for HDL Designer, ModelSim, Leonardo and Quartus are fully updated with the common design settings. If you think you need some special settings for a certain tool, please use a user specific location and the settings can be integrated by calling a script or the tool settings. To update the common libraries all directories in <hdl_dir> except <hdl_dir> \<detector_name>_tell1_vhdl_libraries are renewed (overwritten). Make sure that you do not overwrite your custom design! The components in the common libraries that have changed its interfaces have to be updated in the HDL Designer. The changes for the update will be documented at each new version and in any case the compilation for simulation will not work if interfaces for components are not consistent. If you get an error message as: Error: The following component instances are out of date with respect to their symbol interface:- I10 Use Reconcile Interface command to resolve differences. you should update the corresponding component by: Selecting the component which interface has changed right click with mouse Update Component 8

11 6.1 User VHDL libraries The so called user libraries contain the design specific to the sub-detectors (users). This includes the top level design for each of the two FPGAs pp fpga and synclink fpga which each is accommodated in their specific libraries. In addition user specific libraries for certain tasks on the chip are foreseen. For the algorithm development even an other variable and its directory has been created. The user libraries are: hdl\<detector>_tell1_vhdl_libraries\user_pp_fpga_lib hdl\<detector>_tell1_vhdl_libraries\user_synclink_fpga_lib hdl\<detector>_tell1_vhdl_libraries\user_ecs_interface_lib hdl\<detector>_tell1_vhdl_libraries\user_pp_tx_link_lib hdl\<detector>_tell1_vhdl_libraries\user_rx_synchronizer_lib hdl\<detector>_tell1_vhdl_libraries\user_synclink_zero_supp_lib 6.2 User design hierarchy guideline Attention! All user specific designs should be placed on the top level of the chip hierarchy to allow for easy changes in interface for these components. In the design the user specific components should be marked with a blue panel. Additional library mappings can be added to structure the user design. These library mappings will need to be updated in the framework library mappings. Ask somebody that has permission to do so. 7 Testbench stimulus To cope with the needs of various simulation stimulus a set of files accessed by the VHDL testbench used. These files contain all information like input event data, pedestal values, IP header ram data but also ROM and RAM initialization values. In addition the log files of the sent Ethernet frames as well as the log files of the buffer fill state are written generated. The location of the files can be set in the test_bench_lib.sim_pkg. The memory initialization is done with Intel HEX format files which can easily created with Quartus. Unfortunately no system variables are recognized in the file location. The Quartus Megawizard generated components are edited in the HDL designer so the path for the memory initialization file reads "<hdl_dir>\vhdl_sim_data\memory_ini\data_gen_ini.hex" as an example for the data generator RAM 2. 2 The path given in Quartus Megawizard is not correct inserted in the generated file. Check if the path is written correctly at all 3 locations in the file! 9

12 8 Solving problems Inconsistent design after compilation recompile all design units T asks SetGenerateAlways T asks SetCompileAlways Force the HDL designer to regenerate and ModelSim libraries recompilation Sometimes the standard libraries compiled for simulation need to be recompiled since the time stamp of the compilation indicates ModelSim not to use the library anymore. Recompilation of the libraries can be done by starting ModelSim from the Windows Start menu. All library mappings existing are shown on the Library Tab. To recompile a library for example the ieee, use Compile Compile. Indicate the destination library (ieee) at the Library selection, indicate the VHDL source files E:\program\FPGAdv63LSPS\Hds\hdl_libs\ieee\hdl and select all source files. The options for the compilation can be checked, use the VHDL-93 dialect. 9 Common synthesis warnings! "<hdl_dir>\vhdl_projects/mgwz_generated/hdl/ddio18_out_syn.vhd", line 13: Warning, altera_mf_components is not declared in library altera_mf. This warning is only occurring if the altera mf library is added to the package references LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; in HDL Desinger. The package is inserted to the references automatically (after accepting it as a default option) when you insert a megawizard generated component in the design. You can either ignore the warning or remove the package reference. port ecs_reg(63)(2) is connected to a disabled tristate, possibly unconnected port in design. These are the unused ecs register. If you implement an 8-bit register the other 24-bits are reported as disabled tristate,... (ignore it) "<hdl_dir>\vhdl_projects/synclink_hlt_lib/hdl/mep_data_ builder_beha.vhd",line 171: Warning, others clause is never selected. In the state machines there is always the assignment when others => null; 10

13 This ensures that no logic is implemented for the possible not defined states of the state machine (ignore it) "<hdl_dir>\vhdl_projects/mgwz_generated/hdl/synclink_hlt_ infifo_256x32_syn.vhd", line 659: Warning, component dcfifo has no visible entity binding This message shows that all altera mf components are passed to Quartus as a black box. Leonardo does not pass any contents but the parameters of the components to Quartus. (ignore it) "<hdl_dir>\vhdl_projects/ecs_interface_lib/hdl/ecs_ synclink_fpga_rd_mux_ecs_read_mux1.vhd", line 25: Warning, index value 0 TO 255 could be out of prefix index constraint 0 TO 63. This message occurs due to the fact that an array type has been used and its index can exceed the defined types range. If you are sure that its correct you can ignore it. "<hdl_dir>\vhdl_user_libraries/synclink_fpga_lib/hdl/ synclink_fpga_struct.vhd", line 265: Warning, initial value for HLT_IPv4_header_rdata is ignored for synthesis. Initial values are convenient for the simulation but will not be passed to to the place and route (ignore it or remove the assignment in your design). "<hdl_dir>\vhdl_projects/synclink_hlt_lib/hdl/hlt_mep_assemble_ design.vhd",line 22: Warning, input eventdata_ef is never used. This is a signal that has been defined but never used. It might be used later and its convenient to keep it. "<hdl_dir>\vhdl_projects/spi3_interface_lib/hdl/egress_new_ass_ egress_new_assignments.vhd",line 159: Warning, PL3_TMOD_int is not assigned under reset; need loops to preserve its value. You should assign the signal value under the reset! This costs you resources! Acceptable warnings: altera mf components is not declared disabled tristate, possibly unconnected port in design. others clause is never selected no visible entity binding could be out of prefix index constraint 0 TO 63 initial value is ignored for synthesis input eventdata ef is never used Not acceptable warnings: not assigned under reset; need loops to preserve its value 11

14 10 Quartus place and route common warnings EDA synthesis tool is specified as LeonardoSpectrum, but Library Mapping File is not specified This should be gone soon! Synthesized away the following node(s): Warning: Synthesized away the following RAM node(s): Warning: Synthesized away node HLT_MEP_generator:mep_assemling_qdr_if MEP_header_fifo_32x32:I8 scfifo:scfifo_component scfifo_g7p:auto_generated a_dpfifo_ndp:dpfifo dpram_fem:fiforam altsyncram_dlc1:altsyncram1 ram_block2a18 This occurs if some bits of a memory are not used. If for example a memory 32-bit wide is defined but only 24-bits are used. (You can ignore or adapt the memory to its needed size) Output port clk0 of PLL enh_pll6_clk_40:i7 altpll:altpll_component pll feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance. (ignore it) TRI or OPNDRN buffers permanently disabled Warning: Node tri_analyzer_out_19 Warning: Node tri_ecsint1 Warning: Node tri_qdr_k_fb_out Warning: Node tri_fpga_scl Warning: Node tri_fpga_sda This comes from unused signals on the chip (you should not see any signal that you want to use in this list!) Output pins are stuck at VCC or GND Warning: Pin Ana_TP_Clk_Out stuck at GND Warning: Pin IndvRST[2] stuck at GND Warning: Pin L1_Throttle stuck at GND This are also unused pins. Several warning occur during place and route of the DDR core which can all be ignored. For example 12

15 Warning: Reduced register l1buffer:i4 ddr_core_48:i16 ddr_core_48_auk_ddr_sdram:ddr_core_48_auk_ddr_sdram_inst auk_ddr_controller:ddr_control cs_last_ne_cs_this with stuck data_in port to stuck value GND project add_assignment Here a summary of the warnings that you can obtain and live with it: Library Mapping File is not specified Synthesized away the following RAM node(s): jitter performance depends on switching rate... TRI or OPNDRN buffers permanently disabled Output pins are stuck at VCC or GND 13