Lab 2 EECE473 Computer Organization & Architecture University of Maine

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1 Lab 2: Verilog Programming Instructor: Yifeng Zhu 50 Points Objectives: 1. Quatus II Programming assignment: PIN assignments, LEDs, switches; 2. Download and test the design on Altera DE2 board 3. Create digital circuit by using Verilog code 4. Design 7-segment display In-lab demonstration: 1. Light up a LED by using a switch (Schematic Design) 10 points 2. Light up a LED if more than two switches are 1 (Verilog Design) 15 points 3. Correctly show the hex values on 7-segment Displays 25 points What to hand in: 1. TA Checkoff sheet with TA s grading and signature. 1. Introduction to DE2 Development Board The DE2 (shown on the above) is designed to support a wide range of experiments. It combines a variety of logic and I/O devices onto a single printed-circuit board and allows you to configure and control these devices to create different applications. The logic devices on the DE2 are an FPGA (a programmable logic device) and several memory components (SDRAM, SRAM, and flash RAM). The I/O devices on the DE2 are a small LCD display, numerous LEDs (lights), and switches. In addition, the DE2 has connections to a variety of external I/O The author (Yifeng Zhu) gratefully acknowledges borrowing parts of this homework assignment from ENGINEERING 100 (Section 700) Introduction to Computing Systems 2006 by Dr. Peter Chen. 1

2 devices, including PS/2 (keyboard and mouse), USB, VGA (video), audio (microphone and speaker), TV, Ethernet, RS-232 (serial port), Secure Digital and IrDA (infrared). 2. Light up a LED by using a Switch (Schematic Design) LEDs (light-emitting diodes) are digital lights. Each LED is controlled (i.e., set to on or off) by a single wire. The LED will be on if the wire has the value 1 and off if the wire has the value 0. A switch is used to input a value (0 or 1) to the DE2. There are two types of switches on the DE2. 1) Create a new project a. File New Project Wizard b. Named the project as LED_Schematic c. Select the device EP2C35F672C6 (DE2) in the Cyclone II family, which is the FPGA chip on the Altera DE2 board. You can also change the device: Assignments Device Select Cyclone II EP2C35F672C6 as the target chip 2) Create a Schematic Design, and make it as the top entity. The Schematic Design will have one input pin and one output pin. The input pin is named as SW[0] and the output pin is named as LEDR[0]. The two PINs are connected together via a NOT gate. 3) Perform PIN Assignments: Perform Pin Assignments. If you want to assign the pin numbers for inputs and outputs manually, you can find the Pin table from A simpler approach is to import the pin assignments from a cvs file and label your pins according to the name shown in the pin table. (For example label one 4-bit input as SW[7..4] to assign that value to the corresponding 4 switches.) You can get the DE2 PIN assignment comma separated value (csv) format file from (DE2_pin_assignments.csv). Copy this file to your working directory and import it into your project by choosing Assignments Import Assignments. After importing the PIN assignments, you can use pin names, instead of pin numbers to directly access input or output pins. For example, the DE2 board provides 18 toggle switches, called SW17 0, that can be used as inputs to a circuit, and 18 red lights, called LEDR17 0, that can be used to display output values. 4) Synthesis/Compile: The compile process may take over twenty minutes. A smart compiler can significantly reduce the compile time. Follow the menu: Processing Compiler Tool Analysis & Synthesis Settings. If your project is large (such as Project 2 and 3 of this course), enabling smart compilation will significantly save you compilation time. 2

3 Downloading the LED_Schematic.sof file to the DE2 board through USB-Blaster. a) Connect the DE2 board to the host computer by means of a USB cable plugged into the USB- Blaster port. b) Turn on the power to the DE2 board. Ensure that the RUN/PROG switch is in the RUN position. c) Select Tools Programmer. d) If not already chosen by default, select JTAG in the Mode box. Also, if the USB-Blaster is not chosen by default, click the "Hardware Setup..." button and select the USB-Blaster in the window that pops up. Note: if USB-Blaster does not appear, go to "Devices" on the Windows 2000 Professional window and check the box that says "Altera USB-Blaster" e) If you use your own computer to program the Altera DE2 boards, you might need to install the USB-Blaster Driver. You can download the driver from here: f) The configuration file yourproject.sof should be listed in the window. If the file is not already listed, then click g) Add File and select it. h) Click the box under Program/Configure to select this action. i) Press Start to configure the FPGA. 5) Demo to TA if you complete. 3. Light up a LED by using Switches (Verilog Coding) In this project, you will develop a project based Verilog that uses a DIP switch to light up a LED. Specifically, if more than two switches are 1, then the LED is lighted up. The dip switches used in this circuit are SW[0] (labeled SW0 on the board) and SW[1] (labeled SW1 on the board). During the testing, move the levers of these switches between 0 (closer to the front edge of the DE2) and 1 (away from the front edge of the DE2) and observe the output of LEDR[0] (the LED directly above SW[0]). 1) Create a new project a. File New Project Wizard (Make sure that this project is stored in a different folder than your previous one) b. Named the project as LED_Verilog c. Select the device EP2C35F672C6 (DE2) in the Cyclone II family 2) Perform PIN import as Step 2 of the previous project. 3) Crate a Verilog File invoked through Quartus' File menu (File New Device Design Files tab Verilog HDL File) 4) Type in the following Verilog code and save the code as top.v a. Save the code as top.v (File Save As). Quartus adds the ".v" extension automatically, so you need only type top as the file name. b. Make sure the box is checked to add this file automatically to the current project. 5) Demo to TA after you complete. 3

4 // file top.v // The output of the LED will be 1 if and only if // two or more of the dip switches are 1. module top( input wire [17:0] SW, output reg [17:0] LEDR); begin if (SW[0] == 1'b1 && SW[1] == 1'b1) begin LEDR[0] = 1'b1; end else if (SW[0] == 1'b1 && SW[2] == 1'b1) begin LEDR[0] = 1'b1; end else if (SW[1] == 1'b1 && SW[2] == 1'b1) begin LEDR[0] = 1'b1; end else begin LEDR[0] = 1'b0; // default value is 0 end end endmodule A few points about the Verilog code above: a. The code describes the circuit for the module top. This module name corresponds to the name of the toplevel design entity you specified when creating the Quartus project. b. 1'b0 and 1'b1 are how you express numbers in Verilog. The number before the ' indicates the number of bits in the number; in this case, we are expressing a 1-bit number. The letter after the ' indicates which base the number is in; in this case, we are expressing numbers in base 2, or binary, denoted by the letter b. The number after the letter indicates the value of the number; in this case, we are expressing the numbers 0 and 1. Other possible bases for expressing numbers are decimal (denoted by the letter d) and hexadecimal (denoted by the letter h). For example, an 8-bit number with the value 200 could be written as 8'd200 or 8'b or 8'hc8. c. The module takes an input variable (SW) and produces an output variable (LEDR). Each variable is declared as an array of 18 bits (bits 17 through 0). The file top.qsf that you downloaded when you created the project connects the SW array to the 18 dip switches on the DE2. Similarly, top.qsf connects the LEDR array to the 18 red LEDs on the DE2. d. Each variable in Verilog (such as SW and LEDR) is declared as type wire or type reg. Use the following rule to determine which type to use for a variable: if the variable is assigned a value in the module (through a statement such as LEDR[0] = 1'b1), it should be declared reg. Otherwise it should be declared wire. e. The code block starting with specifies the relationship between LEDR and SW. It specifies how the value of LEDR[0] (the 0th element of the LEDR array) depends on the values of SW[0], SW[1], and SW[2]. means "continuously drive the wire LEDR based on the value of computed in this block. In this case, the value will depend on SW and will implement a "majority vote": the output of the LED will be 1 if and only if two or more of the dip switches are 1. f. The syntax of Verilog is similar to that of C++. a. The operators =, ==, and && have the same meaning as in C++. Other operators that have the same meaning as in C++ are comparison operators (<, >, <=, >=,!=), logical operators (&&,,!), 4

5 addition/subtraction (+, -), and bitwise operators (<<, >>, &,, ~). (Avoid using from multiply/divide (*, /), as they are difficult to synthesize into an FPGA circuit.) b. If... else if... else work exactly as they do in C++. All if statements in Verilog should end with an unconditional else clause. c. begin... end are used to group lines of code into a single block, just as {... } work in C++. d. As with C++, Verilog ignores white space, uses // or /*... */ for comments, and is case sensitive. 4. Seven-segment LEDs based on Multi-module Verilog Hexadecimal (base 16) is a common way to represent numbers in digital circuits. Each hex digit shows the value of 4 bits of the number (value 0-15): Value Hex A B C D E F Create a new Quartus project called SevenSegmentLED. As always, the top-level design entity for the project will be a module named top. Next, complete the Verilog module hexdigit. hexdigit takes as input a 4-bit number (in) and produces a 7-bit array of values (out) based on the input value. The bits of out are meant to control the segments of a 7-segment LED, as per the following diagram: out[5] out[4] out[0] out[6] out[3] out[1] out[2] For each bit of out, the value 0 causes that segment of the LED to be lit, and the value 1 causes that segment of the LED to be off. This is opposite from the LEDR devices you used in Lab 1. Complete the code so that the value of out returned by hexdigit generates a human-readable picture of the input value on the 7-segment LED. Remember that each output value must be defined for each combination of input values (usually by having an unconditional else clause in each if statement). Also remember that multi-bit values are specified with the mostsignificant bit on the left. E.g., out = 7'b ; is shorthand for: out[6] = 1'b0; out[5] = 1'b1; out[4] = 1'b1; out[3] = 1'b0; out[2] = 1'b0; out[1] = 1'b0; out[0] = 1'b0; 5

6 The table below shows how the segments in Figure 2 correspond to the pin names from the DE2_pin_assignments.csv file. Display Segment Wires for HEX0 Wires for HEX1 0 HEX0[0] HEX1[0] 1 HEX0[1] HEX1[1] 2 HEX0[2] HEX1[2] 3 HEX0[3] HEX1[3] 4 HEX0[4] HEX1[4] 5 HEX0[5] HEX1[5] 6 HEX0[6] HEX1[6] The same naming convention is used for all of the Hex displays on the DE2 board. The following is the top.v // file top.v module top( input wire [17:0] SW, output wire [6:0] HEX0, output wire [6:0] HEX1); hexdigit (SW[3:0], HEX0); hexdigit (SW[7:4], HEX1); endmodule The following is an incomplete hexdigit.v and please complete the code. // file hexdigit.v module hexdigit ( input wire [3:0] in, output reg [6:0] out); begin if (in == 4'h0) begin out = end endmodule Compile, download, and test your circuit. You should use the switches to control the value of 7-segment LEDs display. Demo to TA if you complete. 6

7 ECE 473 Lab 2 TA Checkoff Sheet Name: Date: Final Grade: 1) Light up a LED by using a switch (Schematic Design) 10 points Grade TA Signature:, Time: Comments: 2) Light up a LED if more than two switches are 1 (Verilog Design) 15 points Grade TA Signature:, Time: Comments: 3) Correctly show the hex values on 7-segment Displays 25 points Grade TA Signature:, Time: Comments: 7