Cortex-M4F Instructions used in ARM Assembly for Embedded Applications (ISBN )

Transcription

1 Cortex-M4F Instructions used in ARM Assembly for Embedded Applications (ISBN ) Function Call/Return Operation Notes Clock Cycles BL label LR return address; PC address of label BL is used to call a function BLX R n LR return address; PC R n -4 BX R n PC R n BX LR is used as function return B label PC address of label Load Integer Constant Operation Flags Notes Clock Cycles ADR R d,label R d address of label PC-4095 address PC+4095 MOV{S} R d, constant R d constant NZ 0 constant 55 (FF 6) & a few others MVN{S} R d, constant R d ~constant NZ 0 constant 55 (FF 6) & a few others MOVW R d, constant R d constant 0 constant (FFFF 6) MOVT R d, constant R d<3..6> constant 0 constant (FFFF 6) Load/Store Memory Operation Bits Notes Clock Cycles LDRB R d,[address mode] R d memory<7..0> (zero extended) 8 R d<3..8> 4 0's LDRSB R d,[address mode] R d memory<7..0> (sign extended) 8 R d<3..8> 4 copies of R d<7> LDRH R d,[address mode] R d memory<5..0> (zero extended) 6 R d<3..6> 6 0's LDRSH R d,[address mode] R d memory<5..0> (sign extended) 6 R d<3..6> 6 copies of R d<6> LDR R d,[address mode] R d memory<3..0> 3 LDRD R t,r t,[address mode] R t.r t memory<63..0> 64 Can't use register offset adrs mode 3 STRB R d,[address mode] R d memory<7..0> 8 STRH R d,[address mode] R d memory<5..0> 6 STR R d,[address mode] R d memory<3..0> 3 STRD R t,r t,[address mode] R t.r t memory<63..0> 64 Can't use register offset adrs mode 3 Load/Store Multiple Operation Notes Clock Cycles POP {register list} registers memory[sp]; SP+=4 #registers regs: Not SP; PC/LR, but not both PSH {register list} SP =4 #registers; registers memory[sp] regs: Neither SP or PC. LDMIA R n!,{register list} registers memory[r n] if! is appended, STMIA R n!,{register list} registers memory[r n] then R n += 4 #registers + #registers LDMDB R n!,{register list} registers memory[r n 4 #registers] if! is appended, STMDB R n!,{ register list} registers memory[r n 4 #registers] then R n = 4 #registers Move / Add / Subtract Operation Flags operand options: Clock Cycles MOV{S} R d,r n R d R n NZ ADD{S} R d,r n,operand R d R n + operand NZCV. constant ADC{S} R d,r n,operand R d R n + operand + C NZCV. R m (a register) SB{S} R d,r n,operand R d R n operand NZCV 3. R m,shift SBC{S} R d,r n,operand R d R n operand + C NZCV (Any kind of shift) RSB{S} R d,r n,operand R d operand R n NZCV Revised: June 7, 08 Page of 7

2 Cortex-M4F Instructions used in ARM Assembly for Embedded Applications (ISBN ) Multiply / Divide Operation Flags Notes Clock Cycles ML{S} R d,r n,r m R d (R n x R m)<3..0> NZC 3 3 3; C undefined MLA R d,r n,r m,r a R d R a + (R n x R m)<3..0> MLS R d,r n,r m,r a R d R a (R n x R m)<3..0> SMML R d,r n,r m R d (R n x R m)<63..3> SMMLA R d,r n,r m,r a R d (R n x R m)<63..3> + R a SMMLS R d,r n,r m,r a R d (R n x R m)<63..3> R a ses upper half of signed 64-bit product [ S ]MLL Rdlo,Rdhi,Rn,Rm RdhiRdlo Rn x Rm Signed/nsigned: 64 3x3 [ S ]MLAL Rdlo,Rdhi,Rn,Rm RdhiRdlo RdhiRdlo + RnxRm Signed/nsigned: [ S ]DIV Rd,Rn,Rm Rd Rn / Rm Signed/nsigned: Saturating Instructions Operation Min Max operand options Clock Cycles SSAT R d,n,operand R d operand n- n-. R m (a register). R m,asr constant SAT R d,n, operand R d operand 0 n 3. R m,lsl constant QADD R d,r n,r m R d R n + R m QSB R d,r n,r m R d R n R m 3 3 (Q if saturates) SIMD Signed Saturating ADD/SB Operation Min to Max Notes Clock Cycles QADD[ 8 6 Rd,Rn,Rm Rd[bits] Rn[bits] + Rm[bits] 8: - 7 to QSB[ 8 ] 6 Rd,Rn,Rm Rd[bits] Rn[bits] - Rm[bits] 6: - 5 to For bytes 0-3: bits 7..0, 5..8, 3..6, & 3..4 (No flags affected) SIMD nsigned Saturating ADD/SB Operation Min to Max Notes Clock Cycles QADD[ 8 6 Rd,Rn,Rm Rd[bits] Rn[bits] + Rm[bits] 8: 0 to 8 - QSB[ 8 ] 6 Rd,Rn,Rm Rd[bits] Rn[bits] - Rm[bits] 6: 0 to 6 - For halfwords 0 and : bits 5..0 & 3..6 (No flags affected) SIMD Signed Non-Saturating ADD/SB Operation GE Flags Notes Clock Cycles SADD[ 8 ] 6 Rd,Rn,Rm Rd[bits] Rn[bits] + Rm[bits] sum 0? : 0 Parallel operations: SSB[ 8 ] Rd,Rn,Rm Rd[bits] Rn[bits] - Rm[bits] diff 0? : 0 6 Four 8-bit operations, or two 6-bit operations SIMD nsigned Non-Saturating ADD/SB Operation GE Flags Notes Clock Cycles ADD[ 8 ] 6 Rd,Rn,Rm Rd[bits] Rn[bits] + Rm[bits] overflow? : 0 Parallel operations: SB[ 8 ] Rd,Rn,Rm Rd[bits] Rn[bits] - Rm[bits] diff 0? : 0 6 Four 8-bit operations, or two 6-bit operations Revised: June 7, 08 Page of 7

3 Cortex-M4F Instructions used in ARM Assembly for Embedded Applications (ISBN ) Q and GE Flag Instructions Operation Notes Clock Cycles For bytes 0-3: bits 7..0, SEL R d,r n,r m R d[bits] (GE[byte] = )? R n[bits] : R m[bits] 5..8, 3..6, & 3..4 MRS R d,apsr R d<3..7> NZCVQ R d<9..6> GE flags All other bots of R d are filled with zeroes. MSR APSR_nzcvq,R n NZCVQ R n<3..7> Other flags in the PSR MSR APSR_g,R n GE flags R n<9..6> are not affected. SIMD Multiply Instructions Operation Notes Clock Cycles SMAD R d,r n,r m R d R n<5..00> R m<5..00> + R n<3..6> R m<3..6> Sets Q flag if an SMSD R d,r n,r m R d R n<5..00> R m<5..00> R n<3..6> R m<3..6> SMLAD R d,r n,r m,r a R d R a + R n<5..00> R m<5..00> + R n<3..6> R m<3..6> SMLSD R d,r n,r m,r a R d R a + R n<5..00> R m<5..00> R n<3..6> R m<3..6> SMLALD R dlo,r dhi,r n,r m R dhi.r dlo += Rn<5..00> R m<5..00> + Rn<3..6> R m<3..6> SMLSLD R dlo,r dhi,r n,r m R dhi.r dlo += Rn<5..00> R m<5..00> Rn<3..6> R m<3..6> Appending "X" to instruction mnemonic changes operands to Rn<5..00> Rm<3..6> and Rn<3..6> Rm<5..00>. addition or subtraction overflows; does not saturate. Signed Multiply Halfwords Operation Notes Clock Cycles SMLBB R d,r n,r m R d R n<5..00> R m<5..00> SMLBT R d,r n,r m R d R n<5..00> R m<3..6> SMLTB R d,r n,r m R d R n<3..6> R m<5..00> SMLTT R d,r n,r m R d R n<3..6> R m<3..6> Pack Halfwords Operation operand options: Notes Clock Cycles PKHBT PKHTB R d,r n,operand R d,r n,operand Btm: R d<5..00> R n<5..00> Top: R d<3..6> operand<3..6> Top: R d<3..6> R n<3..6> Btm: R d<5..00> operand<5..00>. R m (a register). R m,lsl constant 3. R m,asr constant Shift constants: LSL: -3 ASR: -3 Compare Instructions Operation operand options: Notes Clock Cycles CMP R n,operand R n operand. constant pdates: NZCV CMN R n,operand R n + operand. R m (a register) pdates: NZCV TST R n,operand R n & operand 3. R m,shift pdates: NZC TEQ R n,operand R n ^ operand (any kind of shift) pdates: NZC Zero/Sign-Extend Instructions Operation operand options: Clock Cycles [ S ]XTB Rd, operand Rd Sign (S) extend or nsigned () extend operand<7..0>. R m (a register) [ S ] XTH Rd, operand Rd Sign (S) extend or nsigned () extend operand<5..0>. R m,ror constant (constant=8, 6 or 4) Revised: June 7, 08 Page 3 of 7

4 Cortex-M4F Instructions used in ARM Assembly for Embedded Applications (ISBN ) Conditional Branch Instructions Operation Notes Clock Cycles Bcc label Branch to label if cc is true "cc" is a condition code CBZ R n, label Branch to label if R n=0 Can't use in an IT block (Fail) or -4 CBNZ R n, label Branch to label if R n 0 Can't use in an IT block ITc c c 3 condition code Each c i is one of T, E, or empty Controls -4 instructions Shift Instructions Operation Flags operand options Notes Clock Cycles ASR{S} R d,r n,operand R d R n >> operand (arithmetic shift right) NZC Sign extends LSL{S} R. constant d,r n,operand R d R n << operand (logical shift left) NZC (typically -3) Zero fills LSR{S} R d,r n,operand R d R n >> operand (logical shift right) NZC. R m (a register) ROR{S} R d,r n,operand R d R n >> operand (rotate right) NZC right rotate RRX{S} R d,r n R d R n >> ; R d<3> C; C R n<0> NZC 33-bit rotate w/c Bitwise Instructions Operation Flags operand options Notes Clock Cycles AND{S} R d,r n,operand R d R n & operand NZC ORR{S} R d,r n,operand R d R n operand NZC EOR{S} R d,r n,operand R d R n ^ operand NZC BIC{S} R d,r n,operand R d R n & ~operand NZC ORN{S} R d,r n,operand R d R n ~operand NZC MVN{S} R d,operand R d ~operand NZC. constant. R m (a register) 3. R m,shift (Any kind of shift) Bitfield Instructions Operation Notes Clock Cycles BFC R d,lsb,width SelectedBitfieldOf(R d) 0 BFI R d,r n,lsb,width SelectedBitfieldOf(R d) LSBitsOf(R n) SBFX R d,r n,lsb,width R d SelectedBitfieldOf(R n) Sign extends BFX R d,r n,lsb,width R d SelectedBitfieldOf(R n) Zero extends Bits / Bytes / Words Operation Notes Clock Cycles CLZ R d,r n R d CountLeadingZeroesOf(R n) #leading 0's = 0-3 RBIT R d,r n R d ReverseBitOrderOf(R n) REV R d,r n R d ReverseByteOrderOf(R n) Pseudo-Instructions Operation Flags Replaced by Clock Cycles LDR R d,=constant R d constant MOV, MVN, MOVW, or LDR NEG R d,r n R d R n NZCV RSBS R d,r n,0 CPY R d,r n R d R n MOV R d,r n Revised: June 7, 08 Page 4 of 7

5 Cortex-M4F Instructions used in ARM Assembly for Embedded Applications (ISBN ) Floating-Point PSH/POP Operation Clock Cycles VPSH {FP register list} SP = 4 #registers, copy registers to memory[sp] + #registers VPOP {FP register list} Copy memory[sp] to registers, SP += 4 # registers Floating-Point Load Constant Clock Cycles VMOV S d,fpconstant fpconstant must be ±m -n, (6 m 3; 0 n 7) Floating-Point Copy Registers Operation Clock Cycles VMOV S d,s m S d S m VMOV R d,s m R d S m VMOV S d,r m S d R m VMOV R t,r t,s m,s m+ R t S m ; R t S m+ (S m, S m+ adjacent regs) VMOV S m,s m+,r t,r t S m R t ; S m+ R t (S m, S m+ adjacent regs) Floating-Point Load Registers Operation Clock Cycles VLDR S d,[r n] S d memory3[r n] VLDR S d,[r n,constant] S d memory3[r n + constant] VLDR S d,label S d memory3[address of label] VLDR D d,[r n] D d memory64[r n] VLDR D d,[r n,constant] D d memory64[r n + constant] 3 VLDR D d,label D d memory64[address of label] VLDMIA R n!,{fp register list} FP registers memory, R n = lowest address; pdates R n if write-back flag (!) is included. VLDMDB R n!,{fp register list} FP registers memory, R n-4 = highest address; Must append (!) and always updates R n + #registers Floating-Point Store Registers Operation Clock Cycles VSTR S d,[r n] S d memory3[r n] VSTR S d,[r n,constant] S d memory3[r n + constant] VSTR D d,[r n] D d memory64[r n] VSTR D d,[r n,constant] D d memory64[r n + constant] 3 VSTMIA R n!,{fp register list} FP registers memory, R n = lowest address; pdates R n if write-back flag (!) is included. VSTMDB R n!,{fp register list} FP registers memory, R n-4 = highest address; Must append (!) and always updates R n + #registers Revised: June 7, 08 Page 5 of 7

6 Cortex-M4F Instructions used in ARM Assembly for Embedded Applications (ISBN ) Floating-Point Convert Representation Operation Clock Cycles VCVT.F3.3 S d,s m S d (float) S m, where S m is an unsigned integer VCVT.F3.S3 S d,s m S d (float) S m, where S m is a s comp integer VCVT{R}.3.F3 S d,s m S d (uint3_t) S m, rounded if suffix R is appended VCVT{R}.S3.F3 S d,s m S d (int3_t) S m, rounded if suffix R is appended Floating-Point Arithmetic Operation Clock Cycles VADD.F3 S d,s n,s m S d S n + S m VSB.F3 S d,s n,s m S d S n S m VNEG.F3 S d,s m S d S m VABS.F3 S d,s m S d S m ; (clears FP sign bit, N) VML.F3 S d,s n,s m S d S n S m VDIV.F3 S d,s n,s m S d S n S m VSQRT.F3 S d,s m S d S m VMLA.F3 S d,s n,s m S d S d + S n S m VMLS.F3 S d,s n,s m S d S d S n S m 4 3 Floating-Point Compare Operation Clock Cycles VCMP.F3 S d,s m Computes S d - S m and updates FP Flags in FPSCR VCMP.F3 S d,#0.0 Computes S d - 0 and updates FP Flags in FPSCR VMRS APSR_nzcv,FPSCR Core CP Flags FP Flags (Needed between VCMP.F3 and conditional branch) Addressing Modes for floating-point load and store instructions (VLDR & VSTR): Addressing Mode Syntax Meaning Example [Rn] address = Rn [R5] Immediate Offset [Rn,constant] address = Rn + constant [R5,00] Shift Codes: Any of these may be applied as the shift option of "operand" in Move / Add / Subtract, Compare, and Bitwise Groups. Shift Code Meaning Notes LSL constant Logical Shift Left by constant bits Zero fills; 0 constant 3 LSR constant Logical Shift Right by constant bits Zero fills; constant 3 ASR constant Arithmetic Shift Right by constant bits Sign extends; constant 3 ROR constant ROtate Right by constant bits constant 3 RRX Rotate Right extended (with carry) by bit Revised: June 7, 08 Page 6 of 7

7 Cortex-M4F Instructions used in ARM Assembly for Embedded Applications (ISBN ) Addressing Modes for integer load and store instructions (LDR, STR, etc.): Any of these may be used with all variations of LDR/STR except LDRD/STRD, which may not use Register Offset Mode. Addressing Mode Syntax Meaning Example Immediate Offset [Rn] address = Rn [R5] [Rn,constant] address = Rn + constant [R5,00] Register Offset [Rn,Rm] address = Rn + Rm [R4,R5] [Rn,Rm,LSL constant] address = Rn + (Rm << constant) [R4,R5,LSL 3] Pre-Indexed [Rn,constant]! Rn Rn + constant; address = Rn [R5,00]! Post-Indexed [Rn],constant address = Rn; Rn Rn + constant [R5],00 Condition Codes: If appended to an FP instruction within an IT block, the condition code precedes any extension. (E.g., VADDGT.F3) Condition Code CMP Meaning VCMP Meaning Requirements EQ (Equal) == == Z = NE (Not Equal)!=!= or unordered Z = 0 HS (Higher or Same) unsigned or unordered C = Note: Synonym for CS (Carry Set) LO (Lower) unsigned < < C = 0 Note: Synonym for CC (Carry Clear) HI (Higher) unsigned > > or unordered C = && Z = 0 LS (Lower or Same) unsigned C = 0 Z = GE (Greater Than or Equal) signed N = V LT (Less Than) signed < < or unordered N V GT (Greater Than) signed > > Z = 0 && N = V LE (Less Than or Equal) signed or unordered Z = N V CS (Carry Set) unsigned or unordered C = Note: Synonym for HS (Higher or Same) CC (Carry Clear) unsigned < < C = 0 Note: Synonym for LO (Lower) MI (Minus) negative < N = PL (Plus) non-negative or unordered N = 0 VS (Overflow Set) overflow unordered V = VC (Overflow Clear) no overflow not unordered V = 0 AL (Always) unconditional unconditional Always true Notes:. This is only a partial list of the most commonly-used ARM Cortex-M4 instructions.. Clock Cycle counts do not include delays due to stalls when an instruction must wait for the previous instruction to complete. 3. There are magnitude restrictions on immediate constants; see ARM documentation for more information. Revised: June 7, 08 Page 7 of 7