CME341 Dec. 9, 2013 Final Exam

Size: px

Start display at page:

Download "CME341 Dec. 9, 2013 Final Exam"

Miranda Griffith
5 years ago
Views:

1 1 CME341 Dec. 9, 2013 Final Exam Time: 3.0 hours, Text Books, Notes and Computer Files Only NO CELL PHONES or LAPTOPS All questions are independent. microprocessor. Each assumes you are starting with the original Parts within a question are dependent upon each other. The modications in one part build upon the modications made in previous parts. Before starting the exam download all the les in the folder les_for_2013_nal on the class website to a folder on your H drive. The path to this folder is Exam Files -> CME341_Exam_Files -> exams_2013_2014.

2 2 (1) 1. This question asks you to modify the final_exam_student_scrambler in the folder les_for_2013_n This student scrambler is dierent than the one given as part of the preamble!!!!!!!! The modied final_exam_student_scrambler will be used for all questions in the exam. For this question you are to use the Quartus and modelsim projects set up in the preamble. (a) Modify student_scrambler as per the instructions on the back of the answer sheet. (b) For this question, the program memory is to be initialized with the same.hex le used in the preamble, i.e. final_program_preamble.hex. (c) Compile the Quatus project final_exam_quartus to generate a new final_exam_quartus.vo le. (d) Open the Modelsim-Altera project final_exam_testbench, open final_exam_testbench.v and make sure the seed is set to 8'HFF and exam_number is set to 8'H00. Compile, load the simulation, format the wave window with the preamble_wave.do le provided and then run the simulation. If you have done things correctly for exam number 8'H00, the value for accumulator_output at the time counter_full_bar is low will be that given on the answer sheet. (e) Change exam_number in final_exam_testbench.v to the number on your answer sheet. Recompile the Modelsim-Altera project, re-load the simulation, re-format the wave window and re-run the simulation. If you have done things correctly for your exam number, the value for accumulator_output at the time counter_full_bar is low will be that given on the answer sheet. (f) Change the seed to 8'HAA and exam_number to 8'H00. Recompile, etcetera and report accumulator_output on the answer sheet. (g) Change exam_number to the number on your exam and repeat. 2. NB: Use hex le final_program_2013_q2.hex to initialize your program memory for all parts of this question. (1) (a) Modify your microprocessor to make NOPC8, i.e. the instruction with machine code C8, clear the r register. Compile etcetera and report your answer on the answer sheet. Make sure you use the seed given on the answer sheet. (1) (b) Further modify your microprocessor to make the r register an accumulator. That is the r register is to get the sum of the ALU output and itself on every ALU instruction. The NOPC8 instruction must still clear the r register. Compile etcetera and report your answer on the answer sheet.

3 3 (1) 3. Modify your microprocessor to change the way the conditional jump operates (but do not change the unconditional jump). The same rules apply for when to jump and when not to jump, i.e. if the zero_flag is zero then jump. The dierence is the jump address is computed relative to the address of the jnz instruction. The modied instruction jumps back from the current instruction by the amount in the least signicant nibble of the instruction register. Such jumps are called relative jumps. For example, if the jnz instruction in the instruction register has machine code 8'HF3 and it is located in program memory at address 8'H29, then the jump would be to program memory address (8'H29 - {4'H0,4'H3}) which is 8'H26. If the jnz in the instruction register was machine code 8'HF0, then the jump would be to program memory address (8'H29 - {4'H0,4'H0}) which is 8'H29. NB: Use hex le final_program_2013_q3.hex to initialize your program memory. (1) 4. Modify the microprocessor to make a load y1 a relative conditional jump. That is make the load y1 for this question behave exactly as the jnz in the question 3. The amount of the relative jump is the value in the data eld of the load y1 instruction. The load y1 instruction should also load the y1 register. The jump and jnz instructions should functions as usual. NB: Use hex le final_program_2013_q4.hex to initialize your program memory. 5. NB: Use hex le final_program_2013_q5.hex to initialize your program memory for all parts of this question. (1) (a) Modify the microprocessor to make o_reg a timer. o_reg is to be decremented by 4'H1 on every clock edge subsequent to the clock edge that writes it. o_reg is written when it is the destination of a move or load instruction. It is decremented until it reaches 4'H0, then it is no longer decremented. That is to say, when o_reg == 4'H0 it is not to be decremented. Compile etcetera and report your answer on the answer sheet. (1) (b) Modify the microprocessor to make it jump to 8'HF8 on the positive clock after the clock edge that has o_reg changing to 4'H0 from a previous value of 4'H1. If the previous value was anything except 4'H1 then the jump to 8'HF8 is not done. That is to say pm_address is made equal to 8'HF8 as soon as o_reg becomes 4'H0 immediately after it was 4'H1. This will force a jump to 8'HF8 on the next clock edge. The instruction that is in the instruction register at the time pm_address is 8'F8 is to be executed if and only if that instruction is not a successful jump.

4 4 For example, if o_reg was loaded with 4'H8 and then counted down to say 4'H3 at which time a load o_reg, #4'H0 was encountered, then the transition would be 4'H3 to 4'H0 and no action would be taken. Compile etcetera and report your answer on the answer sheet. (1) (c) Modify your microprocessor so that the jump to 8'HF8 becomes a interrupt with interrupt vector 8'HF8 and NOPC8 becomes a return from interruption. Note 1: The program for this question has no load o_reg or move to o_reg instructions is the ISR so the ISR will not be interrupted. Note 2: There are no disable and enable interrupt instructions. Compile etcetera and report your answer on the answer sheet. (1) 6. Modify your microprocessor to change the jump instruction to a Jump to SubRoutine (JSR) instruction. Use NOPC8 as the Return From Subroutine (RFS) instruction. Allow for 7 levels of nesting (i.e. 7 JSR instructions can be encountered before a RFS is encountered). You may design this feature under the assumption that an RFS instruction does not immediately follow either a JSR or a RFS instruction. NB: Use hex le final_program_2013_q6.hex to initialize your program memory for this question. (1) 7. Modify your microprocessor to extend the size of program memory to 512 words. Of course the memory will have 9 address bits. The most signicant of the 9 bits is controlled by a 1-bit base register. The base register is to be synchronously cleared with the synchronous reset signal constructed in the program sequencer. It is to be set with NOPC8 and cleared with NOPD8. That is to say the clock edge that executes NOPC8 sets the base register and the clock edge that executes NOPD8 clears the base register. For all instructions except the special case listed below the most signicant address bit of the program memory is connected to the the base register. The special case mentioned above is when the instruction to be executed is located at 9'H0FF or 9'H1FF (i.e. the PC is 8'HFF) and that instruction is not a successful jump (The instruction could be a conditional jump instruction with the zero ag being set which mean there is no jump). In that case: (a) The most signicant address bit of program memory is to be the complement of the base register. (b) The base register is to be toggled on the same clock edge that executes the special case instruction instruction.

5 NOTE: There will not be a NOPC8 or NOPD8 instruction in memory locations 9'H0FF or 9'H1FF so do not worry about these cases. NB: Use hex le final_program_2013_q7.hex to initialize your program memory for this question. (1) 8. Modify your microprocessor to implement a zero-overhead loop. The x1 and y1 registers will become loop_count and loop_length respectively. The assembler program used to test this program will not use x1 in any ALU operations so you are free to decrement it in any way you see t while implementing the zero-overhead loop. The loop begins on the instruction after loop_count is written, which is a load or move instruction where x1 is the destination register. The number of times the loop will be executed is the number in loop_count upon entering the loop plus one. That is to say the value in loop_count upon entering the loop is the number of times the execution of the loop will be repeated. The length of the loop is one more than the value in the loop_length register. For example, if loop_length had a value of zero upon entering the loop then there would be one instruction in the loop and the last instruction would have the same address as the rst instruction. NOTE: Neither loop_count or loop_length will change (i.e. will be written) in the execution of the loop. HELPFUL HINT: The comments in the comment eld in the listing (i.e. the le final_program_2013_q8.lst) make it very clear how the circuit should operate. advised to look at final_program_2013_q8.lst before making the modications. 5 You are NB: Use hex le final_program_2013_q8.hex to initialize your program memory for this question. (1) 9. Modify your microprocessor to force a one clock-cycle wait, which could be viewed as a nooperation, prior to every data memory read. That is to say, a data memory read instruction should stay in the instruction register for two clock periods and get executed on the second clock edge. The clock edge that would normally execute the read would do nothing. This means neither the PC or pm_address will change on the rst clock edge. The subsequent clock edge will execute the instruction. NB: Use hex le final_program_2013_q9.hex to initialize your program memory for this question.

6 6 Listing for question 2a and 2b A load x0, #4'HA; 0002 C7 com x0; 0003 A4 mov o_reg, r; 0004 C8 NOPC8; clear r 0005 C7 com x0; 0006 C7 com x0; 0007 C7 com x0; 0008 A4 mov o_reg, r; 0009 C8 NOPC8; clear r 000A E0 jump Start; Listing for question load x0, #4'H3; F load y0, #4'Hf; 0003 A0 Loop: mov o_reg, x0; 0004 C2 add x0, y0; mov x0, r; 0006 F3 jnz 8'H30; jnz Loop 0007 E1 jump Next; 0010 align; Next: load x0, #4'H5; 0011 C2 add x0, y0; 0012 FF jnz 8'HF0; jnz Loop Next 10H Loop 03H

7 7 Listing for question load x0, #4'H0; load y0, #4'H1; 0003 C2 Loop1: add x0,y0; 0004 A4 mov o_reg, r; mov x0, r; load y1,#4'h3; jnz Loop E1 jump Loop2; 0010 align 0010 C2 Loop2: add x0,y0; 0011 A4 mov o_reg, r; mov x0, r; 0013 F1 jnz Loop2; 0014 E2 jump Loop3; 0020 align 0020 E2 Loop3: jump Loop3; Loop3 20H Loop2 10H

8 8 Listing for question 5a, 5b and 5c load o_reg, #4'H8; load o_reg, #4'H4; o_reg = 4 upon execution load x0, #4'H1; o_reg = 3 upon execution load x1, #4'H2; o_reg = 2 upon execution load y0, #4'H1; o_reg = 1 upon execution 0006 C2 add x0, y0; o_reg = 0 upon execution load y1, #4'H4; load is excuted ; For parts b) and c) also ; jumps to F E1 jump Loop1; For part c) this is the place ; of the return from interrupt 0010 align Loop1: load o_reg,#4'h3; traps in this loop ; for parts a) and c) load o_reg,#4'h2; 0012 E1 jump Loop1; 00F8 org 8'HF8 00F8 82 ISR: mov x0, y0; 00F9 C8 NOPC8; RFI for part c) 00FA E0 jump Start; only executed for part b) ISR F8H Loop1 10H

9 9 Listing for question E2 jump ISR1; load o_reg, #4'H0; A load x0, #4'HA; 0004 C7 com x0; r=5, zero_flag = 1; 0005 F1 jnz Trap; 0010 align 0010 F1 Trap: jnz Trap; r=5, zero_flag = 1; 0020 align ISR1: load o_reg, #4'H1; 0021 E3 jump ISR2; load o_reg, #4'H1; 0023 C8 NOPC8; RFI 0030 align ISR2: load o_reg, #4'H2; 0031 E4 jump ISR3; load o_reg, #4'H2; 0033 C8 NOPC8; RFI 0040 align ISR3: load o_reg, #4'H3; 0041 E5 jump ISR4; load o_reg, #4'H3; 0043 C8 NOPC8; RFI 0050 align ISR4: load o_reg, #4'H4; 0051 E6 jump ISR5; load o_reg, #4'H4; 0053 C8 NOPC8; RFI 0060 align ISR5: load o_reg, #4'H5; 0061 C8 NOPC8; RFI ISR4 50H Trap 10H ISR3 40H ISR2 30H ISR1 20H ISR5 60H

10 10 Listing for question org 8'H C8 NOPC8; 0002 E0 jump Start; jump to 9'H100 00F0 org 8'HF0; 00F0 40 end: load o_reg, #4'H0; 00F1 41 load o_reg, #4'H1; 00F2 42 load o_reg, #4'H2; 00F3 43 load o_reg, #4'H3; 00F4 44 load o_reg, #4'H4; 00F5 45 load o_reg, #4'H5; 00F6 46 load o_reg, #4'H6; 00F7 47 load o_reg, #4'H7; 00F8 48 load o_reg, #4'H8; 00F9 49 load o_reg, #4'H9; 00FA 4A load o_reg, #4'HA; 00FB 4B load o_reg, #4'HB; 00FC 4C load o_reg, #4'HC; 00FD 4D load o_reg, #4'HD; 00FE 4D load o_reg, #4'HD; 00FF 4F load o_reg, #4'HF; A Page1: load o_reg, #4'HA; 0101 D8 NOPD8; 0102 EF jump 8'HF; jump to 9'H0F0 end 0F0H Start 000H Page1 100H

11 11 Listing for question org 8'H load y1, #4'H2; loop length is load x1, #4'H5; execute loop 5+1=6 times top: load o_reg, #4'H1; should appear 6 times load o_reg, #4'H2; should appear 6 times end: load o_reg, #4'H3; should appear 6 times F load o_reg, #4'HF; should appear once load o_reg, #4'H0; 0008 E1 jump Trap; 0010 align 0010 E1 Trap: jump Trap; Trap 10H end 05H top 03H Listing for question org 8'H load i, #4'H7; load m, #4'H1; load dm, #4'H1; load dm, #4'H2; load dm, #4'H3; load i, #4'H7; 0007 A7 mov o_reg, dm; 0008 A7 mov o_reg, dm; 0009 A7 mov o_reg, dm; 000A 40 load o_reg, #4'H0; 000B E1 jump Trap; 0010 align 0010 E1 Trap: jump Trap; Trap 10H

CME341 Dec. 16, 2014 Final Exam

1 CME341 Dec. 16, 2014 Final Exam Time: 3.0 hours, Text Books, Notes and Computer Files Only NO CELL PHONES or LAPTOPS All questions are independent. Each assumes you are starting with the microprocessor