instruction 1 Fri Oct 13 13:05:

Transcription

1 instruction Fri Oct :0:0. Introduction SECTION INSTRUCTION SET This section describes the aressing modes and instruction types.. Aressing Modes The CPU uses eight aressing modes for flexibility in accessing data. The aressing modes define the manner in which the CPU finds the data required to execute an instruction. The eight aressing modes are: Inherent Immediate Direct Extended Indexed, no oset Indexed, -bit oset Indexed, -bit oset Relative.. Inherent Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no operand aress and are one byte long... Immediate Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no operand aress and are two bytes long. The opcode is the first byte, and the immediate data value is the second byte. 0 0 MCHC0CA INSTRUCTION SET MOTOROLA -

2 instruction Fri Oct :0: Direct Direct instructions can access any of the first memory aresses with two bytes. The first byte is the opcode, and the second is the low byte of the operand aress. In direct aressing, the CPU automatically uses $00 as the high byte of the operand aress... Extended Extended instructions use three bytes and can access any aress in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand aress. When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction... Indexed, No Oset Indexed instructions with no oset are -byte instructions that can access data with variable aresses within the first memory locations. The index register contains the low byte of the eective aress of the operand. The CPU automatically uses $00 as the high byte, so these instructions can aress locations $0000 $00FF. Indexed, no oset instructions are often used to move a pointer through a table or to hold the aress of a frequently used RAM or I/O location... Indexed, -Bit Oset Indexed, -bit oset instructions are -byte instructions that can access data with variable aresses within the first memory locations. The CPU as the unsigned byte in the index register to the unsigned byte following the opcode. The sum is the eective aress of the operand. These instructions can access locations $0000 $0FE. Indexed -bit oset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the first memory locations and could extend as far as location 0 ($0FE). The k value is typically in the index register, and the aress of the beginning of the table is in the byte following the opcode. MOTOROLA INSTRUCTION SET MCHC0CA -

3 instruction Fri Oct :0:0.. Indexed, -Bit Oset Indexed, -bit oset instructions are -byte instructions that can access data with variable aresses at any location in memory. The CPU as the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the eective aress of the operand. The first byte after the opcode is the high byte of the -bit oset; the second byte is the low byte of the oset. Indexed, -bit oset instructions are useful for selecting the kth element in an n-element table anywhere in memory. As with direct and extended aressing, the Motorola assembler determines the shortest form of indexed aressing... Relative Relative aressing is only for branch instructions. If the branch condition is true, the CPU finds the eective branch destination by aing the signed byte following the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The oset is a signed, two s complement byte that gives a branching range of to + bytes from the aress of the next location after the branch instruction. When using the Motorola assembler, the programmer does not need to calculate the oset, because the assembler determines the proper oset and verifies that it is within the span of the branch.. Instruction Types The MCU instructions fall into the following five categories: Register/memory instructions Read-modify-write instructions Jump/branch instructions Bit manipulation instructions Control instructions 0 0 MCHC0CA INSTRUCTION SET MOTOROLA -

4 instruction Fri Oct :0: Register/Memory Instructions These instructions operate on CPU registers and memory locations. Most of them use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory... Read-Modify-Write Instructions Table -. Register/Memory Instructions Instruction A Memory Byte and Carry Bit to Accumulator A Memory Byte to Accumulator AND Memory Byte with Accumulator Bit Test Accumulator Compare Accumulator Compare Index Register with Memory Byte EXCLUSIVE OR Accumulator with Memory Byte Unconditional Jump Jump to Subroutine Load Accumulator with Memory Byte Load Index Register with Memory Byte Multiply OR Accumulator with Memory Byte Subtract Memory Byte and Carry Bit from Accumulator Store Accumulator in Memory Store Index Register in Memory Subtract Memory Byte from Accumulator Mnemonic These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. ADC ADD AND BIT CMP CPX EOR JMP JSR LDA LDX MUL ORA SBC STA STX SUB MOTOROLA INSTRUCTION SET MCHC0CA -

5 instruction Fri Oct :0:0 NOTE Do not use read-modify-write instructions on write-only registers... Jump/Branch Instructions Table -. Read-Modify-Write Instructions Instruction Arithmetic Shift Left (Same as LSL) Arithmetic Shift Right Mnemonic NOTES:. Unlike other read-modify-write instructions, BCLR and BSET use only direct aressing.. TST is an exception to the read-modify-write sequence because it does not write a replacement value. Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump to subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed. The BRCLR and BRSET instructions cause a branch based on the state of any readable bit in the first memory locations. These -byte instructions use a combination of direct aressing and relative aressing. The direct aress of the ASL ASR Clear Bit BCLR () Set Bit BSET () Clear Register Complement (One s Complement) Decrement Increment Logical Shift Left (Same as ASL) Logical Shift Right Negate (Two s Complement) Rotate Left through Carry Bit Rotate Right through Carry Bit CLR COM DEC INC LSL LSR NEG ROL ROR Test for Negative or Zero TST () 0 0 MCHC0CA INSTRUCTION SET MOTOROLA -

6 instruction Fri Oct :0:0 0 0 byte to be tested is in the byte following the opcode. The third byte is the signed oset byte. The CPU finds the eective branch destination by aing the third byte to the program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from to + from the aress of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register. Table -. Jump and Branch Instructions Instruction Branch if Carry Bit Clear Branch if Carry Bit Set Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same Branch if IRQ Pin High Branch if IRQ Pin Low Branch if Lower Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always Branch if Bit Clear Branch Never Branch if Bit Set Branch to Subroutine Unconditional Jump Jump to Subroutine Mnemonic BCC BCS BEQ BHCC BHCS BHI BHS BIH BIL BLO BLS BMC BMI BMS BNE BPL BRA BRCLR BRN BRSET BSR JMP JSR MOTOROLA INSTRUCTION SET MCHC0CA -

7 instruction Fri Oct :0:0.. Bit Manipulation Instructions The CPU can set or clear any writable bit in the first bytes of memory. Port registers, port data direction registers, timer registers, and on-chip RAM locations are in the first bytes of memory. The CPU can also test and branch based on the state of any bit in any of the first memory locations. Table -. Bit Manipulation Instructions Bit Clear Branch if Bit Clear Branch if Bit Set Bit Set Instruction NOTE Mnemonic BCLR BRCLR BRSET BSET Avoid using bit clear and bit set instructions in registers containing write-only bits, which may be changed inadvertently. 0.. Control Instructions These instructions act on CPU registers and control CPU operation during program execution. Table -. Control Instructions Clear Carry Bit Instruction Clear Interrupt Mask No Operation Reset Stack Pointer Return from Interrupt Return from Subroutine Set Carry Bit Set Interrupt Mask Stop Oscillator and Enable IRQ Pin Software Interrupt Transfer Accumulator to Index Register Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts Mnemonic CLC CLI NOP RSP RTI RTS SEC SEI STOP SWI TAX TXA WAIT 0 MCHC0CA INSTRUCTION SET MOTOROLA -

8 instruction Fri Oct :0: Instruction Set Summary Source Form ADC #opr ADC opr ADC opr ADC opr,x ADC opr,x ADC,X ADD #opr ADD opr ADD opr ADD opr,x ADD opr,x ADD,X AND #opr AND opr AND opr AND opr,x AND opr,x AND,X ASL opr ASLA ASLX ASL opr,x ASL,X ASR opr ASRA ASRX ASR opr,x ASR,X Table - is an alphabetical list of all MHC0 instructions and shows the eect of each instruction on the condition code register. Operation Table -. Instruction Set Summary Description Eect on CCR H I N Z C A with Carry A (A) + (M) + (C) A without Carry A (A) + (M) Logical AND A (A) (M) Arithmetic Shift Left (Same as LSL) C 0 Arithmetic Shift Right C b b0 BCC rel Branch if Carry Bit Clear PC (PC) + + rel? C = 0 REL rr BCLR n opr Clear Bit n Mn 0 Aress Mode (b0) (b) (b) (b) (b) (b) (b) (b) BCS rel Branch if Carry Bit Set (Same as BLO) PC (PC) + + rel? C = REL rr BEQ rel Branch if Equal PC (PC) + + rel? Z = REL rr BHCC rel Branch if Half-Carry Bit Clear PC (PC) + + rel? H = 0 REL rr BHCS rel Branch if Half-Carry Bit Set PC (PC) + + rel? H = REL rr b b0 Opcode A B C D E F AB BB CB DB EB FB A B C D E F B D F Operand ee ee ee Cycles MOTOROLA INSTRUCTION SET MCHC0CA -

9 instruction Fri Oct :0:0 Source Form BHI rel Branch if Higher PC (PC) + + rel? C Z = 0 REL rr BHS rel Branch if Higher or Same PC (PC) + + rel? C = 0 REL rr BIH rel Branch if IRQ Pin High PC (PC) + + rel? IRQ = REL F rr BIL rel Branch if IRQ Pin Low PC (PC) + + rel? IRQ = 0 REL E rr BIT #opr BIT opr BIT opr BIT opr,x BIT opr,x BIT,X Table -. Instruction Set Summary (Continued) Operation Description Eect on CCR H I N Z C Bit Test Accumulator with Memory Byte (A) (M) BLO rel Branch if Lower (Same as BCS) PC (PC) + + rel? C = REL rr BLS rel Branch if Lower or Same PC (PC) + + rel? C Z = REL rr BMC rel Branch if Interrupt Mask Clear PC (PC) + + rel? I = 0 REL C rr BMI rel Branch if Minus PC (PC) + + rel? N = REL B rr BMS rel Branch if Interrupt Mask Set PC (PC) + + rel? I = REL D rr BNE rel Branch if Not Equal PC (PC) + + rel? Z = 0 REL rr BPL rel Branch if Plus PC (PC) + + rel? N = 0 REL A rr BRA rel Branch Always PC (PC) + + rel? = REL 0 rr BRCLR n opr rel Branch if Bit n clear PC (PC) + + rel? Mn = 0 (b0) (b) (b) (b) (b) (b) (b) (b) BRN rel Branch Never PC (PC) + + rel? = 0 REL rr BRSET n opr rel Branch if Bit n Set PC (PC) + + rel? Mn = BSET n opr Set Bit n Mn Aress Mode (b0) (b) (b) (b) (b) (b) (b) (b) (b0) (b) (b) (b) (b) (b) (b) (b) Opcode A B C D E F B 0D 0F A 0C 0E 0 A C E Operand ee rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr Cycles 0 0 MCHC0CA INSTRUCTION SET MOTOROLA -

10 instruction 0 Fri Oct :0:0 0 0 Source Form BSR rel Branch to Subroutine PC (PC) + ; push (PCL) SP (SP) ; push (PCH) SP (SP) PC (PC) + rel REL AD rr CLC Clear Carry Bit C 0 0 CLI Clear Interrupt Mask I 0 0 A CLR opr CLRA CLRX CLR opr,x CLR,X CMP #opr CMP opr CMP opr CMP opr,x CMP opr,x CMP,X COM opr COMA COMX COM opr,x COM,X CPX #opr CPX opr CPX opr CPX opr,x CPX opr,x CPX,X DEC opr DECA DECX DEC opr,x DEC,X EOR #opr EOR opr EOR opr EOR opr,x EOR opr,x EOR,X INC opr INCA INCX INC opr,x INC,X JMP opr JMP opr JMP opr,x JMP opr,x JMP,X Clear Byte M $00 A $00 X $00 M $00 M $00 0 Compare Accumulator with Memory Byte (A) (M) Complement Byte (One s Complement) M (M) = $FF (M) A (A) = $FF (A) X (X) = $FF (X) M (M) = $FF (M) M (M) = $FF (M) Compare Index Register with Memory Byte (X) (M) Decrement Byte M (M) A (A) X (X) M (M) M (M) EXCLUSIVE OR Accumulator with Memory Byte A (A) (M) Increment Byte Table -. Instruction Set Summary (Continued) Operation Description M (M) + A (A) + X (X) + M (M) + M (M) + Eect on CCR H I N Z C Unconditional Jump PC Jump Aress Aress Mode Opcode F F F F F A B C D E F A B C D E F A A A A A A B C D E F C C C C C BC CC DC EC FC Operand ee ee ee ee Cycles MOTOROLA INSTRUCTION SET MCHC0CA -0

11 instruction Fri Oct :0:0 Source Form JSR opr JSR opr JSR opr,x JSR opr,x JSR,X LDA #opr LDA opr LDA opr LDA opr,x LDA opr,x LDA,X LDX #opr LDX opr LDX opr LDX opr,x LDX opr,x LDX,X LSL opr LSLA LSLX LSL opr,x LSL,X LSR opr LSRA LSRX LSR opr,x LSR,X Jump to Subroutine PC (PC) + n (n =,, or ) Push (PCL); SP (SP) Push (PCH); SP (SP) PC Eective Aress Load Accumulator with Memory Byte A (M) Load Index Register with Memory Byte X (M) Logical Shift Left (Same as ASL) C 0 b b0 Logical Shift Right 0 C 0 b b0 MUL Unsigned Multiply X : A (X) (A) 0 0 NEG opr NEGA NEGX NEG opr,x NEG,X Negate Byte (Two s Complement) M (M) = $00 (M) A (A) = $00 (A) X (X) = $00 (X) M (M) = $00 (M) M (M) = $00 (M) NOP No Operation D ORA #opr ORA opr ORA opr ORA opr,x ORA opr,x ORA,X ROL opr ROLA ROLX ROL opr,x ROL,X Table -. Instruction Set Summary (Continued) Operation Description Eect on CCR H I N Z C Logical OR Accumulator with Memory A (A) (M) Rotate Byte Left through Carry Bit C b b0 Aress Mode Opcode BD CD DD ED FD A B C D E F AE BE CE DE EE FE AA BA CA DA EA FA Operand ee ee ee ee Cycles 0 0 MCHC0CA INSTRUCTION SET MOTOROLA -

12 instruction Fri Oct :0:0 0 0 ROR opr RORA RORX ROR opr,x ROR,X Rotate Byte Right through Carry Bit C b b0 RSP Reset Stack Pointer SP $00FF C RTI RTS SBC #opr SBC opr SBC opr SBC opr,x SBC opr,x SBC,X Return from Interrupt Return from Subroutine Subtract Memory Byte and Carry Bit from Accumulator SP (SP) + ; Pull (CCR) SP (SP) + ; Pull (A) SP (SP) + ; Pull (X) SP (SP) + ; Pull (PCH) SP (SP) + ; Pull (PCL) SP (SP) + ; Pull (PCH) SP (SP) + ; Pull (PCL) A (A) (M) (C) 0 SEC Set Carry Bit C SEI Set Interrupt Mask I B STA opr STA opr STA opr,x STA opr,x STA,X Store Accumulator in Memory M (A) STOP Stop Oscillator and Enable IRQ Pin 0 E STX opr STX opr STX opr,x STX opr,x STX,X SUB #opr SUB opr SUB opr SUB opr,x SUB opr,x SUB,X SWI Source Form Store Index Register In Memory M (X) Subtract Memory Byte from Accumulator A (A) (M) Software Interrupt Table -. Instruction Set Summary (Continued) Operation Description Eect on CCR H I N Z C A B C D E F B C D E F BF CF DF EF FF A0 B0 C0 D0 E0 F0 ee ee ee ee PC (PC) + ; Push (PCL) SP (SP) ; Push (PCH) SP (SP) ; Push (X) SP (SP) ; Push (A) SP (SP) ; Push (CCR) SP (SP) ; I PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte 0 TAX Transfer Accumulator to Index Register X (A) Aress Mode Opcode Operand Cycles MOTOROLA INSTRUCTION SET MCHC0CA -

13 instruction Fri Oct :0:0 Source Form TST opr TSTA TSTX TST opr,x TST,X Table -. Instruction Set Summary (Continued) Operation Description Eect on CCR H I N Z C Test Memory Byte for Negative or Zero (M) $00 TXA Transfer Index Register to Accumulator A (X) F WAIT Stop CPU Clock and Enable Interrupts 0 F Aress Mode A Accumulator opr Operand (one or two bytes) C Carry/borrow flag PC Program counter CCR Condition code register PCH Program counter high byte Direct aress of operand PCL Program counter low byte rr Direct aress of operand and relative oset of branch instruction REL Relative aressing mode Direct aressing mode rel Relative program counter oset byte ee High and low bytes of oset in indexed, -bit oset aressing rr Relative program counter oset byte Extended aressing mode SP Stack pointer Oset byte in indexed, -bit oset aressing X Index register H Half-carry flag Z Zero flag High and low bytes of operand aress in extended aressing # Immediate value I Interrupt mask Logical AND Immediate operand byte Logical OR Immediate aressing mode Logical EXCLUSIVE OR Inherent aressing mode ( ) Contents of Indexed, no oset aressing mode ( ) Negation (two s complement) Indexed, -bit oset aressing mode Loaded with Indexed, -bit oset aressing mode? If M Memory location : Concatenated with N Negative flag Set or cleared n Any bit Not aected Opcode D D D D D Operand Cycles 0 0 MCHC0CA INSTRUCTION SET MOTOROLA -

14 instruction Fri Oct :0:0 0 0 Table -. Opcode Map Bit Manipulation Branch Read-Modify-Write Control Register/Memory REL MSB 0 A B C D E F MSB LSB LSB 0 SUB SUB SUB SUB SUB SUB RTI NEG NEG NEGX NEGA NEG BRA REL BSET0 BRSET0 0 CMP CMP CMP CMP CMP CMP RTS BRN REL BCLR0 BRCLR0 SBC SBC SBC SBC SBC SBC MUL BHI REL BSET BRSET 0 CPX CPX CPX CPX CPX CPX SWI COM COM COMX COMA COM BLS REL BCLR BRCLR AND AND AND AND AND AND LSR LSR LSRX LSRA LSR BCC REL BSET BRSET BIT BIT BIT BIT BIT BIT BCS/BLO REL BCLR BRCLR LDA LDA LDA LDA LDA LDA ROR ROR RORX RORA ROR BNE REL BSET BRSET STA STA STA STA STA TAX ASR ASR ASRX ASRA ASR BEQ REL BCLR BRCLR MOTOROLA INSTRUCTION SET MCHC0CA - ASLX/LSLX ASLA/LSLA EOR EOR EOR EOR EOR EOR CLC ASL/LSL ASL/LSL ASL/LSL BHCC REL BSET BRSET ADC ADC ADC ADC ADC ADC SEC ROL ROL ROLX ROLA ROL BHCS REL BCLR BRCLR A ORA ORA ORA ORA ORA ORA CLI DEC DEC DECX DECA DEC BPL REL BSET BRSET A B ADD ADD ADD ADD ADD ADD SEI BMI REL BCLR BRCLR B C JMP JMP JMP JMP JMP RSP INC INC INCX INCA INC BMC REL BSET BRSET C D JSR JSR JSR JSR JSR BSR REL NOP TST TST TSTX TSTA TST BMS REL BCLR BRCLR D E LDX LDX LDX LDX LDX LDX STOP BIL REL BSET BRSET E F STX STX STX STX STX TXA WAIT CLR CLR CLRX CLRA CLR BIH REL BCLR BRCLR F 0 MSB of Opcode in Hexadecimal MSB LSB Number of Cycles Opcode Mnemonic Number of Bytes/Aressing Mode BRSET0 LSB of Opcode in Hexadecimal 0 = Inherent REL = Relative = Immediate = Indexed, No Oset = Direct = Indexed, -Bit Oset = Extended = Indexed, -Bit Oset