CME341 Dec. 10, 2016 Final Exam

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1 1 CME341 Dec. 10, 2016 Final Exam Time: 3.0 hours, Text Books, Notes and Computer Files Only NO CELL PHONES or LAPTOPS All questions are independent. Each assumes you are starting with the microprocessor constructed in the preamble. If a question has more than 1 part, e.g. a) and b), then each part after the first part builds on the previous part. That is to say the modifications in each part builds upon the parts that precede it. The worth of the question are explained in the preamble. Before starting the exam download all the files in the folder files_for_2016_final on the class website to a folder on your H drive. The path to this folder is Exam Files -> CME341_Exam_Files -> exams_2016_2017. Remember that from_ps must be hardwired to zero in the program sequencer used in the final exam.

2 1. Make the no-operation instruction that is referred to as NOPC8, which in machine code is 8 HC8, a skip one instruction instruction. It is to jump to the instruction located two beyond the NOPC8 instruction being executed. I.e. it is to skip the instruction following the NOPC8 instruction. 2 NB: Do not change reg_enables[4]. It should still be high when 8 HC8 is in the instruction register. Answer for seed == 8 HAA is 16 HA71C Listing for question org 8 H C8 start: NOPC E0 jmp start; should not execute this instruction 0002 CF NOPCF 0003 D8 NOPD DF NOPDF F load x0,#4 HF; 0006 A8 mov m, x0; 0007 A5 mov o_reg,m; 0008 C7 com x0; 0009 F0 jnz start; 000A C8 NOPC8 000B C8 NOPC8; should not execute this instruction ; which is now a skip instruction 000C E0 jmp start;

3 2. Make the y 1 register an accumulator when it is the destination of a move. That is a move to y1 instruction becomes y 1 = src + y1, where src is the ID of the register being moved to y1. The load instruction should not be altered. 3 Answer for seed == 8 HAA is 16 H047E Listing for question org 16 H0000; start: load x1,#4 H5; load m, #4 H1; load y1,#4 H2; y1 = A load y1,#4 HA; y1 = A 0004 DA add x1,y1; mov y1,x1; y1 = 5+A=F C mov y1,r; y1 = F+F=E D mov y1,m; y1 = E+1=F 0008 E1 jmp done; 0010 E1 done: jmp done; done 10H

4 3. Make NOPD8 a circular shift of r 1-bit to the left through the zero flag and NOPDF a circular shift of r 1-bit to the right through the zero flag. A circular shift 1-bit to the left through the carry flag shifts the bits in the r register 1-bit to the left with the most significant bit of r being shifted into the carry flag and the carry flag being shifted into the least significant bit of r. A circular shift 1-bit to the right through the carry flag is similar with the shift being in opposite direction. That is the least significant bit of r is shifted into the carry flag and the carry flag is shifted into the most significant bit of r. Note: The zero flag should operate as normal on other ALU instructions. 4 Answer for seed == 8 HAA is 16 H75A9 Listing for Question start: load x1,#8 H3; load y1,#8 H0; 0002 DA add x1,y1; r=4 b0011, zero_flag = 1 b E1 jmp loop1; 0010 D8 loop1: NOPD8; shift left through zero flag 0011 F1 jnz loop1; 0012 E2 jmp loop2; at this point zero_flag 1, r = 1000; 0020 align 0020 DF loop2: NOPDF; shift right through zero flag 0021 F2 jnz loop2; 0022 E3 jmp loop3; at this point zero_flag 1, r = 0001; 0030 align 0030 E3 loop3: jmp loop3; loop2 20H loop1 10H loop3 30H

5 4. The i register is the index register used in the indirect addressing of the data memory, i.e. the i register is used as the address for data memory. Change your microprocessor so that the i register is still auto-incremented, but the address used for data memory should be i+m. 5 NB: Make from_cu = { o_reg, o_reg }. Answer for seed == 8 HAA is 16 HDCA0 Listing for question org 16 H start: load m,#4 H3; increment value will be load i,#4 H6; load dm,#4 H5; load dm word number 9 with 5 ; i = i + m = load m,#4 H0; change increment to load i,#4 H9; i = A7 mov o_reg,dm; o_reg = 5, i = load o_reg,#4 H0; 0007 E1 jmp done; 0010 E1 done: jmp done; done 10H

6 5. Modify your microprocessor to change the way the conditional jump operates (but do not change the unconditional jump). The same rules apply for when to jump and when not to jump, i.e. if the zero_flag is zero then jump. The jump address of new instruction does not the input jump_address. The jump address is derived from the address of the instruction. It must be a valid jump address that is closest to, but lower than, the address of the conditional jump instruction being executed. I.e. the jump must be at least 1 back and could be as much as 16 back. To better explain this two examples are given: Example 1: The jnz instruction is located at address 8 H29 in program memory. If the zero flag is zero when this jnz instruction is executed the jump would be to program memory address 8 H20. Example 2: The jnz instruction is located at address 8 H20 in program memory. If the zero flag is zero when this jnz instruction is executed the jump would be to program memory address 8 H10. Answer for seed == 8 HAA is 16 H1E7A 0000 org 16 H start: load x1,#4 H2; load y1, #4 H1; 0002 E1 jmp loop1; 0010 D9 loop1: sub x1,y1; C mov x1,r; 0012 FF jnz 8 HF0; ignore jump address and jump to loop load x1,#4 H3; 0014 E2 jmp loop2; 0020 align 0020 D9 loop2: sub x1,y1; decrement x C mov x1,r; 0022 C8 NOPC8; 0023 C8 NOPC8; 0024 C8 NOPC8; 0025 C8 NOPC8; 0026 C8 NOPC FF jnz 8 HF0; ignore jump address and jump to loop E3 jmp loop3; 0030 align 0030 E3 loop3: jmp loop3; loop2 20H loop1 10H loop3 30H 6

7 6. (a) Modify your computational unit to add a 4-bit timer called timer. The function of timer is described below: i. timer is to be synchronously cleared by sync_reset. ii. If timer contains 4 H0 it is to be re-loaded with the contents of y 1 on the next positive clock edge. iii. If timer 0, it is to be decremented on the next clock edge. Connect timer to the 4 least significant bits of from_cu as follows from_cu[7:0]={ 4 H0, timer }. Answer for seed == 8 HAA is 16 H94EE start: load y1,#4 H2; load y1,#4 H7; 0002 C8 NOPC8; 0003 C8 NOPC8; 0004 C8 NOPC8; 0005 C8 NOPC8; 0006 C8 NOPC8; 0007 C8 NOPC8; 0008 C8 NOPC8; 0009 C8 NOPC8; 000A C8 NOPC8; 000B C8 NOPC8; 000C C8 NOPC8; 000D C8 NOPC8; 000E C8 NOPC8; 000F E0 jmp start; 00F0 org 16 HF0; 00F0 11 ISR: load x1, #4 H1; 00F1 12 load x1, #4 H2; 00F2 13 load x1, #4 H3; 00F3 14 load x1, #4 H4; 00F4 15 load x1, #4 H5; 00F5 16 load x1, #4 H6; 00F6 17 load x1, #4 H7; 00F7 18 load x1, #4 H8; 00F8 19 load x1, #4 H9; 00F9 1A load x1, #4 HA; 00FA 1B load x1, #4 HB; 00FB DF NOPDF ISR F0H 7

8 (b) When timer has value 4 H1 it is to be interpreted as an interrupt and that interrupt has interrupt vector 8 HF0. NOPDF is to be used as the return from interrupt instruction. If a jump instruction is interrupted then the return from interrupt should be the destination of the jump. If a conditional jump is interrupted the return from interrupt should be to the next instruction if the zero flag is 1 and to the destination of the jump if the zero flag is 0. In a nutshell, the return address should be the pm_address calculated for the instruction in the ir at the time the interrupt is generated. The microprocessor hardware must be modified so that the interrupt service routine can not be interrupted. That is to say if timer == 4 H1 while any instruction in the interrupt service routine, which includes the return-from-interrupt instruction, is in the instruction register the interrupt is ignored. The hex file and the listing for this part are the same as those for 6a. Answer for seed == 8 HAA is 16 H664F 8

9 7. Modify your microprocessor to include a 8-word by 8-bit stack. NOPDF is to push PC onto the stack and NOPC8 is to pop the stack into an 8-bit register called pop_reg. The register pop_reg must be synchronously cleared by sync_reset. The registers that control the stack should also be initialized with sync_reset. 9 Connect pop_reg to from_ps so that the test bench can verify the operation. Answer for seed == 8 HAA is 16 H4C4E Listing for question F start: load x1,#4 HF; TOS should be 8 H DF NOPDF; push pc: TOS = 8 H1 after push 0002 DF NOPDF; push pc: TOS = 8 H2 after push 0003 DF NOPDF; push pc: TOS = 8 H3 after push 0004 DF NOPDF; push pc: TOS = 8 H4 after push load x1,#4 H0; 0006 C8 NOPC8; pop: pop_reg gets 8 H4 ; TOS = 8 H3 after pop 0007 C8 NOPC8; pop: pop_reg gets 8 H C8 NOPC8; pop: pop_reg gets 8 H C8 NOPC8; pop: pop_reg gets 8 H1 000A E1 jmp done; 0010 E1 done: jmp done; trap here done 10H

10 8. Modify your microprocessor to implement a zero overhead do while y 0 < y 1 loop. The roles of the variables and registers involved are modified/simplified to facilitate implementation in the exam environment. The following simplifications are made: (a) The loop length will be the constant 8 H4 (b) The test, which is made while the last instruction in the do-while loop is in the instruction register, is to see if the contents of register y 0 is less than the contents of register y 1. If y 0 < y 1 is true, the next instruction executed is the first instruction in the do-while loop. If y 0 y 1, then the next instruction executed is the instruction following the last instruction in the loop. (c) The first instruction in the loop is the instruction that follows NOPCF. Answer for seed == 8 HAA is 16 H74FC Listing for question F start: load x0, #4 HF; x0 = load y0, #4 H1; load y1, #4 H4; 0003 E1 jmp loop1; 0010 CF loop1: NOPCF; while loop starts at next instruction 0011 CA add x0, y1; first instr in the loop: r = y C mov y1,r; decrement y load x1, #4 H3; load x1, #4 H4; last instruction in the loop 0015 E2 jmp done; at this point y1= align 0020 E2 done: jmp done; done 20H loop1 10H 10

11 9. Modify your microprocessor to extend the size of program memory to 1024 words. Of course the memory will have 10 address bits, which means a bigger program counter will have to be used. Name this bigger program counter pc_big. All instructions, except the jump and conditional jump instructions work in exactly the same way. The target address of a jump instruction will be 10 bits with the most significant 4 bits being the argument of the jump instruction (i.e. the least significant 4 bits in the ir) and the least significant 6 bits being 6 H0. A conditional jump instruction, if successful, executes a jump to the address where the most significant 2-bits are 2 H0, the next 4-bits are the argument of the jump instruction and the least significant 4-bits are 4 H0. 11 The 10 bit pc_big is sent to the test bench in two segments: First, the least significant 8 bits of pc_big are connected to the 8-bit pc, which is a signal in the port list of the program sequencer, i.e. pc = pc_big[7 : 0]. Second the most significant 8 bits of pc_big are connected to from_ps, i.e. from_ps = pc_big[9 : 2]. The program memory file for this question is called big_program_memory_q9.hex. Remember that port list for the microprocessor has an 8-bit output that channels pm_address to the test bench. Connect the least significant 8 bits of the 10-bit program memory address to this channel. The answer for seed == 8 HAA: is 16 HBCD3 Listing for question C0 start: neg x0; r = 0; 0001 F1 jnz step1; don t jump 0002 C7 com x0; r = F 0003 F1 jnz step1; jump 0010 E3 step1: jmp 8 H30; jump to step 2 00C0 org 8 HC0 00C0 E8 step2: jmp 8 H80; Jump to 10 H200; 0200 E8 step3: jmp 8 H80; Jump to 10 H200; step3 200H step2 C0H step1 10H

12 10. Modify your microprocessor to implement a zero-overhead loop with a 4 bit loop count register called loop_count. The register loop_count must be built so that it is synchronously cleared with sync_reset and loaded by the load y 1 instruction. The load y 1 instruction also loads y 1 as it did before. The loop begins on the instruction after the load loop_count instruction, which shows up in the listing as a load y 1 instruction. The loop will be executed one more time than the value written to loop_count by the load loop_count instruction. That is to say the value in loop_count upon entering the loop is the number of times the execution of the loop will be repeated. 12 The length of the loop is fixed at 3 instructions. Make from_ps = { 4 H0, loop_count }. NOTE: loop_count is only written by a load y1, not by a move to y1. Also note from the listing that loop_count is not written by an instruction inside the loop. Answer for seed == 8 HAA is 16 H883D Listing for question start: load i,#4 H1; load x1,#4 H1; load y1,#4 H3; this is a load loop_count instruction 0003 DA add x1,y1; first instruction in the loop C mov y1,r; 0005 BC mov dm,r; last instruction in the loop 0006 E1 jmp done; 0010 E1 done: jmp done; done 10H

13 11. Modify your microprocessor to make NOPD8 a wait for two clock cycles. I.e. That is NOPD8 should be in the instruction register for 3 clock cycles and the instruction that follows NOPD8 is to be executed on the third clock edge after NOPD8 is executed for the first time. 13 The instruction register should hold NOPD8 while waiting and reg_enables[4] should be 1 b1 while NOPD8 is in the instruction register. The pc and should not change so that it is the address of NOPD8 while waiting. pm_address should point to the instruction that follows the NOPD8 that is in the instruction decoder. Note that a NOPD8 could follow a NOPD8 and both should cause a wait of two clock cycles. Answer for seed == 8 HAA is 16 HC start: load x1,#4 H1; 0001 D8 NOPD8; wait two clock cycles load x1,#4 H2; 0003 D8 NOPD8; wait two clock cycles 0004 D8 NOPD8; wait two more clock cycles load x1,#4 H3; 0006 E1 jmp done; 0010 E1 done: jmp done; done 10H

14 12. Modify your microprocessor to make the jump to 8 H00 instruction a two word instruction with the second word being the 8-bit jump address. 14 When the second word of the instruction is in the instruction register all the register enables must be 1 b0 regardless of that instruction. Answer for seed == 8 HAA is 16 H0E85 Listing for question start: load o_reg, #4 H0; 0001 E0 jmp 8 H00; first of two bytes 0002 C8 NOPC8; jump to 8 HC8 00C8 org 8 HC8 00C8 C8 loop1: NOPC8; 00C9 41 load o_reg, #4 H1; 00CA 40 load o_reg, #4 H0; 00CB ED jmp loop2; 00D0 align 00D0 E0 loop2: jmp 8 H00; first byte 00D1 C8 NOPC8; jump to loop1 loop2 D0H loop1 C8H

15 13. Modify your micro so that NOPC8 toggles a flip/flop called alternate_function. The flip/flop is to be cleared by sync_reset. Change the computational unit to use a different set of ALU functions when alternate_function is 1 b1. Seven of the eight alternate ALU instructions are to be no - operations with the functionality of NOPD8. The other alternate ALU instruction, which is the ALU instruction for ALU function field value 3 H1, is to perform an accumulation of a difference and is given by r = x y + r. The zero flag is still 1 b1 if and only if r == 0. Answer for seed == 8 HAA is 16 HE1E3 Listing for question org 16 H start: load x0,#4 H3; load y0,#4 H2; 0002 C1 sub x0,y0; r=x0-y0= C8 NOPC8; enter alternate ALU mode 0004 C2 add x0,y0; should be a no-op 0005 C1 sub x0,y0; accum diff; r = x0-y0+r= C1 sub x0,y0; accum diff; r = x0-y0+r= D0 neg x1; should be a no-op r = C mov x1,r; 0009 C8 NOPC8; end normal ALU mode 000A C1 sub x0,y0; r=x0-y0=1 000B C8 NOPC8; alternate mode 000C C8 NOPC8; back to normal 000D C0 neg x0; r=d 000E E1 jmp done; 0010 E1 done: jmp done; done 10H 15

CME341 Dec. 16, 2014 Final Exam

1 CME341 Dec. 16, 2014 Final Exam Time: 3.0 hours, Text Books, Notes and Computer Files Only NO CELL PHONES or LAPTOPS All questions are independent. Each assumes you are starting with the microprocessor