CME341 Dec. 16, 2014 Final Exam

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1 1 CME341 Dec. 16, 2014 Final Exam Time: 3.0 hours, Text Books, Notes and Computer Files Only NO CELL PHONES or LAPTOPS All questions are independent. Each assumes you are starting with the microprocessor constructed in the preamble. If a question has more than 1 part, e.g. a) and b), then each part after the rst part builds on the previous part. That is to say the modications in a part build upon the modications made in the previous parts. The worth of the question are explained in the preamble. Before starting the exam download all the les in the folder les_for_2014_nal on the class website to a folder on your H drive. The path to this folder is Exam Files -> CME341_Exam_Files -> exams_2014_2015.

2 1. Make the no-operation instruction that is referred to as NOPC8, which in machine code is 8'HC8, a jump to address 8'HC8 instruction. 2 Answer for seed == 8'HAA is 16'HA29A Listing for question org 8'H00; start: load o_reg, #4'H1; 0001 D8 NOPD8; no-operation 0002 C8 NOPC8; jump to 8'HC E0 JMP start; should never happen 00C8 org 8'hC8; 00C8 CF loop: NOPCF; no-operation 00C9 42 load o_reg, #4'H2 00CA C8 NOPC8; jump to loop loop C8H

3 3 2. Change the y 1 input to the y-select multiplexer to r. Answer for seed == 8'HAA is 16'H74CF Listing for question org 8'H00; start: load x0,#4'h2; load x1,#4'h3; load y0,#4'h4; D load y1,#4'hd; 0004 E1 jmp loop; 0010 align 0010 C2 loop: add x0,y0; r=x0+y0= CA add x0,y1; r=x0+r = D2 add x1,y0; r=x1+y0= DA add x1,y1; r=x1+r =A 0014 E1 jmp loop; loop 10H

4 4 3. (a) Make a ip/op called accumulator_mode in the instruction decoder and change from_id so that it is assigned { 7'b0, accumulator_mode } 1. This assignment will connect accumulator_mode to the test bench. This ip/op accumulator_mode is to be synchronously cleared with sync_reset, set by the no-operation instruction NOPCF (machine code 8'HCF) and cleared by the nooperation instruction NOPC8 (machine code 8'HC8). Answer for seed == 8'HAA is 16'H015B (b) Further modify your microprocessor to make r an accumulator while accumulator_mode is 1'b1. That is, if accumulator_mode is 1'b1, r gets the sum of the ALU output and itself on all ALU instructions except for no-operations, in which case r gets r. Of course while accumulator_mode is 1'b0 r gets the ALU output. Answer for seed == 8'HAA is 16'H72F9 Listing for question org 8'H00; question start: load x0,#4'h1; load x1,#4'h2; load y0,#4'h3; load y1,#4'h4; 0004 E1 jmp loop; 0010 align 0010 C2 loop: add x0,y0; r=1+3= D2 add x1, y0; r=2+3= CF NOPCF; set accumulator mode 0013 C2 add x0,y0; a) r=1+3=4 ; b)r=r+x0+y0= DA add x1, y1; a) r = 2+4=6 ; b) r=r+x1+y1=f 0015 DF NOPDF; no-operation, r does not change 0016 C8 NOPC8; clear accumulator mode 0017 E1 jmp loop; ; loop 10H 1 NOTE: The most signicant 7 bits of from_id are set to zero. This will cause the compiler to issue a 7 bits stuck at ground warning

5 4. The i register is the index register used in the indirect addressing of the data memory, i.e. the i register is used as the address for data memory. The microprocessor has been designed so that the i register is post incremented by the value in the m register on all move and load instructions where dm is either the source or the destination. Change your microprocessor to eectively pre-increment the i register by the value in the m register on all move and load instructions where dm is either the source or the destination. The implementation of this so called pre-increment still post-increments i. However, the address used for data memory is i+m, which gives the appearance that i was pre-incremented. 5 Answer for seed == 8'HAA is 16'H32EC Listing for question org 8'H00; start: load m, #4'H3; load i, #4'H7; load dm, #4'H5; store 4'H5 in address dm[a] ; increment i by 3 so i = A load m, #4'H0; A load i, #4'HA; make sure i = A 0005 A7 mov o_reg, dm; move dm[a], which is 4'H5, to o_reg ; increment i by 0 so i = A 0006 E0 jmp start;

6 5. Modify your microprocessor to change the way the conditional jump operates (but do not change the unconditional jump). The same rules apply for when to jump and when not to jump, i.e. if the zero_flag is zero then jump. The dierence is the jump address is computed relative to the address of the jnz instruction. The modied instruction jumps back from the current instruction by the amount in the least signicant nibble of the instruction register. Such jumps are called relative jumps. For example, suppose a jnz instruction with machine code 8'HF3 is located at address 8'H29 in program memory. Then if the zero ag is zero when this jnz instruction is executed the jump would be to program memory address (8'H29 - {4'H0,4'H3}), which is 8'H26. To clarify this even more, if the jnz was machine code 8'HF0, then the jump would be to program memory address (8'H29 - {4'H0,4'H0}), which is 8'H29. 6 Answer for seed == 8'HAA is 16'HD2F3 Listing for question org 8'H00; start: load o_reg, #4'H0; load x0,#4'h3; F load y0, # 4'HF; 0003 A0 loop: move o_reg, x0; 0004 C2 add x0,y0; mov x0, r; 0006 F3 jnz 8'H30; jnz loop 0007 E1 jmp next; 0010 align next: load x0, #4'H5; 0011 C2 add x0, y0; 0012 FF jnz 8'HF0; jnz loop loop 03H next 10H

7 7 6. Modify your microprocessor so that the jump to 8'HF0 becomes an interrupt with interrupt vector 8'HFC and NOPC8 becomes a return from interruption. Answer for seed == 8'HAA is 16'HB759 Listing for question org 8'H00; start: load x0,#4'h3; F load y0,#4'hf; 0002 E1 jmp main; 0010 align 0010 EF main: jmp 8'HF0; generate an interupt 0011 F1 jnz main; 0012 E2 jmp trap; 0020 align 0020 E2 trap: jmp trap; 00FC org 8'HFC; 00FC C2 ISR: add x0,y0; 00FD 84 mov x0,r; decrement x0 00FE C8 NOPC8; return to main program ISR FCH main 10H trap 20H

8 7. Modify your microprocessor to change the jump instruction to a Jump to SubRoutine (JSR) instruction. Use NOPDF (machine code 8'HDF) as the Return From Subroutine (RFS) instruction. Allow for 7 levels of nesting (i.e. 7 JSR instructions can be encountered before a RFS is encountered). 8 The jnz instruction should not be aected. Answer for seed == 8'HAA is 16'HAB12 Listing for question org 8'H00; 0000 E2 start: jmp SR1; jump to subroutine SR load o_reg, #4'H0; load x0, #4'H8; 0003 C7 com x0; r = 7, zero flag = F1 jnz trap; r!=0 so jump to trap 0010 align; 0010 F1 trap: jnz trap; r!= 0, jump to trap 0020 align SR1: load o_reg,#4'h1; 0021 E3 jmp SR2; 0022 DF NOPDF; return from subroutine 0030 align SR2: load o_reg,#4'h2; 0031 E4 jmp SR3; 0032 DF NOPDF; return from subroutine 0040 align SR3: load o_reg,#4'h3; 0041 E5 jmp SR4; 0042 DF NOPDF; return from subroutine 0050 align SR4: load o_reg,#4'h4; 0051 E6 jmp SR5; load o_reg,#4'h6; 0053 E7 jmp SR6; 0054 DF NOPDF; return from subroutine 0060 align SR5: load o_reg,#4'h DF NOPDF; return from subroutine 0070 align SR6: load o_reg,#4'h DF NOPDF; return from subroutine Symbol table is on the next page

9 SR3 40H SR2 30H SR1 20H trap 10H SR6 70H SR5 60H SR4 50H 9

10 8. Modify your microprocessor to change the move i_pins to dm instruction to a move dm to dm instruction. The destination address for data memory should be i and the source address should be y 1. In equation form this instruction would be written dm[i] = dm[y 1 ]. The modication will involve changing data memory to be a two port memory, with one of the ports being read only. 10 Answer for seed == 8'HAA is 16'HC840 Listing for question org 8'H00; start: load m, #4'H0; turn off auto increment load i,#4'h7; A load dm,#4'ha; dm[7] = A load y1,#4'h7; load i,#4'h3; 0005 BF mov dm,ipins; dm[i]=dm[y1] i.e. dm[3]=dm[7]=a 0006 A7 mov o_reg, dm; o_reg = dm[i] i.e. o_reg = A load o_reg, #4'H0; 0008 E0 jmp start;

11 11 9. Modify your microprocessor to extend the size of program memory to 512 words. Of course the memory will have 9 address bits. The most signicant of the 9 bits is to be controlled by a 1-bit base register named base_register. The size of pc and pm_address will remain 8 bits. The 9-bit memory address will be extended_pm_address = { MSB, pm_address }, where MSB is a 1 bit signal dependent on the base register. The jump and conditional jump instructions are to aect pm_address as usual. Note that pm_address is now the least signicant 8 bits of the 9-bit address now called extended_pm_address. The base register is to be synchronously cleared with sync_reset, set by instruction NOPC8 and cleared by instruction NOPD8. That is to say the clock edge that executes NOPC8 sets the base register and the clock edge that executes NOPD8 clears the base register. The base register is to be automatically incremented (which for a 1-bit register means toggled) when the instruction in ir is located at address 9'H0FF or 9'H1FF unless that instruction is a jump or a successful conditional jump, in which case the base register is not incremented. The logic that generates MSB depends on the memory location of the instruction being executed. If the instruction is located at any address except addresses 9'H0FF and 9'H1FF, then MSB = base_register. If the instruction is located at address 9'H0FF or 9'H1FF, then there are two cases to consider: Case 1: The instruction is a jump or successful conditional jump. In this case MSB = base_register. Case 2: The instruction is not a jump and is not a successful conditional jump. In this case MSB = the D input to base_register. Change from_ps to be from_ps = { 3'b0, MSB, 3'b0, MSB }. The reason for doing this is to facilitate debugging, however, it is not an option. The change must be made as it aects accumulator_output. NOTE: There will not be a NOPC8 or NOPD8 instruction in memory locations 9'H0FF or 9'H1FF so do not worry about these cases. Two possible answer for seed == 8'HAA: one is 16'H8D54 the other is 16'H364E The listing is on the next page.

12 12 Listing for question org 8'H Start: load o_reg, #4'H0; 0001 C8 NOPC8; 0002 E0 jump Start; jump to 9'H100 00F0 org 8'HF0; 00F0 40 end: load o_reg, #4'H0; 00F1 41 load o_reg, #4'H1; 00F2 42 load o_reg, #4'H2; 00F3 43 load o_reg, #4'H3; 00F4 44 load o_reg, #4'H4; 00F5 45 load o_reg, #4'H5; 00F6 46 load o_reg, #4'H6; 00F7 47 load o_reg, #4'H7; 00F8 48 load o_reg, #4'H8; 00F9 49 load o_reg, #4'H9; 00FA 4A load o_reg, #4'HA; 00FB 4B load o_reg, #4'HB; 00FC 4C load o_reg, #4'HC; 00FD 4D load o_reg, #4'HD; 00FE 4D load o_reg, #4'HD; 00FF 4F load o_reg, #4'HF; A Page1: load o_reg, #4'HA; 0101 D8 NOPD8; 0102 EF jump 8'HF; jump to 9'H0F0 end 0F0H Start 000H Page1 100H

13 Modify your microprocessor to implement a zero-overhead loop with a 4 bit loop count register called loop_count. The register loop_count must built so that it is synchronously cleared with sync_reset and loaded by the jnz instruction. To be more specic, change the conditional jump instruction (i.e. the jnz instruction) to a load loop_count instruction. The value in the 4-bit jump address eld will be the value loaded into the 4 bit register loop_count. For example a jnz 8'H50 instruction will load loop_count with a value of 4'H5, regardless of the status of the zero ag. The loop begins on the instruction after loop_count is written, which the instruction after a jnz instruction. The number of times the loop will be executed is 1 plus the value written to loop_count just prior to entering the loop. That is to say the value in loop_count upon entering the loop is the number of times the execution of the loop will be repeated The length of the loop is xed at 4 instructions. Make from_ps = { 4'H0, loop_count }. The reason for doing this is to facilitate debugging, however, it is not an option. The change must be made as it aects accumulator_output. NOTE: loop_count will not be written by an instruction inside the loop. Answer for seed == 8'HAA is 16'H43CC Listing for question org 8'H A Start: load o_reg, #4'HA; 0001 F3 jnz 8'H30; execute loop 3+1=4 times top: load o_reg, #4'H1; should appear 4 times load o_reg, #4'H2; should appear 4 times load o_reg, #4'H3; should appear 4 times end: load o_reg, #4'H4; should appear 4 times load o_reg, #4'H0; should appear once 0007 E1 jmp trap; 0010 align F trap: load o_reg, #4'HF; 0011 E1 jmp trap;

14 11. Question 11 has been removed at the last minute because of its degree of diculty. 14

15 12. Modify your microprocessor to make the jump to 8'H00 instruction a two word instruction with the second word being the 8-bit jump address. 15 Answer for seed == 8'HAA is 16'HF574 Listing for question org 8'H start: load o_reg,#4'h0; 0001 E0 jmp 8'H00; 0002 C8 NOPC8; jump to 8'HC8, which is loop1 00C8 org 8'HC8 00C8 C8 loop1: NOPC8; 00C9 41 load o_reg, #4'H1; 00CA 40 load o_reg, #4'H0; 00CB ED jmp loop2; 00D0 align 00D0 E0 loop2: jmp 8'H00; 00D1 C8 NOPC8; jump to loop1 loop2 D0H loop1 C8H

16 13. Modify the instruction decoder in your microprocessor to generate the enables for ir and auxiliary instruction registers ir 2, ir 3 and ir 4. Change from_id to be from_id = { 4'H0, ir_en }, where ir_en is the 4-bit vector ir_en[3:0] with ir_en[0] being the enable for ir, ir_en[1] being the enable for ir 2, ir_en[2] being the enable for ir 3 and ir_en[3] being the enable for ir 4. The enables are generated to support variable word length instructions with ir 2 holding the second word in the instruction, ir 3 holding the third word in the instruction and ir 4 holding the fourth word in the instruction. No-operation instructions NOPC8 (machine code 8'HC8), NOPCF (machine code 8'HCF) and NOPD8 (machine code 8'HD8) are to remain no-operation instructions but are to be treated as 2-word, 3-word and 4-word instructions, respectively. 16 Answer for seed == 8'HAA is 16'HBC27 Listing for question org 8'H00; start: load o_reg, #4'H8; 0001 C8 NOPC8; two word no-operation instruction load o_reg, #4'H2; second word - will have no effect load o_reg,#4'h9; o_reg will change from 8 to CF NOPCF; three word no-operation instruction load o_reg, #4'H3; second word - will have no effect load o_reg, #4'H3; third word - will have no effect A load o_reg, #4'HA; o_reg will change from 9 to A 0008 D8 NOPD8; four word no-operation instruction load o_reg, #4'H4; second word of - will have no effect 000A 44 load o_reg, #4'H4; third word - will have no effect 000B 44 load o_reg, #4'H4; fourth word - will have no effect 000C 4B load o_reg, #4'HB; o_reg will change from A to B- 000D E0 jmp start;

CME341 Dec. 9, 2013 Final Exam

1 CME341 Dec. 9, 2013 Final Exam Time: 3.0 hours, Text Books, Notes and Computer Files Only NO CELL PHONES or LAPTOPS All questions are independent. microprocessor. Each assumes you are starting with the