ECE 4510/5530 Microcontroller Applications Week 4 Lab 3-4

Transcription

1 Microcontroller Applications Week 4 Lab 3-4 Dr. Bradley J. Bazuin Associate Professor Department of Electrical and Computer Engineering College of Engineering and Applied Sciences

2 Lab 4 Elements Hardware Development Three terminal linear regulator Enhanced Capture Timer (ECT) (Chap. 8) Serial Communication Interface (SCI) (Chap. 9) Software Development Polling vs. Interrupts

3 THREE TERMINAL REGULATOR 3

4 MC7805CTG Linear Regulator 5V Positive Voltage Regulator Output Current in Excess of 1.0 A No External Components Required Internal Thermal Overload Protection Internal Short Circuit Current Limiting Output Transistor Safe Area Compensation Output Voltage Offered in 1.5%, 2% and 4% Tolerance Available in Surface Mount D2PAK 3, DPAK 3 and Standard 3 Lead Transistor Packages Data Sheet: MC7805CTG, ON Semiconductor 4

5 MC7805CTG Linear Regulator 78XX refers to the regulate output voltage Regulators require: Minimum input voltage: Vout+2.0V (7.0V) Defined as the drop-out voltage Nominal input voltage: 7.5 V to 25 V Must monitor device temperature for higher input voltages Thermal dissipation junction-to-ambient: 65 C -per-watt Maximum junction temperature: +150 C Nominal temperature rise for 7.5V input, 1 A out: (7.5-5) x 1 = 2.5 Watts 2.5 x 65 = C max. ambient = C (oops) 5

6 Typical Lab Consideration Thermal dissipation junction-to-ambient: 65 C -per-watt Maximum junction temperature: +150 C Lab temperature: 77 F or 25 C = 125 C temperature rise 125 / 65 = 1.9 Watts available before thermal problems Assume 0.5 ma operation 1.9 / 0.5 = 3.8 Volt drop in regulator Maximum input voltage: = 8.8 Volts Therefore, set the lab supply to between 7.5 and 8 volts Check to make sure the current used is not too high. 6

7 TIMER/COUNTER OUTPUT COMPARE 7

8 Chapter 8 Enhanced Capture Timer 16-bit main counter with 7-bit prescaler 8 programmable input capture or output compare channels Two 8-bit or one 16-bit pulse accumulators 8 PWM channels Programmable period and duty cycle 8-channel 8-bit or 4-channel 16-bit Separate control for each pulse width and duty cycle Center-aligned or left-aligned outputs Programmable clock select logic with a wide range of frequencies Fast emergency shutdown input Usable as interrupt inputs 8

9 Memory Addresses 9

10 Adapt9S12DP512 I/O Pins 10

11 Overview of Timer Functions Many applications require a dedicated timer system Time delay creation and measurement Period and pulse width measurement Frequency measurement Event counting Arrival time comparison Time of day tracking Periodic interrupt generation Waveform Generation The TIM (and ECT also) shares the eight Port T pins (IOC0 IOC7). 11

12 Overview of Timer Functions The applications mentioned will be very difficult to implement without a dedicated timer system HCS12 implements a very complicated timer system to support the implementation of these applications HCS12 microcontroller consists of a 16-bit timer counter The timer can be started or stopped according to the wishes of the programmer Three different timer functions can be implemented in HCS12 Input-capture Output compare Timer overflow 12

13 The HCS12 Timer System (1 of 2) The HCS12 has a standard timer module (TIM) that consists of: Eight channels of multiplexed input capture and output compare functions. 16-bit pulse accumulator A 16-bit timer counter The TIM block diagram is shown in Figure 8.1. The DP512 devices have implemented an Enhanced Capture Timer module (ECT). The ECT module contains: All the features contained in the TIM module One 16-bit buffer register for each of the input capture channels Four 8-bit pulse accumulator A 16-bit Modulus Down Counter with 4-bit prescaler Four user selectable delay counters for increasing input noise immunity The TIM (of course ECT also) shares the eight Port T pins (IOC0 IOC7). 13

14 The HCS12 Timer System (2 of 2) 14

15 Applications of Input Capture Function Event arrival time recording Period measurement: need to capture the main timer values corresponding to two consecutive rising or falling edges one period (a) Capture two rising edges one period (b) Capture two falling edges Figure 8.9 Period measurement by capturing two consecutive edges Pulse width measurement: need to capture the rising and falling edges Pulse width Rising edge Falling edge Figure 8.10 Pulse-width measurement using input capture

16 Input Capture Interrupt generation: Each input capture function can be used as an edge-sensitive interrupt source. Event counting: count the number of signal edges arrived during a period e 1 e 2 e 3 e 4 e i e j Start of interval End of interval Figure 8.11 Using an input-capture function for event counting Time reference: input-capture used in conjunction with an output compare function Time t 0 Time t 0 + delay Time of reference (set up by signal edge) Figure 8.12 A time reference application Time to activate output signal (set up by output compare)

17 Duty Cycle Measurement T T duty cycle = T T * 100% Figure 8.13 Definition of duty cycle 17

18 Phase Difference Measurement T signal S1 T signal S2 T phase difference = * 360 o T Figure 8.14 Phase difference definition for two signals 18

19 T Pin Related Registers Timer Counter Registers TIOS = $40 TCFORC = $41 TOC7M = $42 TOC7D = $43 TCNT = $44 (16-bit) TSCR1 = $46 TTOV = $47 TCTL1 = $48 TCTL2 = $49 TCTL3 = $4A TCTL4 = $4B TIE = $4C TSCR2 = $4D TFLG1 = $4E TFLG2 = $4F Timer Counter Registers TC0 = $50 (16-bit) TC1 = $52 (16-bit) TC2 = $54 (16-bit) TC3 = $56 (16-bit) TC4 = $58 (16-bit) TC5 = $5A (16-bit) TC6 = $5C (16-bit) TC7 = $5E (16-bit) and more through $7F 19

20 The HCS12 Timer Elements Bus clock Timer overflow interrupt Prescaler 16-bit counter Channel 0 Input Capture Output compare Channel 1 Input Capture Output compare Channel 2 IOC0 IOC1 16-bit free-running main timer Prescalaer TC0 interrupt TC1 interrupt TC2 interrupt TC3 interrupt TC4 interrupt Registers Input Capture Output compare Channel 3 Input Capture Output compare Channel 4 Input Capture Output compare IOC2 IOC3 IOC4 16-bit modulus downcounter Prescalaer Load Control Registers TC5 interrupt TC6 interrupt TC7 interrupt PA overflow interrupt PA input interrupt 16-bit Pulse accumulator A Channel 5 Input Capture Output compare Channel 6 Input Capture Output compare Channel 7 Input Capture Output compare IOC5 IOC6 IOC7 Interrupt Registers Capture/Compare Registers Figure 8.1 HCS12 Standard Timer (TIM) block diagram 20

21 Timer Block Diagram (Latch Mode) bus clock 1,2,..., bit load register 1, 4, 8, 16 Prescaler 16-bit free-running 16-bit modulus main timer bus clock Prescaler down counter PTx pin logic Delay counter EDG x comparator TCx capture/compare register one IC channel (IC0..IC3) TCxH hold register to other IC channels ICLAT, LATQ, BUFEN (force latch) Latch write $0000 to modulus counter LATQ (MDC latch enable) PTi pin logic EDG i MUX EDG j j = 8 - i comparator TCx capture/compare register one IC channel (IC4..IC7) Figure 8.35 Enhanced Input capture function block diagram in latch mode 21

22 Timer Block Diagram (Queue Mode) bus clock 1,2,..., bit load register 1, 4, 8, 16 Prescaler 16-bit free-running maintimer bus clock Prescaler 16-bit modulus down counter PTx pin logic Delay counter EDG x comparator TCxcapture/compare register one IC channel (IC0..IC3) TCxH hold register to other IC channels PTi pin logic EDG i MUX EDG j j = 8 - i comparator TCxcapture/compare register one IC channel (IC4..IC7) Figure 8.36 Enhanced Input capture function block diagram in Queue mode (channels IC0..IC3 block diagram) 22

23 Timer Counter Register (TCNT) Required for input capture and output compare functions. An up counter. Must be accessed in one 16- bit operation in order to obtain the correct value Three other registers related to the operation of the TCNT: TSCR1, TSCR2, TFLG2. The 16-bit main timer is an up counter. A full access for the counter register should take place in one clock cycle. A separate read (any mode)/write (test mode) for high byte and low byte will give a different result than accessing them as a word. Read anytime. Write has no meaning or effect in the normal mode; only writable in special modes (test_mode = 1). The period of the first count after a write to the TCNT registers may be a different size because the write is not synchronized with the prescaler clock. 23

24 Running the TCNT Counter Timer Counter Register 1 (TSCR1) Select the mode of operation for the module STOP: Timer and modulus counter are off since clocks are stopped. FREEZE: Timer and modulus counter keep on running, unless TSFRZ in TSCR($06) is set to one. WAIT: Counters keep on running, unless TSWAI in TSCR ($06) is set to one. NORMAL: Timer and modulus counter keep on running, unless TEN in TSCR($06) respectively MCEN in MCCTL ($26) are cleared. Timer Counter Register 2 (TSCR2) Timer prescale counting factor, timer overflow IE, and timer counter reset enable Timer Interrupt Flag 2 Register (TFLG2) Bit 7 (TOF) Set when 16-bit free-running timer overflows from $FFFF to $0000. This bit is cleared automatically by a write to the TFLG2 register with bit 7 set. (See also TCRE control bit explanation.) 24

25 Timer System Control Register 1 (TSCR1) Setting and clearing the bit 7 of TSCR1 will start and stop the counting of the TCNT. Setting the bit 4 will enable fast timer flag clear function. If this bit is clear, then the user must write a one to a timer flag in order to clear it value TEN TSWAI TSFRZ TFFCA after reset TEN -- timer enable bit 0 = disable timer; this can be used to save power consumption 1 = allows timer to function normally TSWAI -- timer stops while in wait mode bit 0 = allows timer to continue running during wait mode 1 = disables timer when MCU is in wait mode TSFRZ -- timer and modulus counter stop while in freeze mode 0 = allows timer and modulus counter to continue running while in freeze mode 1 = disables timer and modulus counter when MCU is in freeze mode TFFCA -- timer fast flag clear all bit 0 = allows timer flag clearing to function normally 1 = For TFLG1, a read from an input capture or a write to the output compare channel causes the corresponding channel flag, CnF, to be cleared. For TFLG2, any access to the TCNT register clears the TOF flag. Any access to the PACN3 and PACN2 registers clears the PAOVF and PAIF flags in the PAFLG register. Any access to the PACN1 and PACN0 registers clears the PBOVF flag in the PBFLG register. Figure 8.2 Timer system control register 1 (TSCR1) 25

26 Timer System Control Register 2 (TSCR2) Bit 7 is the TCNT overflow interrupt enable bit. The clock input (E-CLK) to TCNT (E-Clock) can be prescaled by a factor selecting by bits 2 to 0 of TSCR value TOI TCRE PR2 PR1 PR0 after reset TOI -- timer overflow interrupt enable bit 0 = interrupt inhibited 1 = interrupt requested when TOF flag is set TCRE -- timer counter reset enable bit 0 = counter reset inhibited and counter free runs 1 = counter reset by a successful output compare 7 If TC7 = $0000 and TCRE = 1, TCNT stays at $0000 continuously. If TC7 = $FFFF and TCRE = 1, TOF will never be set when TCNT rolls over from $FFFF to $0000. Figure 8.3 Timer system control register 2 (TSCR2) TCNT can be reset to 0 when TCNT equals TC7 by setting bit 3 of TSCR2. Table 8.1 Timer counter prescale factor PR2 PR1 PR0 Prescale Factor

27 Timer Interrupt Flag 2 Register Only bit 7 (TOF) is implemented. Bit 7 will be set whenever TCNT overflows. (TFLG2) TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write the bit to one. Read anytime. Write used in clearing mechanism (set bits cause corresponding bits to be cleared). Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set. TOF Timer Overflow Flag Set when 16-bit free-running timer overflows from $FFFF to $0000. This bit is cleared automatically by a write to the TFLG2 register with bit 7 set. (See also TCRE control bit explanation.) 27

28 Using TCNT Values Once the counter is set up, the timer functions can be used to: In - Input-Capture: The TCNT value is captured when the desired external event occurs Out - Output-Compare: The output occurs when TCNT equals the preset register value 28

29 Timer Port Pins Each port pin can be used as a general I/O pin when timer function is not selected. Pin 7 can be used as input capture 7, output compare 7 action, and a pulse accumulator input. The pulse accumulation function is unique to this pin. When a timer port pin is used as a general I/O pin, its direction is configured by the DDRT register. 29

30 OUTPUT COMPARE 30

31 Output Compare Function The HCS12 has eight output compare functions. Each output compare channel consists of A 16-bit comparator A 16-bit compare register TCx (also used as input capture register) An output action pin (PTx, can be pulled high, pulled low, or toggled) An interrupt request circuit A forced-compare function (CFOCx) Control logic 2510

32 Operation of the Output-Compare One of the applications of the output-compare function is to trigger an action at a specific time in the future. To use an output-compare function, the user Makes a copy of the current contents of the TCNT register Adds to this copy a value equal to the desired delay Stores the sum into an output-compare register (TCx, x = 0..7) A successful compare will set the corresponding flag bit in the TFLG1 register. An interrupt may be optionally requested if the associated interrupt enable bit in the TIE register is set.

33 Control of the Output-Compare The actions that can be activated on an output compare pin include Pull up to high Pull down to low Toggle The action is determined by the Timer Control Register 1 & 2 (TCTL1 & TCTL2): value OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 after reset value after reset (a) TCTL1 register OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL (b) TCTL2 register read: anytime write: anytime OMn OLn : output level no action (timer disconnected from output pin) toggle OCn pin clear OCn pin to 0 set OCn pin to high Figure 8.18 Timer control register 1 and 2 (TCTL1 & TCTL2)

34 Example 8.4 Output-Compare Example 8.4 Generate an active high 1 KHz digital waveform with 30 percent duty cycle from the PT0 pin. Use the polling method to check the success of the output compare operation. The frequency of the E clock is 24 MHz. Solution: An active high 1 KHz waveform with 30 percent duty cycle is shown in Figure The logic flow of this problem is illustrated in Figure Setting the prescaler to the TCNT to 8, then the period of the clock signal to the TCNT will be 1/3 ms. The numbers of clock cycles that the signal is high and low are 900 and 2100, respectively. 300 s 700 s Figure KHz 30 percent duty cycle waveform 34

35 Example 8.4 Flow Diagram Start Select pull high as pin action Clear C0F flag Start OC0 output compare with a delay of 700 s no C0F = 1? yes Select pull low as pin action Clear C0F flag Start OC0 output compare with a delay of 300 s no C0F = 1? yes Figure 8.20 The program logic flow for digital waveform generation 35

36 Example 8.4 Assembly Code #include "c:\miniide\hcs12.inc" hi_time = 900 lo_time = 2100.text _main:: movb #$90,TSCR1 ; enable TCNT with fast timer flag clear movb #$03,TSCR2 ; disable TCNT interrupt, set prescaler to 8 bset TIOS,OC0 ; enable OC0 movb #$03,TCTL2 ; select pull high as pin action ldd TCNT ; start an OC0 operation with 700 us as delay repeat: addd #lo_time ; " std TC0 ; " low: brclr TFLG1,C0F,low ; wait until OC0 pin go high movb #$02,TCTL2 ; select pull low as pin action ldd TC0 ; start an OC operation with 300 us as delay addd #hi_time ; " std TC0 ; " high: brclr TFLG1,C0F,high ; wait until OC0 pin go low movb #$03,TCTL2 ; select pull high as pin action ldd bra TC0 repeat

37 Example 8.4 C Code #include "c:\egnu091\include\hcs12.h" #define hi_time 900 #define lo_time 2100 void main (void) { TSCR1 = 0x90; /* enable TCNT and fast timer flag clear */ TIOS = OC0; /* enable OC0 function */ TSCR2 = 0x03; /* disable TCNT interrupt, set prescaler to 8 */ TCTL2 = 0x03; /* set OC0 action to be pull high */ TC0 = TCNT + lo_time; /* start an OC0 operation */ while(1) { while(!(tflg1 & C0F)); /* wait for PT0 to go high */ TCTL2 = 0x02; /* set OC0 pin action to pull low */ TC0 += hi_time; /* start a new OC0 operation */ while(!(tflg1 & C0F)); /* wait for PT0 pin to go low */ TCTL2 = 0x03; /* set OC0 pin action to pull high */ TC0 += lo_time; /* start a new OC0 operation */ } }

38 Example 8.5: 1 msec Time Delay Write a function to generate a time delay which is a multiple of 1 ms. Assume that the E clock frequency is 24 MHz. The number of milliseconds is passed in Y. Also write an instruction sequence to test this function. Solution: One method to create 1 ms delay is as follows: Set the prescaler to TCNT to 64 Perform the number of output-compare operations (given in Y) with each operation creating a 1-ms time delay. The number to be added to the copy of TCNT is 375. ( = 1 ms) 38

39 Example 8.5: Y x 1 msec Time Delay Subroutine delayby1ms: pshd movb #$90,TSCR1 ; enable TCNT & fast flags clear movb #$06,TSCR2 ; configure prescaler to 64 bset TIOS,OC0 ; enable OC0 ldd TCNT again0: addd #375 ; start an output-compare operation std TC0 ; with 1 ms time delay wait_lp0: brclr TFLG1,OC0,wait_lp0 ldd TC0 dbne y,again0 puld rts 39

40 Example 8.5: C Code void delayby1ms(int k) { int ix; TSCR1 = 0x90; /* enable TCNT and fast timer flag clear */ TSCR2 = 0x06; /* disable timer interrupt, set prescaler to 64 */ TIOS = OC0; /* enable OC0 */ TC0 = TCNT + 375; for (ix = 0; ix < k; ix++) { while(!(tflg1 & C0F)); TC0 += 375; } TIOS &= ~OC0; /* disable OC0 */ } See Textbook CD: Utilities/delay.c The above is from the old textbook CD 40

41 Textbook Delay Code Delay.asm delayby50us ; multiple passed in Y reg delayby1ms ; multiple passed in Y reg delayby10ms ; multiple passed in Y reg delayby100ms ; multiple passed in Y reg Delay.c void delayby10us(int k); void delayby50us(int k); /* time delay based on */ void delayby1ms(int k); /* 24 MHz E-clock. */ void delayby10ms(int k); void delayby100ms(int k);

42 Example 8.6: Estimate Frequency Use an input-capture and an output-compare functions to measure the frequency of the signal connected to the PT0 pin. Solution: To measure the frequency, we will Use one of the output-compare function to create a one-second time base. Keep track of the number of rising (or falling) edges that arrived at the PT0 pin within one second.

43 Example 8.6: Estimate Frequency (1 of 2) #include "c:\miniide\hcs12.inc" CR = $0D LF = $0A.org $1000 oc_cnt.blkb 1 frequency.blkb 2 msg:.byte CR,LF.ascii The frequency is %d.byte CR,LF,0.org $3E6E ; set up interrupt vector number.word TC0_isr ; for TC0.text _main:: movb #$90,TSCR1 ; enable TCNT and fast timer flags clear movb #$02,TSCR2 ; set prescale factor to 4 movb #$02,TIOS ; enable OC1 and IC0 movb #100,oc_cnt ; prepare to perform 100 OC1 operation, each ; creates 10 ms delay and total 1 second movw #0,frequency ; initialize frequency count to 0 movb #$01,TCTL4 ; prepare to capture the rising edges of PT0 movb #C0F,TFLG1 ; clear the C0F flag bset TIE,IC0 ; enable IC0 interrupt cli ; "

44 Example 8.6: Code (2 of 2) ldd TCNT ; start an OC1 operation with 10 ms delay continue: addd #60000 ; " std TC1 ; " w_lp: brclr TFLG1,C1F, w_lp; wait for 10 ms ldd TC1 dec oc_cnt bne continue sei ; set I, disabling all interrupts ldd frequency pshd ldd #msg ldx #00 jsr [printf, X] leas 2,sp swi TC0_isr: ldd TC0 ; clear C0F flag ldx frequency ; increment frequency count by 1 inx ; " stx frequency ; rti 44

45 Example 8.6: C Code (1 of 2) #include <hcs12.h> #include <vectors12.h> #include <convert.c> #include <stdio.c> #define INTERRUPT attribute ((interrupt)) unsigned int frequency; void INTERRUPT TC0_isr(void); void main(void) { char arr[7]; char *msg = "Signal frequency is "; int i, oc_cnt; unsigned frequency; UserTimerCh0 = (unsigned short)&tc0_isr; TSCR1 = 0x90; /* enable TCNT and fast flag clear */ TSCR2 = 0x02; /* set prescale factor to 4 */ TIOS = 0x02; /* select OC1 and IC0 */ oc_cnt = 100; /* prepare to perform 100 OC1 operations */ frequency = 0;

46 Example 8.6: C Code (2 of 2) TCTL4 = 0x01; /* prepare to capture PT0 rising edge */ TFLG1 = C0F; /* clear C0F flag */ TIE = IC0; /* enable IC0 interrupt */ asm("cli"); TC1 = TCNT ; while (oc_cnt) { while(!(tflg1 & C1F)); TC1 = TC ; oc_cnt = oc_cnt - 1; } asm( sei"); int2alpha(frequency, arr); puts(msg); puts(&arr[0]); asm("swi"); } void INTERRUPT TC0_isr(void) { TFLG1 = C0F; /* clear C0F flag */ frequency ++; }

47 Making Sound Using the Output-Compare Function A sound can be generated by creating a digital waveform with appropriate frequency and using it to drive a speaker or a buzzer. The simplest song is a two-tone siren. HCS12DP F PT5 Buzzer Figure 8.21 Circuit connection for a buzzer 47

48 Example 8.7: Algorithm for Generating a Siren Step 1 Enable an output compare channel to drive the buzzer (or speaker). Step 2 Start an output compare operation with a delay count equal to half the period of the siren and enable the OC interrupt. Step 3 Wait for the duration of the siren tone (say half a second). During the waiting period, interrupts will be requested many times by the output compare function. The interrupt service routine simply restart the output compare operation. Step 4 At the end of the siren tone duration, choose a different delay count for the output compare operation so that the siren sound may have a different frequency. Step 5 Wait for the same duration as in Step 3. During this period, many interrupts will be requested by the output compare operation. Step 6 Go to Step 2. 48

49 Example 8.7 Siren Generation Write a program to generate a two-tone siren that oscillates between 300 Hz and 1200 Hz. Solution: Set the prescaler to TCNT to 1:8. The delay count for the low frequency tone is ( ) = The delay count for the high frequency tone is ( ) =

50 Example 8.7 Siren Generation (1 of 2) #include "c:\miniide\hcs12.inc" hi_freq = 1250 ; delay count for 1200 Hz (with 1:8 prescaler) lo_freq = 5000 ; delay count for 300 Hz (with 1:8 prescaler) toggle = $04 ; value to toggle the TC5 pin.org $1000 delay:.blkw 1 ; store the delay for output-compare operation.text _main:: lds #$3C00 movw #oc5_isr,usertimerch5 ; initialize the interrupt vector entry movb #$90,TSCR1 ; enable TCNT, fast timer flag clear movb #$03,TSCR2 ; set main timer prescaler to 8 bset TIOS,OC5 ; enable OC5 movb #toggle,tctl1 ; select toggle for OC5 pin action movw #hi_freq,delay ; use high frequency delay count first ldd TCNT ; start the low frequency sound addd delay ; " std TC5 ; " bset TIE,OC5 ; enable OC5 interrupt cli 50

51 Code (2 of 2) forever: ldy #5 ; wait for half a second jsr delayby100ms ; " movw #lo_freq, delay ; switch to low frequency delay count ldy #5 jsr delayby100ms movw #hi_freq, delay ; switch to high frequency delay count bra forever oc5_isr: ldd TC5 ; half period of frequency addd delay std TC5 rti #include c:\miniide\delay.asm 51

52 C Program for Siren Generation (1 of 2) #include "c:\egnu091\include\hcs12.h" #include "c:\egnu091\include\delay.c" #define HiFreq 1250 #define LoFreq 5000 int delay; /* delay count for OC5 operation */ int main(void) { asm("cli"); TSCR1 = 0x90; /* enable TCNT and fast timer flag clear */ TSCR2 = 0x03; /* set prescaler to TCNT to 1:8 */ TIOS = BIT5; /* enable OC5 */ TCTL1 = 0x04; /* select toggle for OC5 pin action */ delay = HiFreq; /* use high frequency delay count first */ TC5 = TCNT + delay; /* start an OC5 operation */ TIE = BIT5; /* enable TC5 interrupt */ asm("cli"); 52

53 C Program for Siren Generation (2 of 2) } while(1) { delayby100ms(5); /* wait for half a second */ delay = LoFreq; /* switch to low frequency tone */ delayby100ms(5); /* wait for half a second */ delay = HiFreq; /* switch to high frequency tone */ } return 0; #pragma interrupt_handler oc5_isr void oc5_isr(void) { TC5 += delay; } #pragma abs_address:vtimch5 // Initialize the Interrupt Vector address void (*interrupt_vectors[]) (void) = {oc5_isr}; // Assign the function pointer #pragma end_abs_address // to the ISR 53

54 Preferred Initialization void init_timerch5(void) { TSCR1 = 0x90; /* enable TCNT and fast timer flag clear */ TSCR2 = 0x03; /* set prescaler to TCNT to 1:8 */ TIOS = BIT5; /* enable OC5 */ TCTL1 = 0x04; /* select toggle for OC5 pin action */ TIE = BIT5; /* enable TC5 interrupt */ } Then we have. int main(void) { asm( sei"); init_timerch5(); /* initialize channel 5*/ delay = HiFreq; /* use high frequency delay count first */ TC5 = TCNT + delay; /* start an OC5 operation */ asm("cli"); 54

55 More Timing Capabilities Play The Star-Spangled Banner More digital waveform generation Pulse accumulator operations N pulse event detector Alternate frequency measurement technique Gate time method for measuring a pulse duration Modulus down-counter to generate periodic interrupts See delay.asm from textbook CD 55

56 Sunseeker Timer Module (1 of 2) /* * Initialise Timer B * - Provides timer tick timebase at 100 Hz */ void timerb_init( void ) { TBCTL = TBSSEL_1 ID_3 TBCLR; TBCCR0 = (INPUT_CLOCK/8/TICK_RATE); TBCCTL0 = CCIE; // Enable CCR0 interrrupt TBCTL = MC_1; // Set timer to 'up' count mode } // ACLK/8, clear TBR // Set timer to count to this value = TICK_RATE overflow 56

57 Sunseeker Timer Module (2 of 2) /* * Timer B CCR0 Interrupt Service Routine * - Interrupts on Timer B CCR0 match at 100Hz * - Sets Time_Flag variable */ //interrupt(timerb0_vector) timer_b0(void) #pragma vector=timerb0_vector interrupt void timer_b0(void) { static unsigned char blink_count = BLINK_SPEED; static unsigned char comms_count = COMMS_SPEED; static unsigned char activity_count; static unsigned char input_count = INPUT_SPEED; // Trigger blink events (indicators) blink_count--; if( blink_count == 0 ){ blink_count = BLINK_SPEED; blink_flag = TRUE; } // Trigger comms events (command packet transmission) comms_count--; if( comms_count == 0 ){ comms_count = COMMS_SPEED; comms_flag = TRUE; } } // Check for CAN activity events if( activity_flag == TRUE ){ activity_flag = FALSE; activity_count = ACTIVITY_SPEED; P4OUT &= ~ngreen_b; } if( activity_count == 0 ){ P4OUT = ngreen_b; } else{ activity_count--; } // Trigger switch input reads (debounce period) input_count--; if( input_count == 0 ){ input_count = INPUT_SPEED; input_flag = TRUE; } Multiple independent periodic flags 57