ME 4447 / ME 6405: Introduction to Mechatronics

Transcription

1 ME 4447 / ME 6405: Introduction to Mechatronics Interrupts and Resets Rohan Bansal Edward Chyau Anirudh Rudraraju Interrupts and Resets 1

2 Telephone Analogy How do we know if someone is calling? Use polling Pick up the phone periodically and check if someone is there. Wait for an interrupt Wait until the phone rings, then answer it. Interrupts and Resets 2

3 Polling Loops and checks a register until a certain state is found Example Wait for a 1 in the CCF bit of the ADCTL (from Lab 2): LDX #$1030 WAIT BRCLR 0,X #$80 WAIT Interrupts and Resets 3

4 Interrupts A way to get the microcontrollers attention A signal is sent to the CPU when data arrives The CPU is free to execute other operations while waiting for data Interrupts and Resets 4

5 Applications of Interrupts Critical signals Switch power sources on power failure Turn on fans when overheating Notify the CPU when an error occurs Timers Create interrupts at specified real times Receive input Check when a button is pushed on a controller Interrupts and Resets 5

6 Drawbacks of Interrupts Interrupts can occur randomly Makes testing and debugging difficult Additional hardware may be required to produce a proper interrupt signal Interrupts and Resets 6

7 Interrupt Flow 1. Complete the current instruction 2. Save the current state to the stack 3. Identify the source of the interrupt 4. Activate Interrupt Service Routing (ISR) 5. Return to original program (RTI) and restore state Interrupts and Resets 7

8 Interrupt Flowchart SOFTWARE INTERRUPT HARDWARE INTERRUPT COPY REGISTER CONTENTS TO STACK N MASK SET? Y SET APPROPRIATE BIT IN CCR CONTINUE MAIN PROGRAM $FFC0 EXECUTE INTERRUPT SERVICE ROUTINE LOAD INTERRUPT VECTOR INTO PROGRAM COUNTER VECTOR TABLE $FFFF Interrupts and Resets 8

9 Saving Current State to Stack Make sure the stack is the same at the end of your interrupt code SP-9 SP-8 SP-7 SP-6 SP-5 SP-4 SP-3 SP-2 SP-1 SP CCR ACCB ACCA IXH IXL IYH IYL PCH PCL SP After Operation SP Before Operation Interrupts and Resets 9

10 Interrupt Vector Vector Address BUFFALO Address Interrupt Source CCR Mask Bit FFC0 FFC1 to FFD4 FFD5 Reserved FFD6 FFD7 C4 C6 SCI Serial System I FFD8 FFD9 C7 C9 SPI Serial Transfer Complete I FFDA FFDB CA CC Pulse Accumulator Input Edge I FFDC FFDD CD CF Pulse Accumulator Overflow I FFDE FFDF D0 D2 Timer Overflow I FFE0 FFE1 D3 D5 Timer Input Capture 4/Output Compare 5 I FFE2 FFE3 D6 D8 Timer Output Compare 4 I FFE4 FFE5 D9 DB Timer Output Compare 3 I FFE6 FFE7 DC DE Timer Output Compare 2 I FFE8 FFE9 DF E1 Timer Output Compare 1 I FFEA FFEB E2 E4 Timer Input Capture 3 I FFEC FFED E5 E7 Timer Input Capture 2 I FFEE FFEF E8 EA Timer Input Capture 1 I FFF0 FFF1 EB ED Real-Time Interrupt I FFF2 FFF3 EE F0 IRQ (external pin) I FFF4 FFF5 F1 F3 XIRQ pin X FFF6 FFF7 F4 F6 Software Interrupt None FFF8 FFF9 F7 F9 Illegal Opcode Trap None FFFA FFFB FA FC COP Failure None FFFC FFFD FD FF Clock Monitor Fail None FFFE FFFF RESET None Interrupts and Resets 10

11 Interrupt Example IRQ Handler Routine Initialize Strings IRQHANDLE ORG $3000 LDAA COUNT * A <-- current count INCA * increment count STAA COUNT * write back count LDX #MSG * print out msg JSR OUTSTRG LDX #COUNT * print out count JSR OUT1BYT RTI * all done return ORG $2000 * data section MSG FCC Number of times button pressed: FCB $04 COUNT FCB $00 * button counter Main IRQ Routine ORG JMP $00ee IRQHANDLE Main Program Do Nothing Loop ORG $2200 * main program CLI * enable interrupts LOOP BRA LOOP * endless loop SWI END Interrupts and Resets 11

12 Types of Interrupts Non-Maskable Interrupts Has priority over maskable interrupts Always Interrupts program execution 6 available non-maskable interrupts Maskable Interrupts Adjustable priority level Can be disabled by the I-bit of CCR 15 available maskable interrupts Interrupts and Resets 12

13 XIRQ When a non-maskable interrupt occurs S X H I N Z V C 1 1 X-bit is set to 1, blocking other non-maskable interrupts I -bit is set to 1, blocking other maskable interrupts X-bit cannot be set by software interrupt Interrupts and Resets 13

14 IRQ When a maskable interrupt occurs S X H I N Z V C 0 1 I -bit is set to 1, blocking other maskable interrupts I-bit can be set by software in prevent the execution of interrupts using: -SEI (Set Interrupt Mask) I-bit can be cleared by software using: -CLI (Clear Interrupt Mask) Interrupts and Resets 14

15 Copy Machine Analogy: Scenarios Rohan (Student) Matt (TA) Dr. Ume Regular Instruction IRQ XIRQ Interrupts and Resets 15

16 Copy Machine Analogy: Scenarios S X H I N Z V C 0 0 S X H I N Z V C 0 1 Interrupts and Resets 16

17 Copy Machine Analogy: Scenarios S X H I N Z V C 0 1 S X H I N Z V C 1 1 Interrupts and Resets 17

18 Priority for Non-maskable Interrupts 1. Reset 2. Clock Monitor 3. COP Watchdog 4. Illegal Opcode 5. XIRQ 6. SWI Interrupts and Resets 18

19 7. IRQ Priority for Non-maskable Interrupts 8. Periodic Interrupt/Real-time Interrupt 9. Timer Input Capture Timer Input Capture Timer Input Capture Timer Output Capture Timer Output Capture Timer Output Capture Timer Output Capture Timer Output Capture Timer Overflow 18. Pulse Accumulator Overflow 19. Pulse Accumulator Input Edge 20. SPI Transfer Complete 21. SCI Serial System Interrupts and Resets 19

20 Highest Priority Interrupt Register (HPRIO) Used to increase the priority of 1 maskable interrupt Located at $103C and set on pins 0-3 I-bit must be set to change priority Default is IRQ Interrupts and Resets 20

21 Highest Priority Interrupt Register (HPRIO) Interrupts and Resets 21

22 IRQE in the OPTIONS OPTION $ ADPU CSEL IRQE DLY CME CR1 CR0 IRQE = IRQ Select Edge Sensitive Only (Time Protected) = IRQ configured for low LEVEL (default) 1 = IRQ configured for falling EDGEs Interrupts and Resets 22

23 What are Resets? Reset is used to force a microcontroller unit (MCU) to assume a set of initial conditions and to begin executing instructions from a predetermined starting address. Like interrupts, they fetch vectors to force a new starting point for further CPU operations. Interrupts and Resets 23

24 Types of Interrupts Power-On Reset (POR) External RESET pin COP Watchdog timer Reset. Clock Monitor Reset Interrupt vectors: Interrupts and Resets 24

25 Power-On Reset (POR) Used only for power-up conditions to initialize MCU internal circuits. Applying VDD to the MCU triggers the POR circuit, initiates a reset sequence, and starts an internal timing circuit. A 4064 clock cycle delay after the oscillator becomes active, allows the clock generator to stabilize In some crucial applications which need a longer delay time, external POR circuits are used Interrupts and Resets 25

26 COP Watchdog Timer Reset COP is a timer system to detect software processing errors Software responsible for keep the watchdog timer from running out. Generates Reset request if it runs out. Watchdog Timing pulses are drawn from the E-clock. COP timer rate can be set by using CR1 and CR0 pins of System Configuration Options (OPTION) register. Interrupts and Resets 26

27 Interrupts and Resets 27

28 Servicing the COP Timer 1. Write $55 to COPRST register to arm the clearing mechanism 2. Write $AA to the COPRST register Any number of instructions can be performed between the above 2 steps Must be performed in the correct sequence before the timer times out Rates are set by bits CR1 and CR0 in COPRST register Interrupts and Resets 28

29 Clock Monitor Reset Detects a slow or stopped E clock An E-clock frequency below 10 khz is detected as a clock monitor error Enabled by setting the CME bit in OPTION Useful as a backup for COP watchdog because CMR requires no clock while COP does CMR also provides additional level of protection by generating a system reset if the MCU clocks are accidentally stopped. In case of systems where stop instruction is used, CME bit would first be cleared before calling the STOP command. After recover from STOP, it would be set back to 1 again. Interrupts and Resets 29

30 External RESET External Reset is generated when the user manually presses the Reset button. As soon as the RESET pin goes to Zero, and internal Nchannel device is turned on. This device holds the RESET pin to zero for 4 E- clock cycles (Redundantly) after which it releases. RESET pin is sampled after 2E clock cycles from the time the Nchannel releases the pin. If low : External Reset If high: Internal Reset : either COP Watchdog or Clock Monitor Chance of Misinterpretation Interrupts and Resets 30

31 Reset Priority If in case of External Reset, when RESET pin is not held long enough, the reset is tentatively assumed to have come from COP or Clock Monitor Systems. First checks for Clock monitor and then checks COP watchdog. If neither pending, normal reset vector is selected by default. Interrupts and Resets 31

32 Interrupts and Resets 32

33 Central Processor Unit (CPU) CPU fetches reset vector from the appropriate address location(depends on the kind of reset; explained in detail later) during the first three cycles. Stack pointer and other CPU registers are indeterminate immediately after reset. X and I interrupt mask bits in the CCR are set to mask any interrupt requests. S bit in the CCR is set to disable the stop mode Interrupts and Resets 33

34 Memory Map RAM and I/O mapping register (INIT) is initialized to $01, putting 256 bytes of RAM at locations $0000-$00FF and control registers at locations $ 1000-$103F. 8KB of ROM and 512 B of EEPROM may or may not be present depending on the values of the two bits in CONFIG register that enable them. CONFIG register being a EEPROM cell is not affected by reset or power-down. Interrupts and Resets 34

35 Interrupts and Resets 35

36 (Reference: M68HC11E series Data Sheet) Interrupts and Resets 36

37 Parallel Input/Output (I/O) Strobe A Flag (STAF), strobe A interrupt (STAI), and handshake (HNDS) control bits in parallel I/O control register are cleared (when operating in single chip mode). (This prevents interrupt from being enabled) PortC, Port D(bits 5-0), PortA(bits 0,1,2, and 7), and Port E are configured as general purpose high impedance inputs. Port B and bits 6-3 of PortA have their directions fixed as outputs and their reset state is logic 0. Interrupts and Resets 37

38 Timer Initialized to count of $0000 All output compare (OC) registers are initialized to $FFFF Use OC to program an action to occur at a specific time (when counter matches OC register, task is executed) Input capture registers are indeterminate. IC records the time that an external event takes Interrupts and Resets 38

39 Real-Time Interrupt: RTI interrupt flag is cleared, automatic hardware interrupts are masked. Pulse Accumulator Disabled (PAI pin defaults to a general purpose input). Interrupts and Resets 39

40 Computer Operating Properly (COP) Watchdog Enabled if NOCOP bit in CONFIG register is clear. Other wise disabled. Interrupts and Resets 40

41 Serial Communications Interface (SCI) Baud rate must be reestablished Transmitter and receiver are disabled Serial Peripheral Interface (SPI) Disabled by resetting Analog-to-Digital Converter (A/D) Conversion complete flag is cleared by reset ADPU bit is cleared, disabling A/D system Interrupts and Resets 41

42 Mode of operation Determined by bits set in the HPRIO register Interrupts and Resets 42

43 Process Flow out of Resets When Triggered Vector fetch (program counter loaded with contents of specified address) S, X, and I bits set in the CCR MCU hardware reset Checks for interrupts Interrupts and Resets 43

44 Low Power Mode To reduce power consumption of the controller Temporarily stops CPU operations until a reset or interrupt occurs 2 modes WAIT STOP Interrupts and Resets 44

45 WAIT mode Command: WAI CPU always shut down during wait mode CPU registers are stacked Program is suspended until interrupted On-chip crystal oscillator remains active Power conservation depends on number of peripheral systems shut down A/D converter current can be eliminated by writing the ADPU bit to 0 The SPI system is enabled or disabled by the SPE control bit The SCI transmitter is enabled or disabled by the TE bit, and the SCI receiver is enabled or disabled by the RE bit. Interrupts and Resets 45

46 Command: STOP + S bit of CCR is clear Lowest possible power consumption All clocks are stopped (crystal oscillator too) Data in internal RAM is retained as long as VDD power is maintained Exit using RESET, XIRQ, or unmasked IRQ XIRQ has 2 recover methods If X is set, returns to command following STOP If X is clear, stacking sequence that leads to normal XIRQ request Interrupts and Resets 46

47 References Interrupts made Easy by Mark Minasi (COMPUTE! ISSUE 149 / FEBRUARY 1993 / PAGE 60, ) Previous Interrupts Lectures from ME 6405 ( Reference Manual, Technical Data, and User Guides for the HC11 Interrupts and Resets 47