Figure 1 Circuit for problem 1.

Transcription

1 Problem : Do Shannon s expansion on A'B' + A'BC + A'BDE + AB'C'D' + AB'C'E' L A'B' = L A'B = C + DE L AB' = C'D' + C'E' = (C + DE)' L AB = Observation : (L A'B )' = (C + DE)' = C'(DE)' = C'(D' + E') = C'D' + C'E' = L AB' C D E A B C D E 3-LUT A B 3-LUT L L L A'B (C,D,E) = m(3,4,5,6,7) L(A,B,L A'B ) = m(,,3,4) Figure Circuit for problem. Translating a sum of minterms description of a function into a LUT implementation is shown in Figure. Note, the most significant variable in the sum of minterms is connected to the control input of the righmost mux. Problem 2: Do Shannon s expansion on A'B'C' + A'BC + A'BDE + A'BCF + AB'C + AB Expand on A,B L A'B' = C' L A'B = C + DE + CF (CF can be removed because it is absorbed by C) L AB' = C L AB = C D E 4-LUT A B C 4-LUT Figure 2 Circuit for problem 2. L A'B (,C,D,E) = m(3,4,5,6,7) L(A,B,C,L A'B ) = m(,,5,7,,,2,3,4,5) L

2 Problem 3: Do Shannon s expansion on A'B'CD' + ABCD' + CD'E' + C'D'F + CF' Expand on C,D L C'D' = F L C'D = L CD' = A'B' + AB + E' + F' L CD = F' A B E F 4-LUT C D F 4-LUT Figure 3 Circuit for problem 3. L CD' (A,B,E,F) = m(,,2,3,4,5,6,8,9,,2,3,4,5) L(C,D,F,L CD' ) = m(2,3,9,,2,3) Problem 4: L(A,B,C,D,E,F,G) = AB + CD + EFG To obtain the lowest delay, the AB, CD and EFG terms must be placed in separate LUTs in the first level, and the OR between them takes place in another LUT in the second level (see Figure 4). This leads to four LUTs and a delay of two LUTs. On the other hand EFG may be placed in one LUT, constructing CD + EFG with another and AB + CD + EFG with the third. This leads to three LUTs and a delay of three LUTs. A B 3-LUT A B 3-LUT C D 3-LUT 3-LUT L C D 3-LUT E F G 3-LUT E F G 3-LUT Problem 5: Figure 4 Circuit for problem 4. K(A,B,C,D,E,F) = K(A,B,C,D) = AB + CD L(A,B,C,D,E,F) = L(C,D,E,F) = CD + EF K(A,B,C,D) = m(3,7,,2,3,4,5) L(C,D,E,F) = m(3,7,,2,3,4,5) A B C D 4-LUT K C D E F 4-LUT L Figure 5 Circuit for problem 5.

3 Problem 6: The waveforms are shown in Figure 6. Each LUT delay is 2ns. Time (ns) S S S2 S3 C C2 C3 C4 Figure 6 Circuit for problem 6. Problem 7: The waveforms are shown in Figure 7. Time (ns) S S S2 S3 C C2 C3 C4 Figure 7 Circuit for problem 7. Problem 8: There are four LUT delays from A /B to C 4 /S 3. This implies that the longest propagation delay in the circuit amounts to 8ns. Therefore, the maximum frequency is /8ns = 25 MHz. Note, in reality there are propagation delays through flip-flops (that happen after the edge of the cycle), as well as timing parameters such as hold time and setup time, that have to be taken into account when computing the frequencies. In our examples we consider the ideal case where these timing parameters are considered to be.

4 Problem 9: The state transition diagram is enclosed. w = state = 3'b z = 'b w = state = 3'b z = 'b w = state = 3'b z = 'b w = state = 3'b z = 'b w = state = 3'b z = 'b w = state = 3'b z = 'b w = w = w = w = w = w = Figure 8 State transition diagram for problem 9. The logic equations for the next state and output logic can be extracted for the state transition diagram and they can be written as follows in its sum of minterms form. next_state[] (w,state[2],state[],state[]) = m(8,,2,3) next_state[] (w,state[2],state[],state[]) = m(9,) next_state[2] (w,state[2],state[],state[]) = m(,2,3) z (,state[2],state[],state[]) = m(5) The logic implementation using 4-input LUTs is shown below. Each LUT comprises 6 SRAM cells and a 6-to- multiplexer. The internal implementation of each LUT follows the same principle as in problem. w state[2] state[] state[] 4-LUT D state[] w state[2] state[] state[] 4-LUT D state[] w state[2] state[] state[] 4-LUT D state[2] w state[2] state[] state[] 4-LUT z Figure 9 Circuit implementation for problem 9. Note: The source code is posted online on the course website. This applies to all the problems where the source code is requested.

5 Problem : w = w = w = state = 3'b z = 'b w = state = 3'b z = 'b w = state = 3'b z = 'b state = 3'b z = 'b w = w = state = 3'b z = 'b w = w = w = Figure State transition diagram for problem. Problem : w = w = state = 3'b z = 'b w = w = state = 3'b z = 'b w = state = 3'b z = 'b w = state = 3'b z = 'b w = w = w = w = state = 3'b z = 'b state = 3'b w = z = 'b w = state = 3'b z = 'b w = w = state = 3'b z = 'b w = w = Figure State transition diagram for problem. Problem 2: state = 3'b z = 'b z = 'b w = w w = w' state = 3'b z = 'b z = 'b w = w w = state = 3'b z = 'b z = 'b w = w' state = 3'b z = 'b z = 'b w = w w = w w = w' w = w' state = 3'b z = 'b z = 'b w = w w = w' Figure 2 State transition diagram for problem 2.

6 Problem 3: Both the FSM and the data-path are shown bellow. S_RED control state = S_RED status hold S_RED Note: status and control signals inferred during synthesis since they are not explicitly declared Red Green status advance S_RED Yellow S_GREEN control state = S_GREEN status hold S_GREEN status advance S_GREEN =99 S_YELLOW control state = S_YELLOW status hold S_YELLOW timer + status advance S_YELLOW =9 Figure 3 FSM and data-path for problem 3. Problem 4: Both the FSM and the data-path are shown bellow. e = e = e = & w = & d = S_DISARMED s = e = S_ARMED s = S_ALARM_ON s = w = d = assert reload any other case any other case Note: status and control signals inferred during synthesis since they are not explicitly declared reload control timer = 499 status timer = 299 status =499 =299 timer + e = & timer = 299 assert reload any other case e = & timer = 499 assert reload S_ALARM_OFF s = any other case Figure 4 FSM and data-path for problem 4.

7 Problem 5: Both the FSM and the data-path are shown bellow. start sample range start = EN maximum S_WAIT state = S_WAIT > stop = start = S_ACTIVE state = S_ACTIVE EN minimum stop = < Figure 5 FSM and data-path for problem 5. Problem 6: Note, the priority encoder-type logic circuits for f and g are identical with the exception that f is buffered. Hence, we can share the common logic as shown logic. c c2 g x y z f Figure 6 Circuit for problem 6. Problem 7: start stop shift_ left load serial_in parallel_in 8 EN Load SI << Note: shift enable has a higher priority than load for the shift register parity Figure 7 Circuit for problem 7. 8

8 Problem 8: data_in[] data_in[] data_in[2] data_in[3] data_in[4] data_in[5] 2 data_in[6] 3 data_in[7] Figure 8 Circuit for problem 8. Problem 9: The source code is posted online on the course website. Problem 2: The index shown on top of the signal transitions indicates the counter value that triggers the transition. Frequency of f is MHz / 5 = 2 khz Figure 9 Waveform for problem 2. Problem 2: Frequency of both signals is 2 MHz / 9 = khz. f g Figure 2 Waveform for problem 2. < 9 > 5 f counter + < 25 >5 g < 4 Figure 2 Circuit for problem 2.

9 Problem 22: The source code is posted online on the course website. <4599 >=385 wave counter + <45 >=32 wave2 <38 Figure 22 Circuit for problem 22. Problem 23: The source code is posted online on the course website. < MHz counter + >=27 <3 wave Figure 23 Circuit for problem 23. To reduce the counter size we can observe that all the intervals during one period of the wave signal are multiples of 6 us (microseconds). Therefore, we can use only a 6 us that will not only reduce the counter size, but will also lead to smaller comparator circuitry. < 6 us counter + >=9 < wave Figure 24 Circuit for problem 23.

10 Problem 24: c b a c2 EN f c3 EN g Figure 25 Circuit for problem 24. Problem 25: c c2 a b EN f EN g Figure 26 Circuit for problem 25. Problem 26: The source code is posted online on the course website. Problem 27: The source code is posted online on the course website.

11 Problem 28: a b c Problem 29: Figure 27 Circuit for problem 28. f a b c Problem 3: Figure 28 Circuit for problem 29. f a b c Figure 29 Circuit for problem 3. f

12 Problem 3: The data path is shown in the figure below. Note, in state S_IDLE the value stays unchanged in the register max until start is issued. It should also be clarified that for comparators, the value on the left (or on the top, depending on the orientation of the figure) is the left hand operand. The control information for this problem can be extracted from the source code posted on the course website. state == S_IDLE Clock + 8'd we 'b write_data 6'd SP_RAM read_data 6'h8 state == S_IDLE && start == max < state!= S_IDLE Figure 3 Circuit for problem 3. Problem 32: The data path is shown in the figure below. When using a dual-port RAM, the max value is compared with data coming from both ports and depending on which of the data is larger, the appropriate value will be loaded in the max register. The benefit of the dual-port RAM is to reduce the number of cycles to approximately half of what can be achieved with a single-port RAM implementation. The control information can be extracted from the source code posted on the course website. < state == S_IDLE + 7'd 'b 'b 'b 6'd 8 'b 6'd _a we_a write_data_a _b we_b write_data_b DP_RAM read_data_a read_data_b < 6'h8 > state == S_IDLE && start == state!= S_IDLE Clock max Figure 3 Circuit for problem 32.

13 Problem 33: The data path is shown in the figure below. It should be noted that the sum register is on 24 bits. This implies that the adder is on 24 bits and read_data needs to be sign-extended from 6 to 24 bits. After the sum is accumulated, the average value is read from bits [23:8] of the sum register, which essentially is the same as dividing the sum by 256. state == S_IDLE Clock + 8'd we 'b write_data 6'd SP_RAM read_data state == S_IDLE state == S_FIRST 24'd sum result = sum[23:8] state == S_IDLE && start == Figure 32 Circuit for problem 33. Problem 34: The data path is shown in the figure below. The principle is the same as in the previous problem. The advantage of using the dual-port RAM lies in the ability to reduce the number of cycles to approximately half of what can be achieved with a single-port RAM implementation. This comes however at the disadvantage of using an extra adder that also increases the propagation delay. Nonetheless, the propagation delay can be ed by introducing an additional buffer between the two adders. state == S_IDLE + 7'd 'b 'b 'b 6'd 8 'b 6'd _a we_a write_data_a _b we_b write_data_b DP_RAM read_data_a read_data_b state == S_IDLE state == S_FIRST 24'd state == S_IDLE && start == Clock sum result = sum[23:8] Figure 33 Circuit for problem 34.

14 Problem 35: The data path is shown in the figure below. 6'd + FSM 7'd A_buffer data_select 7 8 we SP_RAM write_data read_data 6'd Clock B_buffer Figure 34 Circuit for problem 35. The basic operations of the FSM from the above data path are illustrated in the enclosed state table. The data_select signal decides which part of the memory is accessed in each cycle (A and S are stored in the top half and B and D are stored in the bottom half). Note, there is one cycle latency for reading from and writing to the embedded RAM. As shown in the state table, after any two consecutive reads from the memory, there will be two consecutive writes. A_buffer and B_buffer are necessary to hold the values read from the memory before performing subtraction. Clock state S_IDLE S_READ_A S_READ_B S_WRITE_S S_WRITE_D S_READ_A S_READ_B S_WRITE_S S_WRITE_D data_select read_data A[] B[] S[] D[] A[] B[] S[] we A_buffer A[] A[] A[] A[] A[] A[] B_buffer B[] B[] B[] B[] B[] write_data S[] D[] S[] D[] Table State table for problem 35.

15 Problem 36: The data path is shown in the figure below. + FSM 7'd 'b 'b _a we_a write_data_a _b we_b write_data_b DP_RAM read_data_a read_data_b Clock Figure 35 Circuit for problem 36. The basic operations of the FSM from the above data path are illustrated in the enclosed state table. By employing a dual-port RAM, there is no need to buffer any data. Each of the ports accesses one half of the RAM and each read is followed by one write. Note also, unlike the implementation using a single-port RAM, the most significant bit of the for the top port is always and the most significant bit of the for the bottom port is always. In this particular case, a dual-port RAM implementation does not reduce only the cycle count, but it also lowers the resource usage. Clock state S_IDLE S_READ S_WRITE S_READ S_WRITE S_READ S_WRITE S_READ S_WRITE _a read_data_a A[] A[] S[] A[] S[] A[2] S[2] A[3] read_data_b B[] B[] D[] B[] D[] B[2] D[2] B[3] we write_data_a S[] S[] S[2] S[3] write_data_b D[] D[] D[2] D[3] Table 2 State table for problem 36.

16 A_buffer_ Problem 37: The data path is shown in the figure below. In the problem statement, the following equation was given: B[i]=(A[i-] 2*A[i] + 4*A[i+])/4. In this particular solution, we choose to rewrite the equation to B[i]=A[i-]/4 A[i]/2 + A[i+]. This enables us to avoid using adders on more bits than the bitwidth of the data from the RAM. This is achieved by arithmetic shifting the data to the right (i.e., division by 2) before it is loaded into the buffers. + 8'd - FSM we SP_RAM write_data load_enable read_data >>> >>> EN EN A_buffer_ minus_ Clock Figure 36 Circuit for problem 37. The basic operations of the FSM from the above data path are illustrated in the enclosed state table. In the state table below, the register from the left-hand side of the figure is shown (and not the port of the RAM). It should be noted that the value from the register is passed to the RAM during the read cycles through a mux that can also select minus one during the write cycles. Clock state S_IDLE S_INIT_FIRST S_INIT_SECOND S_WRITE S_READ S_WRITE S_READ S_WRITE read_data A[] A[] A[] B[] A[2] B[] A[3] load_enable A_Buffer_ A[] A[] A[] A[] A[2] A[2] A_Buffer_minus_ A[] A[] A[] A[] A[] we write_data B[] B[] B[2] Table 3 State table for problem 37.

17 A_buffer_ Problem 38: The data path is shown in the figure below. + FSM load_enable 8'd -2 8'd255 8'd254 'b 6'd _a we_a write_data_a _b we_b write_data_b read_data_a >>> >>> DP_RAM EN EN A_buffer_ minus_ Clock Figure 37 Circuit for problem 38. The basic operations of the FSM from the above data path are illustrated in the enclosed state table. In this dual-port RAM implementation, the top port is always used for reading and the bottom port is always used for writing. This allows data to be written every cycle. Although not shown in the state table (but available in the source code), the FSM implements also the conditions for the last two reads from and writes to the memory. Clock state S_IDLE S_INIT_FIRST S_INIT_SECOND S_WRITE S_WRITE S_WRITE S_WRITE S_WRITE _a read_data_a A[] A[] A[] A[2] A[3] A[4] A[5] load_enable A_Buffer_ A[] A[] A[] A[2] A[3] A[4] A_buffer_minus_ A[] A[] A[] A[2] A[3] _b we write_data_b B[] B[] B[2] B[3] B[4] Table 4 State table for problem 38.

18 Problem 39: The data path is shown in the figure below. This implementation takes advantage of the data dependency from the recurrence equation that describes the Fibonacci series. The accumulator stores A[i-] and the read_data coming from the memory gives A[i-2]. This allows new data A[i] to be calculated and written to the memory in the following cycle. This operation is performed every single cycle. + 4'd FSM 'd Clock we write_data SP_RAM read_data accumulator Figure 38 Circuit for problem 39. The basic operations of the FSM from the above data path are illustrated in the enclosed state table. Please note in cycle 3 the accumulator computes A[2] by summing A[] with A[]. This is not necessarily how the recurrence equation defines A[2], however we exploit the fact that the first two entries in the Fibonacci series are equal. Clock state S_IDLE S_R S_R S_WRITE S_WRITE S_WRITE S_WRITE S_WRITE read_data A[] A[] A[] A[2] A[3] A[4] A[5] accumulator A[] A[]+A[]=A[2] A[2]+A[]=A[3] A[3]+A[2]=A[4] A[4]+A[3]=A[5] A[5]+A[4]=A[6] we Table 5 State table for problem 39.

19 Problem 4: The data path is shown in the figure below. This implementation based on dual-port RAMs does not rely on any buffers. We rewrite the Fibonacci recurrence equation as follows: A[i] = A[i-] + A[i-2] and A[i+] = A[i] + A[i-] = 2*A[i-] + A[i-2]. Thus, two new values are computed at the same time using the same operands. This can be achieved by employing the adder tree shown at the bottom of the figure. FSM +2 4'd _a we_a read_data_a write_data_a + _b we_b DP_RAM write_data_b read_data_b Clock Figure 39 Circuit for problem 4. The basic operations of the FSM from the above data path are illustrated in the enclosed state table. The first two operands (A[] and A[]) are read from the memory in cycle and the first new values (A[2] and A[3]) are computed and written back in cycle 2. Because the values of A[2] and A[3] will be available at the output data ports of the memory in cycle 3, we can reuse them to compute A[4] and A[5], which are written to the memory in the same cycle. Clock state S_IDLE S_READ S_WRITE S_WRITE S_WRITE S_WRITE _a _b read_data_a A[] A[2] A[4] A[6] read_data_b A[] A[3] A[5] A[7] we write_data_a A[]+A[]=A[2] A[2]+A[3]=A[4] A[6] A[8] write_data_b A[]+A[]+A[]=A[3]A[2]+A[3]+A[3]=A[5] A[7] A[9] Table 6 State table for problem 4.

20 Problem 4: In a block of 8x8 the total number of elements is 64. The pixel counter iterates from to 63 and it uses its 3 least significant bits as the 3-bit offset in the column (ca) and its 3 most significant bits as the 3-bit offset in the row (ra). Please note the offset in a group of signals is defined by the least significant bits of that signal. Given the fact that the image is 6x6, there will be 2 blocks on the horizontal axis and 2 blocks on the vertical axis. This requires two hierarchical modulo 2 counters connected as shown in the enclosed figure. Whenever the pixel counter reaches 63, the column block counter (cb) will be incremented. When cb is 9 and pixel counter reaches 63, cb will be reset to and the row block counter (rb) will be incremented (note, this rb counter is also modulo 2). The column is created by placing cb on the 5 most significant bits of ca and the row is created by placing rb on the 5 most significant bits of ra. It is important to note that both ra and ca are on 8 bits, which is justified by the fact that both of them iterate from to 59 (the number of both rows and columns is 6). The memory is given by 6*ra + ca. Using a multiplier for the multiplication with constant 6 is avoided by observing that 6= This enables us to use two left shifts on signal ra (by 7 and 5 positions respectively) which is followed by one addition on 5 bits. The result of 6*ra is on 5 bits and it is added to ca (which is an 8 bit signals that is extended to 5 bits with 7 zeros on the most significant positions) to obtain the memory, which is also on 5 bits (as required to iterate from to 25599). ra = {rb,pixel[5:3]} ca = {cb,pixel[2:]} = 6*ra + ca + =9 + = pixel cb rb 5 3 ([2:]) 5 3 ([5:3]) ca *ra ra 6*ra 28*ra 7 Figure 4 Circuit for problem 4. Note, in the above figure it is assumed that when concatenating two signals, the signal on the top or on the left represents the more significant bits.

21 Problem 42: A block of size 6x8 will imply 28 elements per block and only blocks on the horizontal axis. The reasoning is similar as for problem 4. ra = {rb,pixel[6:4]} ca = {cb,pixel[3:]} = 6*ra + ca + =9 + = pixel cb rb 4 4 ([3:]) 5 3 ([6:4]) ca *ra ra 6*ra 28*ra 7 Figure 4 Circuit for problem 42. Problem 43: A block of size 8x6 will imply 28 elements per block and only blocks on the vertical axis. The reasoning is similar as for problem 4. ra = {rb,pixel[6:3]} ca = {cb,pixel[2:]} = 6*ra + ca + =9 + = pixel cb rb 5 3 ([2:]) 4 4 ([6:3]) ca *ra ra 6*ra 28*ra 7 Figure 42 Circuit for problem 43.

22 Problem 44: If the most significant bit [5] of the input number is then the number is positive. If at least one of the bits [4:8] of this positive number is non-zero then the number is greater than 255 and it needs to be saturated. If bit [5] of the input number is then the number is negative. If at least one of the bits [4:8] of this negative number is zero then the number is smaller than -256 and it needs to be saturated. In any other case the output equals the input. ([5]) 6 6 ([4:9]) ([8]) 7 ([4:8]) ([7:]) 9 ([8:]) -256 Figure 43 Circuit for problem 44. Problem 45: The basic principle of operation of the right-most multiplexers shown in the enclosed figure is similar to the one described in the previous problem. In addition, bits [8:7] need also to be checked to ensure that the number is between 28 and 5 or between -28 and -52. If the input number is positive and bits [8:7] are both then the number needs to be saturated to 28 (as requested in the problem statement). Similarly, if the input number is negative and bits [8:7] are both then the number needs to be saturated to -28. ([5]) 6 5 ([4:]) ([9]) 2 ([8:7]) 7 ([6:]) 6 ([4:9]) ([9:]) 2 ([8:7]) Figure 44 Circuit for problem 45.

23 Problem 46: The source code is posted online on the course website and it can be used to better understand the control FSM from the figure. In the following only the basic intuition behind the method is described. The three matrices A, B and S are stored in three different dual-port RAMs. Since 2 multipliers are available, matrix multiplication can be parallelized by exploiting the fact that different elements from matrix S can be computed at the same time. For example, to compute elements S and S 4 we need rows and 4 from matrix A and column from matrix B. This can be done by accessing rows and 4 from matrix A at the same time and passing the values to 2 different multiply and accumulate (MAC) units. This is achieved by using the same 5-bit offset on the es of the two ports of the RAM that contains A. Only the most significant bit differs on the es of the two ports, as they will point to the locations from row and 4 respectively. Note, the values from matrix B (column ) are used by both MAC units. The es for all the memories are generated using a state counter controlled by the top-level FSM. The index part of the state counter (three least significant bits) is used to iterate through the 8 elements from matrices A and B required for each element of S. Once the 8 elements have been multiplied and accumulated, the most significant bits from the state counter are used to create the for writing in the dual-port RAM that stores matrix S S_row 3 S_col 3 index state_counter 6 6 A DI we A2 DI2 we2 A DI we A2 DI2 we2 A B DO DO2 DO DO2 EN 6 6 Control FSM A DI we A2 DI2 we2 S DO DO2 Figure 45 Circuit for problem 46. Problem 47: The basic principle is to decompose the problem into a sequence of states that performs matrix multiplication of two 8x8 matrices. The arithmetic resources can thus be shared and more details can be found in the source code available on the course website. Problem 48: The reasoning is the same as in the case of problem 47, with the exception that two multipliers can be used. More details can be found in the source code available on the course website.

24 Problem 49: Based on the position of the sample in the input sequence we will decide by how many positions the input data will be shifted. It is assumed that the input data is on n bits. Without loss of generality it is assumed the input samples are unsigned. Because the problem statement does not specify explicitly the bitwidth of the output data, it is assumed that this value is n+6 (i.e., the number of bits required to represent the maximum value on the output, since the largest coefficient in the quantization matrix is 64=2 6 ). The var left shift box from the figure is a shifting unit that uses 3 control inputs (signal v in the figure) to decide by how many bits the data is shifted to the left. It s basic operation is identical to the var left shift unit from the next problem (and its operating principle will be detailed in the answer to the next problem). Because the input data is processed in the zig-zag sequence we take the 3 least significant bits from the zig-zag counter (called pixel ) and add them to the 3 most significant bits from the zigzag counter. This addition of two 3-bit unsigned numbers will result in a 3-bit result with an output carry. This output carry is concatenated to the most significant position of the adder result. This creates a 4-bit signal that represents the sum of the row and column index in the quantization matrix. It should be noted that the entries in the quantization matrix are identical for the same value of this 4-bit signal and these entries are used to determine by how many positions to left shift the input data. As given in the problem statement, the quantization matrix has only powers of 2 and all the values are greater than. This implies that the least significant bit of the output will always be. Therefore, the input data will be shifted by to 5 positions to the left. Consequently, the var left shift will perform the multiplication by to 32 and the concatenation of to the least significant bit of the output data will do an additional multiplication by 2. Next state for zig-zag Input data n 2 Var left shift n+5 n+6 3 Output data V 6 pixel =7 =6 =5 =4 =3 3 ([5:3]) 4 =2 = = 3 ([2:]) Figure 46 Circuit for problem 49.

25 Problem 5: Var Input left data n shift n+3 n Output data V Next state for zig-zag 6 pixel >=4 <=7 >=8 <= = =4 3 ([5:3]) 4 3 ([2:]) Figure 47 Circuit for problem 5. This problem is similar to the previous question. The comparisons are however done differently because the values 2 and 4 are appearing on both ends of the quantization matrix. What needs to be emphasized is the structure of the var left shift unit. This unit consists of 4-to- multiplexers as shown below. The number of multiplexers is n+3 (i.e., the number of bits at the output of the var left shift unit). I j stands for bit j in the input data and O j stands for bit j in the output data. Because input data is on n bits, I -, I -2, and I -3 are all s. As in the case of the previous problem it is assumed that the numbers are unsigned. Therefore, I n, I n+, and I n+2 are also all s. Note however, if our assumption would be that the input numbers are signed then I n, I n+, and I n+2 would be equal to I n-. Ij Ij- Ij-2 Ij-3 V V Oj j from to n+2 and I-=I-2=I-3= and In=In+=In+2= Figure 48 Circuit for problem 5 (similar to var left shift unit from problem 49).