POS-PHY Level 4 POS-PHY Level 3 Bridge Reference Design

Transcription

1 Level 4 Bridge Reference Design October 2001; ver Application Note 180 General Description This application note describes how the Level 4 Bridge reference design can be used to bridge packet or cell traffic from a single OC-192c SONET/SDH stream (single-phy) to four OC-48 network processors, in ingress and egress directions. Figure 1 shows an example block diagram. For quad-oc-48c line card applications, this reference design is not required and the multi-phy Level 4 function could be connected directly to the functions. Figure 1. Typical Application interfaces Ingress Level 4 interface Network Processor (OC-48) OC-192c Framer Level 4 to Bridge Network Processor (OC-48) Network Processor (OC-48) APEX II device Network Processor (OC-48) Egress Altera Corporation 1 A-AN

2 Level 4-- Bridge Reference Design Application Note Features Provides an interface between the Altera Level 4 and POS- PHY functions Provides round-robin distributional packets from the Level 4 interface to the interfaces, feedback is based on buffer fill levels Supports up to four functions, and one Level 4 function, all configured for single-phy mode Supports Level 4 data rates of up to gigabits per second (Gbps) Supports data rates of up to Gbps Uses the Atlantic TM interface for ingress and egress directions Level 4 and s The Level 4 and functions support packet transfers between physical (PHY) and link layer devices. They support single-phy (SPHY) or multi-phy (MPHY) operation. This reference design is for single-phy applications only. The Level 4 function supports a data rate of up to Gbps (832 MHz x 16 bits). The function has a data rate of up to Gbps (104 MHz x 32 bits). When the Level 4 function has a data rate of Gbps, it can be connected to three (9.952 Gbps /3.328 Gbps) functions. This is known as minimum case. When the Level 4 function has a data rate of Gbps, it can be connected to four ( Gbps / Gbps) functions. This is known as maximum case. Atlantic Interface The Atlantic interface is a full-duplex synchronous bus protocol supporting both packets and cells. The Atlantic interface s configurable width of 8, 16, 32, 64, or 128 bits allows translation between different bus types. The Level 4 function is an Atlantic interface slave source and sink. It uses a 128-bit wide data path to deliver packets to the Level 4 bridge reference design which is also an Atlantic interface slave source and sink. 2 Altera Corporation

3 Level 4-- Bridge Reference Design Application Note The Atlantic interface provides a connection between the bridge and the FIFO buffers. The width of the output bus (to FIFO buffer) is also 128-bits wide. The FIFO buffers are used for crossing the clock domain from the Atlantic interface to the functions. The Atlantic interface width from the FIFO buffers to the functions is 32 bits. f For further information on this interface, refer to the Atlantic Interface al Specification, available at Packet Sizes Packet sizes can vary, but the empty (MTY), start of packet (SOP) and end of packet (EOP) signals must be functional. Figure 2 shows a high-level block diagram of the Level 4 to reference design, and neighboring functions. Figure 2. Ingress Block Diagram Atlantic Interfaces FIFO (10,238 bytes) PHY Interface Level 4 Level 4 to Reference Design FIFO (10,238 bytes) FIFO (10,238 bytes) PHY Interface PHY Interface FIFO (10,238 bytes) PHY Interface Altera Corporation 3

4 Level 4-- Bridge Reference Design Application Note Figure 3 shows a high-level block diagram of the to Level 4 reference design, and neighboring functions. Figure 3. Egress Block Diagram Atlantic Interfaces FIFO (14,400 bytes) PHY Interface Level 4 to Level 4 Reference Design FIFO (14,400 bytes) FIFO (14,400 bytes) PHY Interface PHY Interface FIFO (14,400 bytes) PHY Interface al Description This reference design comprises two bridges: one bridge connects a single Level 4 source (receiver) to multiple sinks (transmitters), the other bridge connects multiple sources to a single Level 4 sink. 4 Altera Corporation

5 Level 4-- Bridge Reference Design Application Note Level 4 to Bridge Figure 4 shows a block diagram of a bridge with a single Level 4 source and multiple sinks. Features Connects a slave source to multiple slave sinks by acting as a master on both sides Supports one Level 4 function on the source side, and up to four functions on the sink side Supports Level 4 data rates of up to Gbps Supports data rates of up to Gbps Uses the Atlantic interface in the source and sink directions Figure 4. Level 4 to Bridge. snkdat[127:0] snksop snkeop snkmty[3:0] snkerr To all s srcdat[127:0] From Level 4 srcdav srcval srcsop srceop srcmty[3:0] srcerr Level 4 to Bridge snk1ena snk1dav snk2ena snk2dav #1 #2 srcena snk3ena snk3dav #3 snk4ena snk4dav #4 Altera Corporation 5

6 Level 4-- Bridge Reference Design Application Note The Level 4 to bridge monitors srcdav from the Level 4 function. When the Level 4 function has enough data to send a complete packet, it asserts its srcdav. When srcdav is asserted, the bridge polls the four functions in a round robin fashion, searching for an asserted data available signal snkndav (where n can be 1, 2, 3, or 4). The bridge connects the first function with an asserted dav line to the Level 4 function which begins the packet transfer. This transfer occurs until srceop is asserted, indicating that a complete packet has been sent. The bridge can now repeat the polling cycle. to Level 4 Bridge Figure 5 shows a block diagram of a bridge with multiple Level 3 sources and a single Level 4 sink. Features Connects multiple slave sources to a slave sink by acting as a master on both sides Supports up to four functions on the source side, and one Level 4 function on the sink side Supports Level 4 data rates of up to Gbps (clock rate of 104 MHz) Supports data rates of up to Gbps (clock rate of 104 MHz) Uses the Atlantic interface in the source and sink directions 6 Altera Corporation

7 Level 4-- Bridge Reference Design Application Note Figure 5. to Level 4 Bridge src1dat[127:0] src1dav From #1 src1val src1sop src1eop src1mty[3:0] src1err snkdat[127:0] snkdav src1ena to Level 4 Bridge snksop snkeop snkmty[3:0] Level 4 src4dat[127:0] src4dav snkerr From #4 src4val src4sop src4eop src4mty[3:0] src4err src4ena snkena The to Level 4 bridge monitors snkdav from the Level 4 function. When the Level 4 function has enough space to accept a complete packet, the snkdav signal is asserted. When snkdav is asserted, the bridge polls the four functions in a round robin fashion, searching for the next one with an asserted data available signal srcndav (where n can be 1, 2, 3, or 4). The bridge connects the output signals from the first function with an asserted dav line to the Level 4 input signals for packet transfer. The transfer occurs until the srceop signal is asserted, indicating that a complete packet has been sent. The bridge can now repeat the polling cycle. Altera Corporation 7

8 Level 4-- Bridge Reference Design Application Note FIFO Buffer Size Packet sizes can vary from 1 byte to 9600 bytes. This section calculates the FIFO buffer sizes needed based on the limits set by the minimum and maximum cases, see Level 4 and s on page 2. Level 4 to Rate Relationship is 3D PL3 = D PL4 using 3 FIFO Buffers is sent out of the FIFO buffer at 1/3 of the rate at which it is received. Therefore, in the period that a packet of 9,600 bytes is received, 3,200 bytes have been sent out leaving 6,400 bytes in the FIFO buffer. In the worst-case scenario, the FIFO buffers receive the following number of bytes, in order: FIFO buffer 1 receives 9,600 bytes FIFO buffer 2 receives 6,400 (2/3 of 9,600) bytes FIFO buffer 3 receives 4,267 (2/3 of 6,400) bytes 1 While the latter FIFO buffers are still receiving data, the former FIFO buffers are constantly sending out data. By the time the third FIFO buffer has received the complete packet of 4,267 bytes, all three FIFO buffers contain 2,844 (2/3 of 4,267) bytes. If the next packet received is 9,600, the FIFO buffer will contain 2,844 + (2/3 of 9,600) = 9,245 bytes. Therefore, the maximum size of each of the four FIFO buffers should be 9,245 bytes. 8 Altera Corporation

9 Level 4-- Bridge Reference Design Application Note Formula: D - Relationship between the rate of reading out of, and the rate of writing into the FIFO buffer. D = rate of reading, PL3 rate rate of writing, PL4 rate 1 PL3 rate < PL4 rate, therefore D < 1. F Number of FIFO buffers P Maximum packet size (in bytes) Fs Minimum FIFO buffer size needed Fs = (1- D) F xp + (1-D)xP T = (1 - D) P 1 This formula can be used only if F > 1/D. Example 1: If D = 1/3, F = 4, P = 9,600; Minimum size of FIFO buffer needed, Fs = (2/3) 4 x 9,600 + (2/3) x 9,600 = 8,296 bytes Example 2: If D = 1/4, F = 4, P = 9,600; Minimum size of FIFO buffer needed, Fs = (3/4) 4 9,600 + (3/4) 9,600 = 10,238 bytes Altera Corporation 9

10 Level 4-- Bridge Reference Design Application Note to Level 4 Formula: D - Relationship between the rate of reading out of, and the rate of writing into the FIFO buffer. rate of writing, PL3 rate D = rate of reading, PL4 rate 1 PL3 rate < PL4 rate, therefore D< 1. F Number of FIFO buffers P Maximum packet size (in bytes) Fs Minimum FIFO buffer size needed T Lower Threshold, the number of bytes needed in the FIFO buffer before the packet can be read Fs = 2 ( xp F 1) F T = ( 1 D)xP Rate Relationship is 3D PL3 = D PL4 using 3 FIFO Buffers is sent out of the FIFO buffer at three times the rate at which it is received. Therefore, in the period that a packet of 9,600 bytes is read, 3,200 bytes have been written. Each FIFO buffer asserts its data available (dav) signal when the lower threshold (T) value has been reached, or an EOP signal has been written into the FIFO buffer. 10 Altera Corporation

11 Level 4-- Bridge Reference Design Application Note Table 1 shows the data flow within the three FIFO buffers. Table 1. Flow (3 FIFO Buffers) Time Action Bytes Contained in each FIFO Buffer FIFO 0 FIFO 1 FIFO 2 0 Start FIFO buffers 0, 1, and 2 write in 3,200 bytes. 3,200 3,200 3,200 2 FIFO buffers 0, 1, and 2 write in another 3,200 bytes. 6,400 6,400 6, ,600 bytes from FIFO buffer 0 are read out. FIFO buffers 0, 1, and 2 write in another 3,200 bytes. 0 9,600 9, ,600 bytes from FIFO buffer 1 are read out. FIFO buffers 0, 1, and 2 write in another 3,200 bytes. 5 9,600 bytes from FIFO buffer 2 are read out. FIFO buffers 0, 1, and 2 write in another 3,200 bytes. 6 9,600 bytes from FIFO buffer 0 are read out. FIFO buffers 0, 1, and 2 write in another 3,200 bytes. 7 Repeat actions from Time 4 to Time 6. The lower threshold (T) and the maximum FIFO buffer size are calculated as follows: Example: If D = 1/3, F = 3, P = 9,600; 3,200 3,200 12,800 6,400 6,400 6, ,600 9,600 Minimum size of FIFO buffer needed, Fs = 2(3-1)/3 x 9,600 = 12,800 bytes Lower Threshold, T = (2/3) 9,600 = 6,400 bytes Rate Relationship is 4D PL3 = D PL4 using 4 FIFO Buffers is sent out of the FIFO buffer at four times the rate at which it is received. Therefore, in the period that a packet of 9,600 bytes is read, 2,400 bytes have been written. Each FIFO buffer asserts its data available (dav) signal when the lower threshold (T) value has been reached, or an EOP signal has been written into the FIFO buffer. Altera Corporation 11

12 Level 4-- Bridge Reference Design Application Note Table 2 shows the data flow within the four FIFO buffers. Table 2. Flow (4 FIFO buffers) Time Action Bytes Contained in each FIFO Buffer FIFO 0 FIFO 1 FIFO 2 FIFO 3 0 Start FIFO buffers 0, 1, 2 and 3 write in 2,400 bytes. 2,400 2,400 2,400 2,400 2 FIFO buffers 0, 1, 2 and 3 write in another 2,400 bytes. 4,800 4,800 4,800 4, ,600 bytes from FIFO buffer 0 are read out. FIFO buffers 0, 1, 2 and 3 write in another 2,400 bytes. 7,200 7,200 7,200 7, ,600 bytes from FIFO buffer 1 are read out. FIFO buffers 0, 1, 2 and 3 write in another 2,400 bytes. 5 9,600 bytes from FIFO buffer 2 are read out. FIFO buffers 0, 1, 2 and 3 write in another 2,400 bytes. 6 9,600 bytes from FIFO buffer 3 are read out. FIFO buffers 0, 1, 2 and 3 write in another 2,400 bytes. 7 9,600 bytes from FIFO buffer 0 are read out. FIFO buffers 0, 1, 2 and 3 write in another 2,400 bytes. 8 Repeat actions from Time 4 to Time 7. The lower threshold (T) and the maximum FIFO buffer size are calculated as follows: Example: If D = 1/4, F = 4, P = 9,600; 0 9,600 9,600 9,600 2,400 2,400 12,000 12,000 4,800 4,800 4,800 14,400 7,200 7,200 7,200 7,200 Minimum size of FIFO buffer needed, Fs = 2(4-1)/4 x 9,600 = 14,400 bytes Lower Threshold, T = (3/4) 9,600 = 7,200 bytes I/O Signals This table shows the generic signal names used for both the to Level 4 and the Level 4 to Level 3 blocks. Table 3. I/O Signals (Part 1 of 2) Signal (1) Direction Description srcndat[127:0] Input Source data bus srcndav Input Source data available (asserted when a complete packet of data is available for transfer) srcnsop Input Source start of packet 12 Altera Corporation

13 Level 4-- Bridge Reference Design Application Note Table 3. I/O Signals (Part 2 of 2) srcneop Input Source end of packet srcnmty [3:0] Input Source number of empty bytes srcnerr Input Source error signal srcnval Input Source valid data signal srcnena Output Source enable signal snkndat [127:0] Output Sink data bus snkndav Input Sink data available (asserted when there is enough space to receive a complete packet of data) snknsop Output Sink start of packet snkneop Output Sink end of packet snknmty [3:0] Output Sink number of empty bytes snknerr Output Sink error signal snknena Output Sink enable signal Note: (1) When there are multiple sources or multiple sinks, replace the n with the module number. If there is only one source or sink, simply delete the n. Configuration The Level 4 to Bridge reference design supports almost all configurations of the Level 4 and functions, provided both functions are configured for single-phy operation. Table 4 and Table 5 show example settings required for the functions to operate with the bridge. Table 4. Level 4 Configuration Settings (Part 1 of 2) Optional Features Choices Flow Direction Rx Tx Atlantic Width Calender_ Length 1 1 Embedded Address (1) No No FIFO Buffer Depth FIFO Pipeline Almost Empty Almost Full FIFO_Threshold Low FIFO_Threshold High Calender_M 2,048 2,048 Maxburst Altera Corporation 13

14 Level 4-- Bridge Reference Design Application Note Table 4. Level 4 Configuration Settings (Part 2 of 2) Optional Features Choices Maxburst MaxT Training Pattern Repetitions No No Transmit Bandwidth Optimization Yes Yes Note: (1) The Level 4 function must have its embedded address (EADDR) parameter set to No. The Yes option is not supported in this bridge reference design. Table 5. Configuration Settings Optional Features Parameters Choices Architecture Options Interface Type Interface A Bus Direction Number of Channels A Interface B Interfaces Interface Type Source 1 Link Layer Atlantic Master Interface Settings A Interface Bus Width Parity Settings FIFO Settings Address & Packet Available Settings B Interfaces Bus Width Clock Selection A Interface B Interfaces Parity A Interface Empty Threshold Burst Remote Burst B Interfaces Size Full Threshold Burst Remote Burst A Interface Packet Available Mode B Interfaces Packet Available Mode 32 A Clock (No FIFO) None None Direct (No Addressing) Direct (No Addressing) Sink 1 Link Layer Atlantic Master 32 A Clock (No FIFO) None None Direct (No Addressing) Direct (No Addressing) 14 Altera Corporation

15 Level 4-- Bridge Reference Design Application Note Resource Usage Table 6 lists the estimated resources used by the reference design and the Level 4 and functions instantiated to operate with the bridge. These numbers are subject to change depending on the chosen configurations of the functions. Table 6. Resource Usage LE ESB Level 4 to bridge to Level 4 bridge Atlantic FIFO from 32 bits to 128 bits ( 4) 1,428(1) 36 Atlantic FIFO from 128 bits to 32 bits ( 4) 1,192(2) 36 Level 4 function Receiver 7, Level 4 function Transmitter 3, function Receivers ( 4) function Transmitters ( 4) Total Resource Usage 15, Notes: (1) For the to Level 4 bridge, the minimum FIFO buffer size needed for data is 14,400 bytes (113 by 128-bit words). (2) For the Level 4 to bridge, the minimum FIFO buffer size needed for data is 10,238 bytes (80 by 128-bit words). Altera Corporation 15

16 Level 4-- Bridge Reference Design Application Note Timing Figure 6 shows the timing relationship between the various I/O signals. Figure 6. Timing Diagram clock srcdav srcena srcval pkt n pkt n+1 srcdat,srcmty,srcerr invalid D2 D3 Deop Dsop invalid D2 D3 srcsop srceop internal sop buffer Dsop (Pkt n) Dsop (Pkt n+1) snkdav snkena snkdat,snkmty,snkerr invalid Dsop D2 D3 Deop invalid Dsop D2 snksop snkeop 101 Innovation Drive San Jose, CA (408) Applications Hotline: (800) 800-EPLD Customer Marketing: (408) Literature Services: lit_req@altera.com Copyright 2001 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. All rights reserved. 16 Altera Corporation