FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM

Transcription

1 FEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port AM Features Functional Description True dual-ported memory cells that allow simultaneous access of the same memory location Synchronous pipelined operation Family of 4-Mbit, 9-Mbit, and 18-Mbit devices Pipelined output mode allows fast operation 0.18-micron CMOS for optimum speed and power High-speed clock to data access 3.3V low power Active as low as 225 ma (typ) Standby as low as 55 ma (typ) Mailbox function for message passing Global master reset Separate byte enables on both ports Commercial and industrial temperature ranges IEEE compatible JTAG boundary scan 484-ball FBGA (1-mm pitch) Pb-Free packaging available Counter wrap around control Internal mask register controls counter wrap-around Counter-interrupt flags to indicate wrap-around Memory block retransmit operation Counter readback on address lines Mask register readback on address lines Dual Chip Enables on both ports for easy depth expansion Seamless Migration to Next Generation Dual-Port Family Table 1. Product Selection Guide The FEx72 family includes 4-Mbit, 9-Mbit and 18-Mbit pipelined, synchronous, true dual-port static AMs that are high-speed, low-power 3.3V CMOS. Two ports are provided, permitting independent, simultaneous access to any location in memory. The result of writing to the same location by more than one port at the same time is undefined. egisters on control, address, and data lines allow for minimal set-up and hold time. During a ead operation, data is registered for decreased cycle time. Each port contains a burst counter on the input address register. After externally loading the counter with the initial address, the counter will increment the address internally (more details to follow). The internal write pulse width is independent of the duration of the /W input signal. The internal write pulse is self-timed to allow the shortest possible cycle times. A HIGH on CE0 or OW on CE1 for one clock cycle will power down the internal circuitry to reduce the static power consumption. One cycle with chip enables asserted is required to reactivate the outputs. Additional features include: readback of burst-counter internal address value on address lines, counter-mask registers to control the counter wrap-around, counter interrupt (CNTINT) flags, readback of mask register value on address lines, retransmit functionality, interrupt flags for message passing, JTAG for boundary scan, and asynchronous Master eset (MST). The device have limited features. Please see Address Counter and Mask egister Operations [17] on page 6 for details. Seamless Migration to Next-Generation Dual-Port Family Cypress offers a migration path for all devices to the next-generation devices in the Dual-Port family with a compatible footprint. Please contact Cypress Sales for more details. Density 4-Mbit (64K x 72) 9-Mbit (128K x 72) 18-Mbit (256K x 72) Part Number CYD04S72V Max. Speed (MHz) Max. Access Time Clock to Data (ns) Typical operating current (ma) Package 484-ball FBGA 23 mm x 23 mm 484-ball FBGA 23 mm x 23 mm 484-ball FBGA 23 mm x 23 mm Cypress Semiconductor Corporation 198 Champion Court San Jose, CA Document #: ev. *I evised May 2, 2006

2 ogic Block Diagram [1] FTSE FTSE POTST[1:0] CONFIG Block CONFIG Block POTST[1:0] DQ[71:0] BE [7:0] CE0 CE1 OE IO Control IO Control DQ [71:0] BE [7:0] CE0 CE1 OE /W /W Dual-Ported Array BUSY Arbitration ogic BUSY A [17:0] CNT/MSK ADS CNTEN CNTST ET CNTINT C Address & Counter ogic Address & Counter ogic A [17:0] CNT/MSK ADS CNTEN CNTST ET CNTINT C WP WP INT Mailboxes INT JTAG TST TMS TDI TDO TCK EADY owspd ESET OGIC MST EADY owspd Note: 1. CYD04S72V have 16 address bits, have 17 address bits and have 18 bits. Document #: ev. *I Page 2 of 25

3 Pin Configuration 484-ball BGA Top View CYD04S72V// A NC DQ61 DQ59 DQ57 DQ54 DQ51 DQ48 DQ45 DQ42 DQ39 DQ36 DQ36 DQ39 DQ42 DQ45 DQ48 DQ51 DQ54 DQ57 DQ59 DQ61 NC B C D E F G H J DQ63 DQ62 DQ60 DQ58 DQ55 DQ52 DQ49 DQ46 DQ43 DQ40 DQ37 DQ37 DQ40 DQ43 DQ46 DQ49 DQ52 DQ55 DQ58 DQ60 DQ62 DQ63 DQ65 DQ64 VSS VSS DQ56 DQ53 DQ50 DQ47 DQ44 DQ41 DQ38 DQ38 DQ41 DQ44 DQ47 DQ50 DQ53 DQ56 VSS VSS DQ64 DQ65 DQ67 DQ66 VSS VSS VSS NC [2, 5] NC [2, 5] VSS OWSP D [2,4] DQ69 DQ68 VSS VSS DQ71 DQ70 CE1[8] CE0 [9] A0 A1 ET[2, 3] A2 A3 WP[2,3] BE4 BE5 A4 A5 EADY [2, 5] BE6 VEF [2, 4] POTS TD0 [2,4] NC [2, 5] BUSY [2, 5] CNTINT [10] POTS TD1 [2, 4] VTT VTT VTT VCOE VCOEVCOE VCOE VSS VSS VSS VSS VSS VSS VSS VSS VEF [2, 4] 2. This ball will represent a next generation Dual-Port feature. For more information about this feature, contact Cypress Sales. 3. Connect this ball to. For more information about this next generation Dual-Port feature contact Cypress Sales. 4. Connect this ball to VSS. For more information about this next generation Dual-Port feature, contact Cypress Sales. 5. eave this ball unconnected. For more information about this feature, contact Cypress Sales. 6. eave this ball unconnected for a 64K x 72 configuration. 7. eave this ball unconnected for 128K x 72 and 64K x72 configurations. 8. These balls are not applicable for device. They need to be tied to. 9. These balls are not applicable for device. They need to be tied to VSS. 10. These balls are not applicable for device. They need to be no connected. NC NC [2, 5] NC [2, 5] VSS VSS VSS DQ66 DQ67 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS K A6 A7 NC[2,5] BE7 VTT VCOE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCOE M NC VSS CE0 [9] DQ68 DQ69 CE1 [8] DQ70 DQ71 BE4 ET [2, 3] BE5 WP [ 2,3] A1 A3 A0 A2 BE6 EADY A5 A4 [2, 5] BE7 NC [2,5] A7 A6 A8 A9 C OE VTT VCOE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCOE VTT OE C A9 A8 A10 A11 VSS BE3 VTT VCOE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCOE VTT BE3 VSS A11 A10 N A12 A13 ADS [9] BE2 VCOE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCOE VTT BE2 ADS [9] P T U V W Y A14 A15 CNT/M SK [8] BE1 A16 [6] A18 [2,5] A17 [7] NC CNTEN [9] BE0 DQ35 DQ34 /W EV [2,4] DQ33 DQ32 FTSE [2,3] CNTS T [8] INT VEF [2, 4] NC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQ31 DQ30 VSS MST VSS NC [2, 5] NC [2, 5] EV [2, 4] VSS VSS VSS VSS VSS VSS VSS VSS VEF [2, 4] VCOE VCOEVCOE VCOE VTT VTT VTT POTS TD1 [2, 4] CNTINT [10] BUSY [2, 5] BE1 A13 A12 CNT/M A15 A14 SK [8] BE0 CNTEN [9] INT A17 [7] A16 [6] CNTS T [8] NC A18 [2,5] EV [2, /W DQ34 DQ35 4] TST [2, FTSE 5] [2,3] DQ32 DQ33 NC [2, 5] POTS OWSP VSS NC [2, 5] NC [2, 5] VSS TDI TDO DQ30 DQ31 TD0 D [2,4] [2,4] DQ29 DQ28 VSS VSS DQ20 DQ17 DQ14 DQ11 DQ8 DQ5 DQ2 DQ2 DQ5 DQ8 DQ11 DQ14 DQ17 DQ20 TMS TCK DQ28 DQ29 DQ27 DQ26 DQ24 DQ22 DQ19 DQ16 DQ13 DQ10 DQ7 DQ4 DQ1 DQ1 DQ4 DQ7 DQ10 DQ13 DQ16 DQ19 DQ22 DQ24 DQ26 DQ27 AA AB NC DQ25 DQ23 DQ21 DQ18 DQ15 DQ12 DQ9 DQ6 DQ3 DQ0 DQ0 DQ3 DQ6 DQ9 DQ12 DQ15 DQ18 DQ21 DQ23 DQ25 NC Document #: ev. *I Page 3 of 25

4 Pin Definitions eft Port ight Port Description A 0 A 17 A 0 A 17 Address Inputs. BE 0 BE 7 BE 0 BE 7 Byte Enable Inputs. Asserting these signals enables ead and Write operations to the corresponding bytes of the memory array. [2,5] BUSY [2,5] BUSY Port Busy Output. When the collision is detected, a BUSY is asserted. C C Input Clock Signal. CE0 [9] CE0 [9] Active ow Chip Enable Input. CE1 [8] CE1 [8] Active High Chip Enable Input. DQ 0 DQ 71 DQ 0 DQ 71 Data Bus Input/Output. OE OE Output Enable Input. This asynchronous signal must be asserted OW to enable the DQ data pins during ead operations. INT INT Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The upper two memory locations can be used for message passing. INT is asserted OW when the right port writes to the mailbox location of the left port, and vice versa. An interrupt to a port is deasserted HIGH when it reads the contents of its mailbox. owspd [2,4] owspd [2,4] Port ow Speed Select Input. When operating at less than 100 MHz, the owspd disables the port D. POTSTD[1:0] [2,4] POTSTD[1:0] [2,4] Port Address/Control/Data I/O Standard Select Input. /W /W ead/write Enable Input. Assert this pin OW to write to, or HIGH to ead from the dual-port memory array. [2,5] EADY [2,5] EADY Port eady Output. This signal will be asserted when a port is ready for normal operation. CNT/MSK [8] CNT/MSK [8] Port Counter/Mask Select Input. Counter control input. ADS [9] CNTEN [9] ADS [9] CNTEN [9] Port Counter Address oad Strobe Input. Counter control input. Port Counter Enable Input. Counter control input. CNTST [8] CNTST [8] Port Counter eset Input. Counter control input. CNTINT [10] WP [2,3] ET [2,3] CNTINT [10] WP [2,3] ET [2,3] Port Counter Interrupt Output. This pin is asserted OW when the unmasked portion of the counter is incremented to all 1s. Port Counter Wrap Input. After the burst counter reaches the maximum count, if WP is low, the unmasked counter bits will be set to 0. If high, the counter will be loaded with the value stored in the mirror register. Port Counter etransmit Input. Counter control input. FTSE [2,3] [2,3] FTSE Flow-Through Select. Use this pin to select Flow-Through mode. When is de-asserted, the device is in pipelined mode. VEF [2,4] VEF [2,4] Port External High-Speed IO eference Input. Port IO Power Supply. EV [2,4] EV [2,4] eserved pins for future features. MST TST [2,5] Master eset Input. MST is an asynchronous input signal and affects both ports. A master reset operation is required at power-up. JTAG eset Input. Document #: ev. *I Page 4 of 25

5 Pin Definitions (continued) eft Port ight Port Description TMS TDI TCK TDO V SS V [11] COE V TT JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State machine transitions occur on the rising edge of TCK. JTAG Test Data Input. Data on the TDI input will be shifted serially into selected registers. JTAG Test Clock Input. JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally three-stated except when captured data is shifted out of the JTAG TAP. Ground Inputs. Core Power Supply. VTT Power Supply. Master eset The FEx72 family devices undergo a complete reset by taking the MST input OW. MST input can switch asynchronously to the clocks. MST initializes the internal burst counters to zero, and the counter mask registers to all ones (completely unmasked). MST also forces the mailbox interrupt (INT) flags and the Counter Interrupt (CNTINT) flags HIGH. MST must be performed on the FEx72 family devices after power-up. Mailbox Interrupts The upper two memory locations may be used for message passing and permit communications between ports. Table 2 shows the interrupt operation for both ports using 18 Mbit device as an example. The highest memory location, 3FFFF is the mailbox for the right port and 3FFFE is the mailbox for the left port. Table 2.shows that in order to set the INT flag, a [1, 12, 13, 14] Table 2. Interrupt Operation Example eft Port write operation by the left port to address 3FFFF will assert INT OW. At least one byte has to be active for a write to generate an interrupt. A valid ead of the 3FFFF location by the right port will reset INT HIGH. At least one byte has to be active in order for a read to reset the interrupt. When one port writes to the other port s mailbox, the INT of the port that the mailbox belongs to is asserted OW. The INT is reset when the owner (port) of the mailbox reads the contents of the mailbox. The interrupt flag is set in a flow-thru mode (i.e., it follows the clock edge of the writing port). Also, the flag is reset in a flow-thru mode (i.e., it follows the clock edge of the reading port) Each port can read the other port s mailbox without resetting the interrupt. And each port can write to its own mailbox without setting the interrupt. If an application does not require message passing, INT pins should be left open. ight Port Function /W CE A 0 17 INT /W CE A 0 17 INT Set ight INT Flag 3FFFF X X X X eset ight INT Flag X X X X H 3FFFF H Set eft INT Flag X X X 3FFFE X eset eft INT Flag H 3FFFE H X X X X 11. This family of Dual-Ports does not use V COE, and these pins are internally NC. The next generation Dual-Port family, the FEx72-E, will use V COE of 1.5V or 1.8V. Please contact local Cypress FAE for more information. 12. CE is internal signal. CE = OW if CE 0 = OW and CE 1 = HIGH. For a single ead operation, CE only needs to be asserted once at the rising edge of the CK and can be deasserted after that. Data will be out after the following CK edge and will be three-stated after the next CK edge. 13. OE is Don t Care for mailbox operation. 14. At least one of BE0 or BE7 must be OW. Document #: ev. *I Page 5 of 25

6 Table 3. Address Counter and Counter Mask egister Control Operation (Any Port) [15,16] CK MST CNT/MSK CNTST ADS CNTEN Operation Description X X X X X Master eset eset address counter to all 0s and mask register to all 1s H H X X Counter eset eset counter unmasked portion to all 0s H H H Counter oad oad counter with external address value presented on address lines H H H H Counter eadback ead out counter internal value on address lines H H H H Counter Increment Internally increment address counter value H H H H H Counter Hold Constantly hold the address value for multiple clock cycles H X X Mask eset eset mask register to all 1s H H Mask oad oad mask register with value presented on the address lines H H H Mask eadback ead out mask register value on address lines H H H X eserved Operation undefined Address Counter and Mask egister Operations [17] This section describes the features only apply to 4 Mbit and 9 Mbit devices, not to 18 Mbit device. Each port have a programmable burst address counter. The burst counter contains three registers: a counter register, a mask register, and a mirror register. The counter register contains the address used to access the AM array. It is changed only by the Counter oad, Increment, Counter eset, and by master reset (MST) operations. The mask register value affects the Increment and Counter eset operations by preventing the corresponding bits of the counter register from changing. It also affects the counter interrupt output (CNTINT). The mask register is changed only by the Mask oad and Mask eset operations, and by the MST. The mask register defines the counting range of the counter register. It divides the counter register into two regions: zero or more 0s in the most significant bits define the masked region, one or more 1s in the least significant bits define the unmasked region. Bit 0 may also be 0, masking the least significant counter bit and causing the counter to increment by two instead of one. The mirror register is used to reload the counter register on increment operations (see retransmit, below). It always contains the value last loaded into the counter register, and is changed only by the Counter oad, and Counter eset operations, and by the MST. Table 3 summarizes the operation of these registers and the required input control signals. The MST control signal is asynchronous. All the other control signals in Table 3 (CNT/MSK, CNTST, ADS, CNTEN) are synchronized to the port s CK. All these counter and mask operations are independent of the port s chip enable inputs (CE0 and CE1). Counter enable (CNTEN) inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast, interleaved memory applications. A port s burst counter is loaded when the port s address strobe (ADS) and CNTEN signals are OW. When the port s CNTEN is asserted and the ADS is deasserted, the address counter will increment on each OW to HIGH transition of that port s clock signal. This will ead/write one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array, and will loop back to the start. Counter reset (CNTST) is used to reset the unmasked portion of the burst counter to 0s. A counter-mask register is used to control the counter wrap. Counter eset Operation All unmasked bits of the counter and mirror registers are reset to 0. All masked bits remain unchanged. A Mask eset followed by a Counter eset will reset the counter and mirror registers to 00000, as will master reset (MST). Counter oad Operation The address counter and mirror registers are both loaded with the address value presented at the address lines. 15. X = Don t Care, H = HIGH, = OW. 16. Counter operation and mask register operation is independent of chip enables. 17. The CYD04S72V has 16 address bits and a maximum address value of FFFF. The has 17 address bits and a maximum address value of 1FFFF. The has 18 address bits and a maximum address value of 3FFFF. Document #: ev. *I Page 6 of 25

7 Counter Increment Operation Once the address counter register is initially loaded with an external address, the counter can internally increment the address value, potentially addressing the entire memory array. Only the unmasked bits of the counter register are incremented. The corresponding bit in the mask register must be a 1 for a counter bit to change. The counter register is incremented by 1 if the least significant bit is unmasked, and by 2 if it is masked. If all unmasked bits are 1, the next increment will wrap the counter back to the initially loaded value. If an Increment results in all the unmasked bits of the counter being 1s, a counter interrupt flag (CNTINT) is asserted. The next Increment will return the counter register to its initial value, which was stored in the mirror register. The counter address can instead be forced to loop to by externally connecting CNTINT to CNTST. [18] An increment that results in one or more of the unmasked bits of the counter being 0 will de-assert the counter interrupt flag. The example in Figure 2 shows the counter mask register loaded with a mask value of 0003Fh unmasking the first 6 bits with bit 0 as the SB and bit 16 as the MSB. The maximum value the mask register can be loaded with is 1FFFFh. Setting the mask register to this value allows the counter to access the entire memory space. The address counter is then loaded with an initial value of 8h. The base address bits (in this case, the 6th address through the 16th address) are loaded with an address value but do not increment once the counter is configured for increment operation. The counter address will start at address 8h. The counter will increment its internal address value till it reaches the mask register value of 3Fh. The counter wraps around the memory block to location 8h at the next count. CNTINT is issued when the counter reaches its maximum value. Counter Hold Operation The value of all three registers can be constantly maintained unchanged for an unlimited number of clock cycles. Such operation is useful in applications where wait states are needed, or when address is available a few cycles ahead of data in a shared bus interface. Counter Interrupt The counter interrupt (CNTINT) is asserted OW when an increment operation results in the unmasked portion of the counter register being all 1s. It is deasserted HIGH when an Increment operation results in any other value. It is also de-asserted by Counter eset, Counter oad, Mask eset and Mask oad operations, and by MST. Counter eadback Operation The internal value of the counter register can be read out on the address lines. eadback is pipelined; the address will be valid t CA2 after the next rising edge of the port s clock. If address readback occurs while the port is enabled (CE0 OW and CE1 HIGH), the data lines (DQs) will be three-stated. Figure 1 shows a block diagram of the operation. etransmit etransmit is a feature that allows the ead of a block of memory more than once without the need to reload the initial address. This eliminates the need for external logic to store and route data. It also reduces the complexity of the system design and saves board space. An internal mirror register is used to store the initially loaded address counter value. When the counter unmasked portion reaches its maximum value set by the mask register, it wraps back to the initial value stored in this mirror register. If the counter is continuously configured in increment mode, it increments again to its maximum value and wraps back to the value initially stored into the mirror register. Thus, the repeated access of the same data is allowed without the need for any external logic. Mask eset Operation The mask register is reset to all 1s, which unmasks every bit of the counter. Master reset (MST) also resets the mask register to all 1s. Mask oad Operation The mask register is loaded with the address value presented at the address lines. Not all values permit correct increment operations. Permitted values are of the form 2 n 1 or 2 n 2. From the most significant bit to the least significant bit, permitted values have zero or more 0s, one or more 1s, or one 0. Thus 1FFFF, 003FE, and are permitted values, but 1F0FF, 003FC, and are not. Mask eadback Operation The internal value of the mask register can be read out on the address lines. eadback is pipelined; the address will be valid t CM2 after the next rising edge of the port s clock. If mask readback occurs while the port is enabled (CE0 OW and CE1 HIGH), the data lines (DQs) will be three-stated. Figure 1 shows a block diagram of the operation. Counting by Two When the least significant bit of the mask register is 0, the counter increments by two. This may be used to connect the x72 devices as a 144-bit single porm in which the counter of one port counts even addresses and the counter of the other port counts odd addresses. This even-odd address scheme stores one half of the 144-bit data in even memory locations, and the other half in odd memory locations. Note: 18. CNTINT and CNTST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together. Document #: ev. *I Page 7 of 25

8 CNT/MSK CNTEN ADS CNTST Decode ogic MST Bidirectional Address ines Mask egister Counter/ Address egister Address Decode AM Array CK From Address ines From Mask egister Mirror Increment ogic Wrap oad/increment Counter 17 To eadback and Address Decode From Mask From Counter Bit Wrap Detect Wrap To Counter Figure 1. Counter, Mask, and Mirror ogic Block Diagram [1] Document #: ev. *I Page 8 of 25

9 Example: oad Counter-Mask egister = 3F CNTINT H 0 0 0s Masked Address Unmasked Address Mask egister bit-0 oad Address Counter = 8 H X X Xs X Max Address egister X X Xs X Address Counter bit Max + 1 Address egister H X X Xs X Figure 2. Programmable Counter-Mask egister Operation [1, 19] IEEE Serial Boundary Scan (JTAG) [20] The FEx72 incorporates an IEEE serial boundary scan test access port (TAP). The TAP controller functions in a manner that does not conflict with the operation of other devices using compliant TAPs. The TAP operates using JEDEC-standard 3.3V I/O logic levels. It is composed of three input connections and one output connection required by the test logic defined by the standard. Performing a TAP eset A reset is performed by forcing TMS HIGH (V DD ) for five rising edges of TCK. This reset does not affect the operation of the FEx72 family and may be performed while the device is operating. An MST must be performed on the FEx72 after power-up. Performing a Pause/estart When a SHIFT-D PAUSE-D SHIFT-D is performed the scan chain will output the next bit in the chain twice. For example, if the value expected from the chain is , the device will output a This extra bit will cause some testers to report an erroneous failure for the FEx72 in a scan test. Therefore the tester should be configured to never enter the PAUSE-D state. Boundary Scan Hierarchy for FEx72 Family Internally, the CYD04S72V and have two DIEs while have four DIEs. Each DIE contains all the circuitry required to support boundary scan testing. The circuitry includes the TAP, TAP controller, instruction register, and data registers. The circuity and operation of the DIE boundary scan are described in detail below. The scan chain of each DIE is connected serially to form the scan chain of the FEx72 family as shown in Figure 3. TMS and TCK are connected in parallel to each DIE to drive all 4 TAP controllers in unison. In many cases, each DIE will be supplied with the same instruction. In other cases, it might be useful to supply different instructions to each DIE. One example would be testing the device ID of one DIE while bypassing the others. Each pin of FEx72 family is typically connected to multiple DIEs. For connectivity testing with the EXTEST instruction, it is desirable to check the internal connections between DIEs as well as the external connections to the package. This can be accomplished by merging the netlist of the devices with the netlist of the user s circuit board. To facilitate boundary scan testing of the devices, Cypress provides the BSD file for each DIE, the internal netlist of the device, and a description of the device scan chain. The user can use these materials to easily integrate the devices into the board s boundary scan environment. Further information can be found in the Cypress application note Using JTAG Boundary Scan For System In a Package (SIP) Dual-PorMs. 19. The X in this diagram represents the counter upper bits. 20. Boundary scan is IEEE compatible. See Performing a Pause/estart for deviation from strict compliance. Document #: ev. *I Page 9 of 25

10 18 Mbit 4 Mbit/9 Mbit TDO TDO D2 TDI TDO D4 TDI TDO D2 TDI TDO TDO D1 TDI TDO D3 TDI TDO D1 TDI TDI Figure 3. Scan Chain TDI Table 4. Identification egister Definitions Instruction Field Value Description evision Number(31:28) 0h eserved for version number Cypress Device(27:12) C002h Defines Cypress DIE number for and C001h Defines Cypress DIE number for CYD04S72V Cypress JDEC ID(11:1) 034h Allows unique identification of FEx72 family device vendor ID egister Presence (0) 1 Indicates the presence of an ID register Table 5. Scan egisters Sizes egister Name Bit Size Instruction 4 Bypass 1 Identification 32 Boundary Scan n [21] Table 6. Instruction Identification Codes Instruction Code Description EXTEST 0000 Captures the Input/Output ring contents. Places the BS between the TDI and TDO BYPASS 1111 Places the BY between TDI and TDO IDCODE 1011 oads the ID with the vendor ID code and places the register between TDI and TDO HIGHZ 0111 Places BY between TDI and TDO. Forces all FEx72 output drivers to a High-Z state CAMP 0100 Controls boundary to 1/0. Places BY between TDI and TDO SAMPE/PEOAD 1000 Captures the input/output ring contents. Places BS between TDI and TDO NBSST 1100 esets the non-boundary scan logic. Places BY between TDI and TDO ESEVED All other codes Other combinations are reserved. Do not use other than the above Note: 21. See details in the device BSD files. Document #: ev. *I Page 10 of 25

11 Maximum atings [22] (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature C to C Ambient Temperature with Power Applied C to C Supply Voltage to Ground Potential V to + 4.6V DC Voltage Applied to Outputs in High-Z State V to V DD + 0.5V DC Input Voltage V to V DD + 0.5V [23] Output Current into Outputs (OW) ma Static Discharge Voltage... > 2000V (JEDEC JESD22-A B) atch-up Current... > 200 ma Operating ange ange Ambient Temperature V DD V COE [11] Commercial 0 C to +70 C 3.3V ± 165 mv 1.8V ± 100 mv Industrial 40 C to +85 C 3.3V ± 165 mv 1.8V ± 100mV Electrical Characteristics Over the Operating ange Parameter Description Part No. Min. Typ Max Min. Typ Max Min. Typ Max Unit V OH Output HIGH Voltage (V DD = Min., I OH = V 4.0 ma) V O Output OW Voltage (V DD = Min., I O = V ma) V IH Input HIGH Voltage V V I Input OW Voltage V I OZ Output eakage Current µa I IX1 Input eakage Current Except TDI, TMS, µa MST I IX2 Input eakage Current TDI, TMS, MST ma I CC Operating Current CYD04S72V ma (V DD = Max.,I OUT = 0 ma), Outputs Disabled ma I SB1 Standby Current CYD04S72V ma (Both Ports TT evel) CE and CE V IH, f = f MAX I SB2 Standby Current CYD04S72V ma (One Port TT evel) CE CE V IH, f = f MAX I SB3 Standby Current (Both CYD04S72V ma Ports CMOS evel) CE and CE V DD 0.2V, f = 0 I SB4 I SB5 I COE [11] Standby Current (One Port CMOS evel) CE CE V IH, f = f MAX Operating Current ( = Max, Iout = 0 ma, f = 0) Outputs Disabled Core Operating Current for (V DD = Max., I OUT = 0 ma), Outputs Disabled 22. The voltage on any input or I/O pin can not exceed the power pin during power-up. 23. Pulse width < 20 ns. CYD04S72V ma ma ma Document #: ev. *I Page 11 of 25

12 Capacitance [24] Part# Parameter Description Test Conditions Max Unit CYD04S72V C IN Input Capacitance T A = 25 C, f = 1 MHz, 20 pf C OUT Output Capacitance V DD = 3.3V 10 [25] pf C IN Input Capacitance 40 pf C OUT Output Capacitance 20 pf AC Test oad and Waveforms OUTPUT Z 0 = 50Ω = 50Ω 3.3V 1 = 590Ω C = 10 pf V TH = 1.5V OUTPUT C = 5 pf 2 = 435Ω (a) Normal oad (oad 1) 3.0V A INPUT PUSES Vss <2ns 10% 90% (b) Three-state Delay (oad 2) 90% 10% <2ns Switching Characteristics Over the Operating ange CYD04S72V CYD04S72V Parameter Description Min. Max Min. Max Min. Max Min. Max Unit f MAX2 Maximum Operating Frequency MHz t CYC2 Clock Cycle Time ns t CH2 Clock HIGH Time ns t C2 Clock OW Time ns [26] t Clock ise Time ns t [26] F Clock Fall Time ns Address Set-up Time ns Address Hold Time ns t SB Byte Select Set-up Time ns t HB Byte Select Hold Time ns t SC Chip Enable Set-up Time NA NA ns t HC Chip Enable Hold Time NA NA ns t SW /W Set-up Time ns t HW /W Hold Time ns t SD Input Data Set-up Time ns t HD Input Data Hold Time ns D ADS Set-up Time NA NA ns 24. C OUT also references C I/O. 25. Except INT and CNTINT which are 20 pf. 26. Except JTAG signal (t and t F < 10 ns max). Document #: ev. *I Page 12 of 25

13 Switching Characteristics Over the Operating ange (continued) Parameter Description Min. Max Min. Max Min. Max Min. Max Unit D ADS Hold Time NA NA ns t SCN CNTEN Set-up Time NA NA ns t HCN CNTEN Hold Time NA NA ns t SST CNTST Set-up Time NA NA ns t HST CNTST Hold Time NA NA ns t SCM CNT/MSK Set-up Time NA NA ns t HCM CNT/MSK Hold Time NA NA ns t OE Output Enable to Data Valid ns t [27, 28] OZ OE to ow Z ns [27, 28] t OHZ OE to High Z ns t CD2 Clock to Data Valid ns t CA2 Clock to Counter Address Valid NA NA ns t CM2 Clock to Mask egister eadback Valid NA NA ns t DC Data Output Hold After Clock HIGH ns [27, 28] t CKHZ Clock HIGH to Output High Z ns [27, 28] t CKZ Clock HIGH to Output ow Z ns t SINT Clock to INT Set Time ns t INT Clock to INT eset Time ns t SCINT Clock to CNTINT Set Time NA NA NA NA ns t CINT Clock to CNTINT eset time NA NA NA NA ns Port to Port Delays t CCS Clock to Clock Skew ns Master eset Timing t S Master eset Pulse Width cycles t SS Master eset Set-up Time ns t S Master eset ecovery Time cycles t SF Master eset to Outputs Inactive ns t SCNTINT Master eset to Counter Interrupt Flag eset Time NA NA ns 27. This parameter is guaranteed by design, but is not production tested. 28. Test conditions used are oad CYD04S72V CYD04S72V Document #: ev. *I Page 13 of 25

14 JTAG Timing Characteristics CYD04S72V 167/ 133/ 100 Parameter Description Min. Max Unit f JTAG Maximum JTAG TAP Controller Frequency 10 MHz t TCYC TCK Clock Cycle Time 100 ns t TH TCK Clock HIGH Time 40 ns t T TCK Clock OW Time 40 ns t TMSS TMS Set-up to TCK Clock ise 10 ns t TMSH TMS Hold After TCK Clock ise 10 ns t TDIS TDI Set-up to TCK Clock ise 10 ns t TDIH TDI Hold After TCK Clock ise 10 ns t TDOV TCK Clock OW to TDO Valid 30 ns t TDOX TCK Clock OW to TDO Invalid 0 ns Switching Waveforms t TH t T Test Clock TCK Test Mode Select TMS t TMSS t TMSH t TCYC t TDIS t TDIH Test Data-In TDI Test Data-Out TDO t TDOX t TDOV Document #: ev. *I Page 14 of 25

15 Switching Waveforms (continued) Master eset MST t S A ADDESS/ DATA INES A OTHE INPUTS t SF t SS t S INACTIVE ACTIVE TMS CNTINT INT TDO [12, 29, 30, 31, 32] ead Cycle CK t CH2 t CYC2 t C2 CE t SC t HC t SC t HC t SB thb BE0 BE7 /W t SW t HW ADDESS A n A n+1 A n+2 A n+3 DATA OUT 1 atency t CD2 t DC Q n Q n+1 Q n+2 t OHZ t CKZ t OZ OE t OE 29. OE is asynchronously controlled; all other inputs (excluding MST and JTAG) are synchronous to the rising clock edge. 30. ADS = CNTEN = OW, and MST = CNTST = CNT/MSK = HIGH. 31. The output is disabled (high-impedance state) by CE = V IH following the next rising edge of the clock. 32. Addresses do not have to be accessed sequentially since ADS = CNTEN = V I with CNT/MSK = V IH constantly loads the address on the rising edge of the CK. Numbers are for reference only. Document #: ev. *I Page 15 of 25

16 Switching Waveforms (continued) Bank Select ead [33, 34] CK t CH2 t CYC2 t C2 ADDESS (B1) A 0 A 1 A 2 A 3 A 4 A 5 t SC t HC CE (B1) t CD2 t SC t HC t CD2 t CKHZ t CD2 t CKHZ DATA OUT(B1) Q 0 Q 1 Q 3 t DC t DC t CKZ ADDESS (B2) A 0 A 1 A 2 A 3 A 4 A 5 t SC t HC CE (B2) t SC t HC t CD2 t CKHZ t CD2 DATA OUT(B2) Q 2 Q 4 t CKZ t CKZ ead-to-write-to-ead (OE = OW) [32, 35, 36, 37, 38] CK t CH2 t CYC2 t C2 CE t SC t HC t SW t HW /W t SW t HW ADDESS A n A n+1 A n+2 A n+2 t SD A n+2 A n+3 t HD DATA IN t CD2 t DC t CKHZ D n+2 DATA OUT Q n EAD NO OPEATION WITE 33. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress FEx72 device from this data sheet. ADDESS (B1) = ADDESS (B2). 34. ADS = CNTEN = BE0 BE7 = OE = OW; MST = CNTST = CNT/MSK = HIGH. 35. Output state (HIGH, OW, or high-impedance) is determined by the previous cycle control signals. 36. During No Operation, data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. 37. CE 0 = OE = BE0 BE7 = OW; CE 1 = /W = CNTST = MST = HIGH. 38. CE 0 = BE0 BE7 = /W = OW; CE 1 = CNTST = MST = CNT/MSK = HIGH. When /W first switches low, since OE = OW, the Write operation cannot be completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CK. Document #: ev. *I Page 16 of 25

17 Switching Waveforms (continued) ead-to-write-to-ead (OE Controlled) [32, 35, 37, 38] t CH2 t CYC2tC2 CK CE t SC t HC t SW t HW /W t SW t HW ADDESS A n A n+1 A n+2 A n+3 A n+4 A n+5 t SD t HD DATA IN D n+2 D n+3 t CD2 t CD2 DATA OUT Q n t OHZ Q n+4 OE EAD WITE EAD ead with Address Counter Advance [37] CK t CH2 t CYC2 t C2 ADDESS A n D D ADS D D CNTEN t SCN t HCN t CD2 t SCN t HCN DATA OUT Q x 1 Q x Q n Q n+1 Q n+2 Q n+3 EAD EXTENA ADDESS t DC EAD WITH COUNTE COUNTE HOD EAD WITH COUNTE Document #: ev. *I Page 17 of 25

18 Switching Waveforms (continued) Write with Address Counter Advance [38] CK t CH2 t CYC2 t C2 ADDESS A n INTENA ADDESS A n A n+1 A n+2 A n+3 A n+4 D D ADS CNTEN t SCN t HCN DATA IN D n D n+1 D n+1 D n+2 D n+3 D n+4 t SD t HD WITE EXTENA ADDESS WITE WITH COUNTE WITE COUNTE HOD WITE WITH COUNTE Document #: ev. *I Page 18 of 25

19 Switching Waveforms (continued) Counter eset [39, 40] CK t CYC2 t CH2 t C2 ADDESS A n A m A p INTENA ADDESS A x 0 1 A n A m A p t SW t HW /W ADS CNTEN CNTST t SST t HST t SD t HD DATA IN D 0 t CD2 t CD2 [52] DATA OUT Q 0 Q 1 Q n t CKZ COUNTE WITE EAD EAD EAD ESET ADDESS 0 ADDESS 0 ADDESS 1 ADDESS A n 39. CE 0 = BE0 BE7 = OW; CE 1 = MST = CNT/MSK = HIGH. 40. No dead cycle exists during counter reset. A ead or Write cycle may be coincidental with the counter reset. EAD ADDESS A m Document #: ev. *I Page 19 of 25

20 Switching Waveforms (continued) eadback State of Address Counter or Mask egister [41, 42, 43, 44] t CYC2 t CH2 t C2 CK t CA2 or t CM2 EXTENA ADDESS A n A n* A 0 A 17 INTENA ADDESS A n A n+1 A n+2 A n+3 A n+4 D D ADS t SCN t HCN CNTEN t CD2 t CKHZ t CKZ DATA OUT Q x-2 Q x-1 Q n Q n+1 Q n+2 Q n+3 OAD EADBACK INCEMENT EXTENA COUNTE ADDESS INTENA ADDESS 41. CE 0 = OE = BE0 BE7 = OW; CE 1 = /W = CNTST = MST = HIGH. 42. Address in output mode. Host must not be driving address bus after t CKZ in next clock cycle. 43. Address in input mode. Host can drive address bus after t CKHZ. 44. An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being ead out on the address lines. Document #: ev. *I Page 20 of 25

21 Switching Waveforms (continued) eft_port (_Port) Write to ight_port (_Port) ead [45, 46, 47] CK t CH2 t CYC2 t C2 _POT ADDESS A n t SW t HW /W _POT DATA IN t CKHZ t SD D n t HD t CKZ CK t CH2 t CYC2 t C2 t CCS _POT ADDESS A n /W t CD2 _POT DATA OUT Q n t DC 45. CE 0 = OE = ADS = CNTEN = BE0 BE7 = OW; CE 1 = CNTST = MST = CNT/MSK = HIGH. 46. This timing is valid when one port is writing, and other port is reading the same location at the same time. If t CCS is violated, indeterminate data will be ead out. 47. If t CCS < minimum specified value, then _Port will ead the most recent data (written by _Port) only (2 * t CYC2 + t CD2 ) after the rising edge of _Port's clock. If t CCS > minimum specified value, then _Port will ead the most recent data (written by _Port) (t CYC2 + t CD2 ) after the rising edge of _Port's clock. Document #: ev. *I Page 21 of 25

22 Switching Waveforms (continued) Counter Interrupt and etransmit [48, 49, 50, 51, 52] CK t CH2 t CYC2 t C2 t SCM t HCM CNT/MSK ADS CNTEN COUNTE INTENA ADDESS 1FFFC 1FFFD 1FFFE 1FFFF ast_oaded ast_oaded +1 t SCINT t CINT CNTINT [53, 54, 55, 56, 57] Mailbox Interrupt Timing t CYC2 t CH2 t C2 CK _POT ADDESS 3FFFF A n A n+1 A n+2 A n+3 t SINT INT t INT t CH2 t CYC2 t C2 CK _POT ADDESS A m A m+1 3FFFF A m+3 A m CE 0 = OE = BE0 BE7 = OW; CE 1 = /W = CNTST = MST = HIGH. 49. CNTINT is always driven. 50. CNTINT goes OW when the unmasked portion of the address counter is incremented to the maximum value. 51. The mask register assumed to have the value of 1FFFFh. 52. etransmit happens if the counter remains in increment mode after it wraps to initially loaded value. 53. CE 0 = OE = ADS = CNTEN = OW; CE 1 = CNTST = MST = CNT/MSK = HIGH. 54. Address 1FFFF is the mailbox location for _Port. 55. _Port is configured for Write operation, and _Port is configured for ead operation. 56. At least one byte enable (B0 B3) is required to be active during interrupt operations. 57. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the ead clock. Document #: ev. *I Page 22 of 25

23 Table 7. ead/write and Enable Operation (Any Port) [1, 15, 58, 59, 60] Inputs Outputs OE CK CE 0 CE 1 /W DQ 0 DQ 71 Operation X H X X High-Z Deselected X X X High-Z Deselected X H D IN Write H H D OUT ead H X H X High-Z Outputs Disabled Ordering Information 256K 72 (18-Mbit) 3.3V Synchronous Dual-PorM Speed (MHz) Ordering Code Package Name Package Type Operating ange BBC BB ball Grid Array Commercial -133BBXC BB ball Pb-Free Ball Grid Array Commercial -133BBI BB ball Grid Array Industrial BBC BB ball Grid Array Commercial -100BBXC BB ball Pb-Free Ball Grid Array Commercial -100BBI BB ball Grid Array Industrial -100BBXI BB ball Pb-Free Ball Grid Array Industrial 128K 72 (9-Mbit) 3.3V Synchronous Dual-PorM BBC BB ball Grid Array Commercial BBC BB ball Grid Array Commercial -133BBI BB ball Grid Array Industrial 64K x 72 (4-Mbit) 3.3 Synchronous CYD04S72V Dual-PorM 167 CYD04S72V-167BBC BB ball Grid Array Commercial 133 CYD04S72V-133BBC BB ball Grid Array Commercial CYD04S72V-133BBI BB ball Grid Array Industrial 58. OE is an asynchronous input signal. 59. When CE changes state, deselection and ead happen after one cycle of latency. 60. CE 0 = OE = OW; CE 1 = /W = HIGH. Document #: ev. *I Page 23 of 25

24 Package Diagram 484-ball FBGA (23 mm x 23 mm x 1.6 mm) BB *E FEx72 and FEx72-E are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: ev. *I Page 24 of 25 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

25 Document History Page Document Title: FEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port AM Document Number: Orig. of EV. ECN NO. Issue Date Change Description of Change ** /17/03 SPN New Data Sheet *A /01/03 SPN Added -133 speed bin Updated spec values for I CC,, t HB, t HW, t HD Added new parameter I CC1 Added bank select read and read to write to read (OE=low) timing diagrams *B /18/03 SPN Updated spec values for t OE, t OHZ, t CH2, t C2,, t HB, t HW, t HD, I CC, I SB5,, t SB, t SW, t SD, t CD2 Updated read to write (OE=low) timing diagram Updated Master eset values for t S, t S, t SF Updated pinout Updated V COE voltage range *C /30/03 SPN Updated package diagram Updated t CD2 value on first page emoved Preliminary status *D See ECN WWZ Added 4 Mbit and 9 Mbit x72 devices into the data sheet with updated pinout, pin description table, power table, and timing table Changed title Added Preliminary status to reflect the addition of 4 Mbit and 9 Mbit devices emoved FEx72-E from the document Added counter related functions for 4 Mbit and 9 Mbit emoved standard JTAG description Updated block diagram Updated pinout with FTSE and one more POTSTD pins per port Updated tsf of value *E See ECN WWZ Change pinout D15 from EV[2,4] to VSS to reflect SC pin removal *F See ECN AEQ Changed pinout K3 from NC to NC[2,5] Changed pinout K20 from NC to NC[2,5] Changed pinout D15 from VSS to NC Changed pinout D8 and M3 from EV[2,4] to VSS Changed pinout M20 and W15 from EV[2,4] to VSS *G See ECN PCX VEF Pin Definition Updated Added Pb-Free Part Ordering Informations *H See ECN YDT Added note for V COE Changed notes for POTSTD to VSS Changed ICC, ISB1, ISB2 and ISB4 number for per PE request *I See ECN YDT Changed CYDxxS72AV to CYDxxS72V (rev. A not implemented) Document #: ev. *I Page 25 of 25