XC95288 In-System Programmable CPLD

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1 0 XC95288 In-System Programmable CPLD DS069 (v4.1) August 21, Product Specification Features 15 ns pin-to-pin logic delays on all pins f CNT to 95 MHz 288 macrocells with 6,400 usable gates Up to 166 user pins 5V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Block - 90 product terms drive any or all of 18 macrocells within Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 24 ma outputs 3.3V or 5V capability Advanced CMOS 5V Fast FLASH technology Supports parallel programming of more than one XC9500 concurrently Available 352-pin BGA and 208-pin HQFP packages Description The XC95288 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of eight 36V18 Blocks, providing 6,400 usable gates with propagation delays of 15 ns. See Figure 2 for the architecture overview. Power Management Power dissipation can be reduced in the XC95288 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for specific operating conditions using the following equation: I CC (ma) = MC HP (1.7) + MC LP (0.9) + MC (0.006 ma/mhz) f Where: MC HP = Macrocells in high-performance mode MC LP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) Figure 1 shows a typical calculation for the XC95288 device. Typical I CC (ma) (500) 300 High Performance Low Power (700) (500) 0 50 Clock Frequency (MHz) 100 DS069_01_ Figure 1: Typical I CC vs. Frequency for XC Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS069 (v4.1) August 21,

2 XC95288 In-System Programmable CPLD JTAG Port 1 3 JTAG Controller In-System Programming Controller Block 1 Macrocells 1 to 18 /GCK /GS /GTS Blocks Fast CONNECT II Switch Matrix Block 2 Macrocells 1 to 18 Block 3 Macrocells 1 to 18 Block 4 Macrocells 1 to Block 16 Macrocells 1 to 18 DS069_02_ Figure 2: XC95288 Architecture block outputs (indicated by the bold line) drive the blocks directly. 2 DS069 (v4.1) August 21, Product Specification

3 XC95288 In-System Programmable CPLD Absolute Maximum atings Symbol Description Value Units V CC Supply voltage relative to GND 0.5 to 7.0 V V IN Input voltage relative to GND 0.5 to V CC V V TS Voltage applied to 3-state output 0.5 to V CC V T STG Storage temperature (ambient) 65 to +150 o C T J Junction temperature +150 o C 1. Stresses beyond those listed under Absolute Maximum atings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum atings conditions for extended periods of time may affect device reliability. ecommended Operation Conditions Symbol Parameter Min Max Units V CCINT V CCIO Supply voltage for internal logic and input buffers Supply voltage for output drivers for 5V operation Commercial T A = 0 o C to 70 o C V Industrial T A = 40 o C to +85 o C Commercial T A = 0 o C to 70 o C V Industrial T A = 40 o C to +85 o C Supply voltage for output drivers for 3.3V operation V IL Low-level input voltage V V IH High-level input voltage 2.0 V CCINT V V O Output voltage 0 V CCIO V Quality and eliability Characteristics Symbol Parameter Min Max Units T D Data etention 20 - Years N PE Program/Erase Cycles (Endurance) 10,000 - Cycles DC Characteristic Over ecommended Operating Conditions Symbol Parameter Test Conditions Min Max Units V OH Output high voltage for 5V outputs I OH = 4.0 ma, V CC = Min V Output high voltage for 3.3V outputs I OH = 3.2 ma, V CC = Min V V OL Output low voltage for 5V outputs I OL = 24 ma, V CC = Min V Output low voltage for 3.3V outputs I OL = 10 ma, V CC = Min V I IL Input leakage current V CC = Max - ±10 µa V IN = GND or V CC I IH high-z leakage current V CC = Max - ±10 µa V IN = GND or V CC C IN capacitance V IN = GND f = 1.0 MHz - 10 pf I CC Operating supply current (low power mode, active) V I = GND, No load f = 1.0 MHz 300 (Typical) ma DS069 (v4.1) August 21,

4 XC95288 In-System Programmable CPLD AC Characteristics XC XC Symbol Parameter Min Max Min Max Units T PD to output valid ns T SU setup time before GCK ns T H hold time after GCK ns T CO GCK to output valid ns f (1) CNT 16-bit counter frequency MHz f (2) SYSTEM Multiple FB internal operating frequency MHz T PSU setup time before p-term clock input ns T PH hold time after p-term clock input ns T PCO P-term clock output valid ns T OE GTS to output valid ns T OD GTS to output disable ns T POE Product term OE to output enabled ns T POD Product term OE to output disabled ns T WLH GCK pulse width (High or Low) ns 1. f CNT is the fastest 16-bit counter frequency available, using the local feedback when applicable. f CNT is also the Export Control Maximum flip-flop toggle rate, f TOG. 2. f SYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs. V TEST Device Output 1 2 C L Output Type V CCIO 5.0V 3.3V V TEST 5.0V 3.3V 1 160Ω 260Ω 2 120Ω 360Ω C L 35 pf 35 pf DS067_03_ Figure 3: AC Load Circuit 4 DS069 (v4.1) August 21, Product Specification

5 XC95288 In-System Programmable CPLD Internal Timing Parameters Symbol Buffer Delays Parameter XC XC Min Max Min Max T IN Input buffer delay ns T GCK GCK buffer delay ns T GS GS buffer delay ns T GTS GTS buffer delay ns T OUT Output buffer delay ns T EN Output buffer enable/disable delay ns Product Term Control Delays T PTCK Product term clock delay ns T PTS Product term set/reset delay ns T PTTS Product term 3-state delay ns Internal egister and Combinatorial Delays T PDI Combinatorial logic propagation delay ns T SUI egister setup time ns T HI egister hold time ns T COI egister clock to output valid time ns T AOI egister async. S/ to output delay ns T AI egister async. S/ recover before clock ns T LOGI Internal logic delay ns T LOGILP Internal low power logic delay ns Feedback Delays T F Fast CONNECT II feedback delay ns T LF block local feedback delay ns Time Adders T PTA (1) Incremental product term allocator delay ns T SLEW Slew-rate limited delay ns 1. T PTA is multiplied by the span of the function as defined in the XC9500 family data sheet. Units DS069 (v4.1) August 21,

6 XC95288 In-System Programmable CPLD XC95288 Pins N U P U P Y P W AA Y [1] Y24 [1] 726 [1] AA T AB T [1] 46 [1] AA24 [1] T Y V AC K [1] 3 [1] E23 [1] K C J [1] 5 [1] E24 [1] L F K [1] 7 [1] E25 [1] L D L G M F M [1] 9 [1] F26 [1] M H M G N H Global control pin. 6 DS069 (v4.1) August 21, Product Specification

7 XC95288 In-System Programmable CPLD XC95288 Pins (Continued) AA AC AB AD AD AE AE AC [1] 55 [1] AD23 [1] AD AC AE AF AD AD AE AE AF AE AE AE AE AF AF C A D B A C B D C A B B B C C B D C B B [1] 206 [1] C23 [1] A D B Global control pin. DS069 (v4.1) August 21,

8 XC95288 In-System Programmable CPLD XC95288 Pins (Continued) AE AD AF AC AE AF AC AE AD AD AF AE AE AD AD AE AC AC AF AE AE AD AE AC C B B A A D D C B B A A C B B A A D A B B A C D DS069 (v4.1) August 21, Product Specification

9 XC95288 In-System Programmable CPLD XC95288 Pins (Continued) AD V AD W AC U AD U AA V AA V AB U AC T AA AA Y V K P G N H N H N J M F M G M G M F L E L D L F J DS069 (v4.1) August 21,

10 XC95288 In-System Programmable CPLD XC95288 Global, JTAG, and Power Pins Pin Type HQ208 BG352 /GCK1 44 Y24 /GCK2 46 AA24 /GCK3 55 AD23 /GTS1 7 E25 /GTS2 9 F26 /GTS3 3 E23 /GTS4 5 E24 /GS 206 C23 TCK 98 AD6 TDI 94 AF6 TDO 176 D12 TMS 96 AE6 V CCINT 5V 11, 59, 124, 153, 204 J23, V24, AF23, AC15, AF15, AD11, AD5, Y3, T1, J3, G4, D5, D10, B13, D17, C22, H24 V CCIO 3.3V/5V 1, 26, 53, 65, 79, 92, 105, 132, 157, 172, 181, 184 GND 2, 13, 24, 27, 42, 52, 68, 81, 93, 104,1 08, 129, 130, 141, 156, 163, 177, 190, 207 A10, A17, B2, B25, D7, D13, D19, G23, H4, K1, K26, N23, P4, U1, U26, W23, Y4, AC8, AC14, AC20, AE25, AF10, AF17 A1, A2, A5, A8, A14, A19, A22, A25, A26, B1, B26, C7, C9, C13, C18, D24, E1, E26, H1, H26, K4, N1, N24, P3, P26, V23, W1, W4, W26, AB1, AB4, AB26, AC9, AD10, AD14, AD15, AD20, AE1, AE26, AF1, AF2, AF5, AF8, AF13, AF19, AF22, AF25, AF26 No Connects - A18, A23, A24, B4, B8, B10, B23, C1, C2, C3, C4, C5, C8, C11, C24, C25, D1, D3, D4, D14, D16, D21, D23, D25, E3, E4, F3, F23, G25, J2, J24, J26, K2, L4, L23, P2, T3, T4, T24, U25, V25, W3, W24, Y2, AB3, AB23, AC2, AC4, AC6, AC11, AC16, AC17, AC21, AC23, AC24, AC25, AD16, AD21, AD24, AD26, AE2, AE4, AE10, AE15, AF3, AF4, AF9, AF DS069 (v4.1) August 21, Product Specification

11 XC95288 In-System Programmable CPLD Device Part Marking and ing Combination Information Device Type Package Speed Operating ange XC95xxx TQ144 7C This line not related to device part number 1 Sample package with part marking. Device ing and Part Marking Number Speed (pin-to-pin delay) Pkg. Symbol No. of Pins Operating ange (1) Package Type XC HQ208C 10 ns HQ pin Heat Sink Quad Flat Pack (HQFP) C XC BG352C 10 ns BG ball Ball Grid Array (BGA) C XC HQ208C 15 ns HQ pin Heat Sink Quad Flat Pack (HQFP) C XC BG352C 15 ns BG ball Ball Grid Array (BGA) C XC HQ208I 15 ns HQ pin Heat Sink Quad Flat Pack (HQFP) I XC BG352I 15 ns BG ball Ball Grid Array (BGA) I XC HQ208C 20 ns HQ pin Heat Sink Quad Flat Pack (HQFP) C XC BG352C 20 ns BG ball Ball Grid Array (BGA) C XC HQ208I 20 ns HQ pin Heat Sink Quad Flat Pack (HQFP) I XC BG352I 20 ns BG ball Ball Grid Array (BGA) I 1. C = Commercial: T A = 0 to +70 C; I = Industrial: T A = 40 to +85 C evision History The following table shows the revision history for this document. Date Version evision 12/04/ Update AC characteristics and internal parameters. 06/18/ Updated format. 08/21/ Updated Package Device Marking Pin 1 orientation. DS069 (v4.1) August 21,

XC95288 In-System Programmable CPLD

0 XC95288 In-System Programmable CPLD November 12, 1997 (Version 2.0) 0 3* Preliminary Product Specification Features 15 ns pin-to-pin logic delays on all pins f CNT to 95 MHz 288 macrocells with 6,400