5 V and 3.3 V ISR High Performance CPLDs

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1 5 V and 3.3 V ISR High Performance CPLDs 5 V and 3.3 V ISR High Performance CPLDs Features In-System Reprogrammable (ISR ) CMOS CPLDs JTAG interface for reconfigurability Design changes do not cause pinout changes Design changes do not cause timing changes High Density 32 to 52 macrocells 32 to 264 I/O pins 5 dedicated inputs including 4 clock pins Simple Timing Model No fanout delays No expander delays No dedicated vs. I/O pin delays No additional delay through PIM No penalty for using full product terms No delay for steering or sharing product terms 3.3 V and 5 V Versions PCI Compatible [] Programmable Bus-hold Capabilities on All I/Os Intelligent Product Term Allocator Provides to product terms to any macrocell Product term steering on an individual basis Product term sharing among local macrocells Flexible Clocking 4 synchronous clocks per device Product term clocking Clock polarity control per logic block Consistent Package and Pinout Offering across All Densities Simplifies design migration Same pinout for 3.3 V and 5 V devices Packages 44 to 256 pins in PLCC, PQFP, TQFP, and Fine-Pitch BGA Packages Pb-free packages available General Description The Ultra37 family of CMOS CPLDs provides a range of high density programmable logic solutions with unparalleled system performance. The Ultra37 family is designed to bring the flexibility, ease of use, and performance of the 22 V to high density CPLDs. The architecture is based on a number of logic blocks that are connected by a Programmable Interconnect Matrix (PIM). Each logic block features its own product term array, product term allocator, and macrocells. The PIM distributes signals from the logic block outputs and all input pins to the logic block inputs. All the Ultra37 devices are electrically erasable and In-System Reprogrammable (ISR), which simplifies both design and manufacturing flows, thereby reducing costs. The ISR feature provides the ability to reconfigure the devices without having design changes cause pinout or timing changes. The Cypress ISR function is implemented through a JTAG-compliant serial interface. Data is shifted in and out through the TDI and TDO pins, respectively. Because of the superior routability and simple timing model of the Ultra37 devices, ISR allows users to change existing logic designs while simultaneously fixing pinout assignments and maintaining system performance. The entire family features JTAG for ISR and boundary scan, and is compatible with the PCI Local Bus specification, meeting the electrical and timing requirements. The Ultra37 family features user programmable bus-hold capabilities on all I/Os. Ultra37 5 V Devices The Ultra37 devices operate with a 5 V supply and can support 5 V or 3.3 V I/O levels. connections provide the capability of interfacing to either a 5 V or 3.3 V bus. By connecting the pins to 5 V the user insures 5V TTL levels on the outputs. If is connected to 3.3 V the output levels meet 3.3 V JEDEC standard CMOS levels and are 5 V tolerant. These devices require 5 V ISR programming. Ultra37V 3.3 V Devices Devices operating with a 3.3 V supply require 3.3 V on all pins, reducing the device s power consumption. These devices support 3.3 V JEDEC standard CMOS output levels, and are 5V-tolerant. These devices allow 3.3 V ISR programming. Note. Due to the 5 V tolerant nature of 3.3 V device I/Os, the I/Os are not clamped to V CC, PCI V IH = 2 V. Cypress Semiconductor Corporation 98 Champion Court San Jose, CA Document Number: Rev. *I Revised August 23, 22

2 Contents Logic Block Diagrams... 3 Selection Guide V Selection Guide V Selection Guide... 7 Pin Configurations... 8 Architecture Overview of Ultra37 Family... 3 Programmable Interconnect Matrix... 3 Logic Block... 3 Product Term Allocator... 4 Ultra37 Macrocell... 4 Clocking... Timing Model... JTAG and PCI Standards... 7 PCI Compliance... 7 IEEE 49.-compliant JTAG... 7 Development Software Support... 7 Warp... 7 Warp Professional... 7 Warp Enterprise... 7 Third-Party Software... 7 Programming... 7 Third-Party Programmers V Device Maximum Ratings... 9 Operating Range V Device Electrical Characteristics... 9 Inductance... 2 Capacitance... 2 Endurance Characteristics V Device Maximum Ratings... 2 Operating Range V Device Electrical Characteristics... 2 Inductance Capacitance Endurance Characteristics AC Test Loads and Waveforms Switching Characteristics Switching Characteristics Switching Waveforms... 3 Power Consumption Typical 5 V Power Consumption Typical 3.3 V Power Consumption Ordering Information V Ordering Information V Ordering Information... 4 Ordering Code Definitions... 4 Package Diagrams Acronyms Document Conventions Units of Measure Document History Page Sales, Solutions, and Legal Information... 5 Worldwide Sales and Design Support... 5 Products... 5 PSoC Solutions... 5 Document Number: Rev. *I Page 2 of 5

3 Logic Block Diagrams CY3732/CY3732V Input Clock/ Input 4 TDI TCK TMS JTAG Tap Controller TDO JTAG EN 4 4 I/Os I/Os I/O I/O 5 PIM I/O I/O 3 A B CY3764/CY3764V Input Clock/ Input I/Os I/O -I/O 5 I/Os I/O -I/O 3 4 A B 32 PIM 4 4 D C 32 I/Os I/O 48 -I/O 63 I/Os I/O 32 -I/O 47 TDI TCK TMS JTAG Tap Controller TDO Document Number: Rev. *I Page 3 of 5

4 Logic Block Diagrams (continued) CY3728/CY3728V INPUTS CLOCK INPUTS TDI TCK TMS JTAG Tap Controller TDO 4 INPUT INPUT/CLOCK MACROCELL MACROCELLS 4 4 JTAG EN I/Os I/O I/O 5 A PIM H I/Os I/O 2 I/O 27 I/Os I/O I/O 3 B G I/Os I/O 96 I/O I/Os I/O 32 I/O 47 I/Os I/O 28 I/O 63 CY3792/CY3792V I/Os I/O I/O 9 I/Os I/O I/O 9 I/Os I/O 2 I/O 29 I/Os I/O 3 I/O 39 I/Os I/O 4 I/O 49 I/Os I/O 5 I/O 59 C D F E A B C D E F Input PIM Clock/ Input 4 4 L K J I H G I/Os I/O 8 I/O 95 I/Os I/O 64 I/O 79 I/Os I/O I/O 9 I/Os I/O I/O 9 I/Os I/O 9 I/O 99 I/Os I/O 8 I/O 89 I/Os I/O 7 I/O 79 I/Os I/O 6 I/O 69 TDI TCK TMS JTAG Tap Controller TDO 6 6 Document Number: Rev. *I Page 4 of 5

5 Logic Block Diagrams (continued) CY37256/CY37256V Input Clock/ Input 4 TDI TCK TMS I/O I/O I/O 2 I/O 23 I/O 24 I/O 35 2 I/Os 2 I/Os 2 I/Os 2 I/Os I/O I/O 47 I/O 48 I/O 59 I/O 6 I/O 7 2 I/Os 2 I/Os 2 I/Os I/O 72 I/O 83 I/O 84 I/O 95 JTAG Tap Controller 2 I/Os TDO 4 A B C D E F G H 96 PIM 4 P O N M L K J I 96 2 I/Os I/O 8 I/O 9 2 I/Os I/O 8 I/O 79 2 I/Os I/O 56 I/O 7 2 I/Os I/O 44 I/O 55 2 I/Os I/O 32 I/O 43 2 I/Os I/O 2 I/O 3 2 I/Os I/O 8 I/O 9 2 I/Os I/O 96 I/O 7 Document Number: Rev. *I Page 5 of 5

6 Selection Guide 5 V Selection Guide Table. General Information Device Macrocells Dedicated Inputs I/O Pins Speed (t PD ) Speed (f MAX ) CY CY / CY / CY CY // Table 2. Speed Bins Device CY3732 X X CY3764 X X X CY3728 X X X CY3792 X X CY37256 X X Table 3. Device-Package Offering and I/O Count Device 44-pin TQFP 44-pin PLCC -pin TQFP -pin TQFP CY CY CY CY CY Document Number: Rev. *I Page 6 of 5

7 3.3 V Selection Guide Table 4. General Information Device Macrocells Dedicated Inputs I/O Pins Speed (t PD ) Speed (f MAX ) CY3732V CY3764V / CY3728V /8/28 25 CY3792V CY37256V //92 2 Table 5. Speed Bins Device CY3732V X X CY3764V X X CY3728V X X CY3792V X X CY37256V X X Table 6. Device-Package Offering and I/O Count Device 44-pin TQFP -pin TQFP -pin TQFP 256-ball FBGA CY3732V 37 CY3764V CY3728V CY3792V 25 CY37256V Document Number: Rev. *I Page 7 of 5

8 Pin Configurations The Pin Configurations are as follows. [2] Figure. 44-pin TQFP pinout (Top View) I/O 3 I/O 4 I/O 2 I/O I/O I/O 3 I/O 3 I/O 29 I/O 28 I/O 5 /TCK I/O 6 I/O 7 CLK 2 /I JTAG EN CLK /I I/O 8 I/O 9 I/O I/O I/O 5 /TCK I/O 6 I/O 7 CLK 2 /I JTAG EN CLK /I I/O 8 I/O 9 I/O I/O I/O 2 I/O 3 /TMS I/O 4 I/O 5 V CC I/O I/O 7 I/O 8 I/O 9 /TDO I/O 2 Figure pin PLCC pinout (Top View) I/O 27 /TDI I/O 26 I/O 25 I/O 24 CLK /I 4 I 3 CLK 3 /I 2 I/O 23 I/O 22 I/O 2 I/O 27 /TDI I/O 26 I/O 25 I/O 24 CLK /I 4 I 3 CLK 3 /I 2 I/O 23 I/O 22 I/O 2 I/O 2 I/O /TMS 3 I/O 4 I/O 5 V CC I/O I/O 7 I/O 8 I/O 9 /TDO I/O 2 I/O 4 I/O 3 I/O 2 I/O I/O I/O 3 I/O 3 I/O 29 I/O Note 2. For 3.3 V versions (Ultra37V), = V CC. Document Number: Rev. *I Page 8 of 5

9 Pin Configurations (continued) The Pin Configurations are as follows. [2] Figure 3. -pin TQFP pinout (Top View) NC TCK TDI I/O 8 I/O 9 I/O I/O I/O I/O 55 I/O 54 I/O 53 I/O 52 I/O 5 I/O 3 I/O 4 I/O 5 CLK /I N/C CLK /I I/O I/O 7 I/O 8 I/O 9 I/O 2 I/O 2 I/O 22 I/O 23 NC I/O 5 I/O 49 I/O 48 CLK 3 /I 4 NC CLK 2 /I 3 I / O 47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 4 I/O 4 NC TMS I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 3 I/O 3 I 2 NC V CC [3 ] I/O 32 I/O 33 I/O 34 I/O 35 I/O I/O 37 I/O 38 I/O 39 TDO I/O I/O I/O I/O I/O I/O I/O I/O NC V CC N/C I/O 63 I/O 62 I/O 6 I/O 6 I/O 59 I/O 58 I/O 57 I/O 56 NC Note 3. This pin is a N/C, but Cypress recommends that you connect it to V CC to ensure future compatibility. Document Number: Rev. *I Page 9 of 5

10 Pin Configurations (continued) The Pin Configurations are as follows. [2] Figure 4. -pin TQFP pinout (Top View) For CY3728(V) and CY37256(V) I/O 5 I/O 4 I/O 3 I/O 2 I/O I/O I/O 9 I/O 8 I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 I/O 2 I/O I/O V CC JTAG EN I/O 27 I/O 26 I/O 25 I/O 24 I/O 23 I/O 22 I/O 2 I/O 2 I/O 9 I/O 8 I/O 7 I/O I/O 5 I/O 4 I/O 3 I/O 2 I/O I/O 7 I/O 8 I/O 9 I/O 2 /TCK I/O 2 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 3 I/O 3 CLK /I CLK /I I/O 32 I/O 33 I/O 34 I/O 35 I/O I/O 37 I/O 38 I/O 39 I/O 4 I/O 4 I/O 42 I/O 43 I/O 44 I/O 45 I/O 46 I/O I/O I/O I/O I/O I/O 52 /TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I V CC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 76 /TDO I/O I/O I/O I/O I/O I/O 9 I/O 8 /TDI I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 I/O 2 I/O I/O I/O 99 I/O 98 I/O 97 I/O 96 CLK 3 /I 4 CLK 2 /I 3 I/O 95 I/O 94 I/O 93 I/O 92 I/O 9 I/O 9 I/O 89 I/O 88 I/O 87 I/O 86 I/O 85 I/O 84 I/O 83 I/O 82 I/O 8 I/O 8 Document Number: Rev. *I Page of 5

11 Pin Configurations (continued) The Pin Configurations are as follows. [2] Figure 5. -pin TQFP pinout (Top View) For CY3792(V) I/O 5 I/O 4 I/O 3 I/O 2 I/O I/O I/O 9 I/O 8 I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 I/O 2 I/O I/O V CC NC I/O 9 I/O 8 I/O 7 I/O I/O 5 I/O 4 I/O 3 I/O 2 I/O I/O I/O 9 I/O 8 I/O 7 I/O 6 I/O 5 NC NC I/O I/O 7 I/O 8 TCK I/O 9 I/O 2 I/O 2 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 CLK /I CLK /I I/O 3 I/O 3 I/O 32 I/O 33 I/O 34 I/O 35 I/O I/O 37 I/O 38 I/O 39 I/O 4 I/O 4 I/O 42 I/O 43 I/O 44 I/O NC I/O I/O I/O TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I V CC I/O I/O 6 64 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDO I/O I/O I/O I/O 4 I/O 3 I/O 2 TDI I/O I/O I/O 99 I/O 98 I/O 97 I/O 96 I/O 95 I/O 94 I/O 93 I/O 92 I/O 9 I/O 9 CLK 3 /I 4 CLK 2 /I 3 I/O 89 I/O 88 I/O 87 I/O 86 I/O 85 I/O 84 I/O 83 I/O 82 I/O 8 I/O 8 I/O 79 I/O 78 I/O 77 I/O 76 I/O 75 NC Document Number: Rev. *I Page of 5

12 Pin Configurations (continued) The Pin Configurations are as follows. [2] Figure ball FBGA pinout (Top View) A I/O 26 I/O 24 I/O 2 V CC I/O I/O 86 V CC I/O 77 I/O 72 I/O 7 B I/O 27 I/O 25 I/O 23 I/O 9 I/O 5 I/O I/O 85 I/O 8 I/O 76 I/O 7 I/O 6 I/O 5 C I/O 29 I/O 28 NC I/O 22 I/O 8 I/O 4 I/O 9 I/O 4 I/O 9 I/O 84 I/O 8 I/O 75 I/O 7 NC I/O 3 I/O 4 D I/O 32 I/O 3 I/O 3 NC I/O 7 I/O 3 I/O 8 I/O 3 I/O 9 I/O 83 I/O 79 I/O 74 I/O 9 I/O I/O I/O 2 E I/O 35 I/O 34 I/O 33 I/O 2 I/O I/O 2 I/O 7 I/O 2 I/O 89 V CC I/O 78 I/O 73 I/O 8 I/O 57 I/O 58 I/O 59 F V CC I/O 38 I/O 37 I/O TCK V CC I/O 6 I/O I/O 88 I/O 82 V CC TDI I/O 54 I/O 55 I/O 56 V CC G I/O 43 I/O 42 I/O 4 I/O 4 V CC I/O 39 I/O 5 I/O I/O 87 I/O 48 I/O 49 CLK 3 / I 4 I/O 5 I/O 5 I/O 52 I/O 53 H I/O 47 I/O 46 CLK / I I/O 45 I/O 44 I/O 44 I/O 45 CLK 2 / I 3 I/O 46 I/O 47 J I/O 5 I/O 5 NC I/O 49 I/O 48 I/O 4 I/O 4 I 2 I/O 42 I/O 43 K I/O 57 I/O 56 I/O 55 I/O 54 CLK / I I/O 53 I/O 52 I/O 9 I/O 96 I/O I/O 35 V CC I/O I/O 37 I/O 38 I/O 39 L V CC I/O 6 I/O 59 I/O 58 TMS V CC I/O 86 I/O 92 I/O 97 I/O 2 V CC TDO I/O 32 I/O 33 I/O 34 V CC M I/O 63 I/O 62 I/O 6 I/O 72 I/O 77 I/O 82 V CC I/O 93 I/O 98 I/O 3 I/O 8 I/O 2 I/O 7 I/O 29 I/O 3 I/O 3 N I/O 66 I/O 65 I/O 64 I/O 73 I/O 78 I/O 83 I/O 87 I/O 94 I/O 99 I/O 4 I/O 9 I/O 3 NC I/O 26 I/O 27 I/O 28 P I/O 68 I/O 67 NC I/O 74 I/O79 I/O 84 I/O 88 I/O 95 I/O I/O 5 I/O I/O 4 I/O 8 NC I/O 24 I/O 25 R I/O 69 I/O 7 I/O 75 I/O 8 I/O 85 I/O 89 I/O 6 I/O I/O 5 I/O 9 I/O 2 I/O 23 T I/O 7 I/O 76 I/O 8 V CC I/O 9 I/O 7 V CC I/O I/O 2 I/O 22 Document Number: Rev. *I Page 2 of 5

13 Architecture Overview of Ultra37 Family Programmable Interconnect Matrix The PIM consists of a completely global routing matrix for signals from I/O pins and feedbacks from the logic blocks. The PIM provides extremely robust interconnection to avoid fitting and density limitations. The inputs to the PIM consist of all I/O and dedicated input pins and all macrocell feedbacks from within the logic blocks. The number of PIM inputs increases with pin count and the number of logic blocks. The outputs from the PIM are signals routed to the appropriate logic blocks. Each logic block receives inputs from the PIM and their complements, allowing for 32-bit operations to be implemented in a single pass through the device. The wide number of inputs to the logic block also improves the routing capacity of the Ultra37 family. An important feature of the PIM is its simple timing. The propagation delay through the PIM is accounted for in the timing specifications for each device. There is no additional delay for traveling through the PIM. In fact, all inputs travel through the PIM. As a result, there are no route-dependent timing parameters on the Ultra37 devices. The worst-case PIM delays are incorporated in all appropriate Ultra37 specifications. Routing signals through the PIM is completely invisible to the user. All routing is accomplished by software no hand routing is necessary. Warp and third-party development packages automatically route designs for the Ultra37 family in a matter of minutes. Finally, the rich routing resources of the Ultra37 family accommodate last minute logic changes while maintaining fixed pin assignments. FROM PIM 72 x 87 PRODUCT TERM ARRAY Figure 7. Logic Block with 5% Buried Macrocells 7 8 PRODUCT TERM ALLOCATOR Logic Block The logic block is the basic building block of the Ultra37 architecture. It consists of a product term array, an intelligent product-term allocator, macrocells, and a number of I/O cells. The number of I/O cells varies depending on the device used. Refer to Figure 7 for the block diagram. Product Term Array Each logic block features a programmable product term array. This array accepts inputs from the PIM, which originate from macrocell feedbacks and device pins. Active LOW and active HIGH versions of each of these inputs are generated to create the full 72-input field. The 87 product terms in the array can be created from any of the 72 inputs. Of the 87 product terms, 8 are for general-purpose use for the macrocells in the logic block. Four of the remaining seven product terms in the logic block are output enable (OE) product terms. Each of the OE product terms controls up to eight of the macrocells and is selectable on an individual macrocell basis. In other words, each I/O cell can select between one of two OE product terms to control the output buffer. The first two of these four OE product terms are available to the upper half of the I/O macrocells in a logic block. The other two OE product terms are available to the lower half of the I/O macrocells in a logic block. The next two product terms in each logic block are dedicated asynchronous set and asynchronous reset product terms. The final product term is the product term clock. The set, reset, OE and product term clock have polarity control to realize OR functions in a single pass through the array. PRODUCT TERMS PRODUCT TERMS MACRO- CELL MACRO- CELL 3 2 I/O CELL 2 to cells 2, 4, 6 8,, 2 PRODUCT TERMS MACRO- CELL 4 I/O CELL 4 TO PIM PRODUCT TERMS MACRO- CELL 5 8 Document Number: Rev. *I Page 3 of 5

14 Low Power Option Each logic block can operate in high speed mode for critical path performance, or in low power mode for power conservation. The logic block mode is set by the user on a logic block by logic block basis. Product Term Allocator Through the product term allocator, software automatically distributes product terms among the macrocells in the logic block as needed. A total of 8 product terms are available from the local product term array. The product term allocator provides two important capabilities without affecting performance: product term steering and product term sharing. Product Term Steering Product term steering is the process of assigning product terms to macrocells as needed. For example, if one macrocell requires ten product terms while another needs just three, the product term allocator will steer ten product terms to one macrocell and three to the other. On Ultra37 devices, product terms are steered on an individual basis. Any number between and product terms can be steered to any macrocell. Note that product terms is useful in cases where a particular macrocell is unused or used as an input register. Product Term Sharing Product term sharing is the process of using the same product term among multiple macrocells. For example, if more than one output has one or more product terms in its equation that are common to other outputs, those product terms are only programmed once. The Ultra37 product term allocator allows sharing across groups of four output macrocells in a variable fashion. The software automatically takes advantage of this capability the user does not have to intervene. Note that neither product term sharing nor product term steering have any effect on the speed of the product. All worst-case steering and sharing configurations are incorporated in the timing specifications for the Ultra37 devices. Ultra37 Macrocell Within each logic block there are macrocells. Macrocells can either be I/O Macrocells, which include an I/O Cell which is associated with an I/O pin, or buried Macrocells, which do not connect to an I/O. The combination of I/O Macrocells and buried Macrocells varies from device to device. Buried Macrocell Figure 8 displays the architecture of buried macrocells. The buried macrocell features a register that can be configured as combinatorial, a D flip-flop, a T flip-flop, or a level-triggered latch. The register can be asynchronously set or asynchronously reset at the logic block level with the separate set and reset product terms. Each of these product terms features programmable polarity. This allows the registers to be set or reset based on an AND expression or an OR expression. Clocking of the register is very flexible. Four global synchronous clocks and a product term clock are available to clock the register. Furthermore, each clock features programmable polarity so that registers can be triggered on falling and rising edges (see Clocking on page ). Clock polarity is chosen at the logic block level. The buried macrocell also supports input register capability. The buried macrocell can be configured to act as an input register (D-type or latch) whose input comes from the I/O pin associated with the neighboring macrocell. The output of all buried macrocells is sent directly to the PIM regardless of its configuration. I/O Macrocell Figure 8 on page 5 illustrates the architecture of the I/O macrocell. The I/O macrocell supports the same functions as the buried macrocell with the addition of I/O capability. At the output of the macrocell, a polarity control mux is available to select active LOW or active HIGH signals. This has the added advantage of allowing significant logic reduction to occur in many applications. The Ultra37 macrocell features a feedback path to the PIM separate from the I/O pin input path. This means that if the macrocell is buried (fed back internally only), the associated I/O pin can still be used as an input. Bus Hold Capabilities on all I/Os Bus-hold, which is an improved version of the popular internal pull-up resistor, is a weak latch connected to the pin that does not degrade the device s performance. As a latch, bus-hold maintains the last state of a pin when the pin is placed in a high impedance state, thus reducing system noise in bus-interface applications. Bus-hold additionally allows unused device pins to remain unconnected on the board, which is particularly useful during prototyping as designers can route new signals to the device without cutting trace connections to V CC or. For more information, see the application note Understanding Bus-Hold A Feature of Cypress CPLDs. Programmable Slew Rate Control Each output has a programmable configuration bit, which sets the output slew rate to fast or slow. For designs concerned with meeting FCC emissions standards the slow edge provides for lower system noise. For designs requiring very high performance the fast edge rate provides maximum system performance. Document Number: Rev. *I Page 4 of 5

15 Figure 8. I/O and Buried Macrocells I/O MACROCELL FROM PTM PRODUCT TERMS O C C C24 C25 P D/T/L R Q O DECODE C2 C3 C4 O FAST SLOW SLEW 2 3 C26 C6 C5 O I/O CELL FROM PTM PRODUCT TERMS BURIED MACROCELL ASYNCHRONOUS RESET 4 SYNCHRONOUS CLOCKS (CLK,CLK,CLK2,CLK3) ASYNCHRONOUS ASYNCHRONOUS CLOCK(PTCLK) PRESET Q C C C24 C25 C7 O P D/T/L R Q FEEDBACK TO PIM DECODE C2 FEEDBACK TO PIM FEEDBACK TO PIM C3 O OE OE INPUT PIN Figure 9. Input Macrocell FROM CLOCK POLARITY MUXES 2 3 O D Q D Q 2 3 C2 C3 O TO PIM C C D Q LE Document Number: Rev. *I Page 5 of 5

16 Figure. Input/Clock Macrocell O TO CLOCK MUX ON ALL INPUT MACROCELLS INPUT/CLOCK PIN C2 FROM CLOCK POLARITY INPUT CLOCK PINS 2 3 O D Q D Q 2 3 CC O TO PIM O C3, C4, C5 OR C TO CLOCK MUX IN EACH CLOCK POLARITY MUX ONE PER FOR EACH CLOCK INPUT C8 C9 D Q LE Clocking Each I/O and buried macrocell has access to four synchronous clocks (CLK, CLK, CLK2 and CLK3) and an asynchronous product term clock PTCLK. Each input macrocell has access to all four synchronous clocks. Dedicated Inputs/Clocks Five pins on each member of the Ultra37 family are designated as input-only. There are two types of dedicated inputs on Ultra37 devices: input pins and input/clock pins. Figure 9 on page 5 illustrates the architecture for input pins. Four input options are available for the user: combinatorial, registered, double-registered, or latched. If a registered or latched option is selected, any one of the input clocks can be selected for control. Figure illustrates the architecture for the input/clock pins. Similar to the input pins, input/clock pins can be combinatorial, registered, double-registered, or latched. In addition, these pins feed the clocking structures throughout the device. The clock path at the input has user-configurable polarity. Product Term Clocking In addition to the four synchronous clocks, the Ultra37 family also has a product term clock for asynchronous clocking. Each logic block has an independent product term clock which is available to all macrocells. Each product term clock also supports user configurable polarity selection. Timing Model One of the most important features of the Ultra37 family is the simplicity of its timing. All delays are worst case and system performance is unaffected by the features used. Figure illustrates the true timing model for the 7-MHz devices in high speed mode. For combinatorial paths, any input to any output incurs a 6.5 ns worst-case delay regardless of the amount of logic used. For synchronous systems, the input setup time to the output macrocells for any input is 3.5 ns and the clock to output time is also 4. ns. These measurements are for any output and synchronous clock, regardless of the logic used. The Ultra37 features: No fanout delays No expander delays No dedicated vs. I/O pin delays No additional delay through PIM No penalty for using product terms No added delay for steering product terms No added delay for sharing product terms No routing delays No output bypass delays The simple timing model of the Ultra37 family eliminates unexpected performance penalties. INPUT INPUT CLOCK Figure. Timing Model for CY3728 t S = 3.5 ns COMBINATORIAL SIGNAL t PD = 6.5 ns REGISTERED SIGNAL D,T,L O t CO = 4.5 ns OUTPUT OUTPUT Document Number: Rev. *I Page of 5

17 JTAG and PCI Standards PCI Compliance 5V operation of the Ultra37 is fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The 3.3V products meet all PCI requirements except for the output 3.3V clamp, which is in direct conflict with 5V tolerance. The Ultra37 family s simple and predictable timing model ensures compliance with the PCI AC specifications independent of the design. IEEE 49.-compliant JTAG The Ultra37 family has an IEEE 49. JTAG interface for both Boundary Scan and ISR. Boundary Scan The Ultra37 family supports Bypass, Sample/Preload, Extest, Idcode, and Usercode boundary scan instructions. The JTAG interface is shown in Figure 2. TDI TMS TCK JTAG TAP CONTROLLER Figure 2. JTAG Interface Instruction Register Bypass Reg. Boundary Scan idcode Usercode ISR Prog. Data Registers TDO In-System Reprogramming (ISR) In-System Reprogramming is the combination of the capability to program or reprogram a device on-board, and the ability to support design changes without changing the system timing or device pinout. This combination means design changes during debug or field upgrades do not cause board respins. The Ultra37 family implements ISR by providing a JTAG compliant interface for on-board programming, robust routing resources for pinout flexibility, and a simple timing model for consistent system performance. Development Software Support Warp Warp is a state-of-the-art compiler and complete CPLD design tool. For design entry, Warp provides an IEEE-STD-76/4 VHDL text editor, an IEEE-STD-4 Verilog text editor, and a graphical finite state machine editor. It provides optimized synthesis and fitting by replacing basic circuits with ones pre-optimized for the target device, by implementing logic in unused memory and by perfect communication between fitting and synthesis. To facilitate design and debugging, Warp provides graphical timing simulation and analysis. Warp Professional Warp Professional contains several additional features. It provides an extra method of design entry with its graphical block diagram editor. It allows up to 5 ms timing simulation instead of only 2 ms. It allows comparison of waveforms before and after design changes. Warp Enterprise Warp Enterprise provides even more features. It provides unlimited timing simulation and source-level behavioral simulation as well as a debugger. It has the ability to generate graphical HDL blocks from HDL text. It can even generate testbenches. Warp is available for PC and UNIX platforms. Some features are not available in the UNIX version. For further information see the Warp for PC, Warp for UNIX, Warp Professional and Warp Enterprise data sheets on Cypress s web site. Third-Party Software Although Warp is a complete CPLD development tool on its own, it interfaces with nearly every third party EDA tool. All major third-party software vendors provide support for the Ultra37 family of devices. Refer to the third-party software data sheet or contact your local sales office for a list of currently supported third-party vendors. Programming There are four programming options available for Ultra37 devices. The first method is to use a PC with the 37 UltraISR programming cable and software. With this method, the ISR pins of the Ultra37 devices are routed to a connector at the edge of the printed circuit board. The 37 UltraISR programming cable is then connected between the parallel port of the PC and this connector. A simple configuration file instructs the ISR software of the programming operations to be performed on each of the Ultra37 devices in the system. The ISR software then automatically completes all of the necessary data manipulations required to accomplish the programming, reading, verifying, and other ISR functions. For more information on the Cypress ISR Interface, see the CYUSBISRPC Programming Cable User s Guide. Document Number: Rev. *I Page 7 of 5

18 The second method for programming Ultra37 devices is on automatic test equipment (ATE). This is accomplished through a file created by the ISR software. Check the Cypress website for the latest ISR software download information. The third programming option for Ultra37 devices is to utilize the embedded controller or processor that already exists in the system. The Ultra37 ISR software assists in this method by converting the device JEDEC maps into the ISR serial stream that contains the ISR instruction information and the addresses and data of locations to be programmed. The embedded controller then simply directs this ISR stream to the chain of Ultra37 devices to complete the desired reconfiguring or diagnostic operations. Contact your local sales office for information on availability of this option. The fourth method for programming Ultra37 devices is to use the same programmer that is currently being used to program FLASH37i devices. For all pinout, electrical, and timing requirements, refer to device data sheets. For ISR cable and software specifications, refer to the UltraISR kit data sheet (CY37i). Third-Party Programmers As with development software, Cypress support is available on a wide variety of third-party programmers. All major third-party programmers (including BP Micro, Data I/O, and SMS) support the Ultra37 family. Document Number: Rev. *I Page 8 of 5

19 5 V Device Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage Temperature C to +5 C Ambient Temperature with Power Applied C to +25 C Supply Voltage to Ground Potential....5 V to +7. V Operating Range The Operating Range is described as follows. [4] DC Voltage Applied to Outputs in High-Z State....5 V to +7. V DC Input Voltage....5 V to +7. V DC Program Voltage to 5.5 V Current into Outputs... ma Static Discharge Voltage (per MIL-STD-883, Method 35)... > 2 V Latch-up Current... > 2 ma Range Ambient Temperature [4] Junction Temperature Output Condition V CC Commercial C to +7 C C to +9 C 5 V 5 V.25 V 5 V.25 V 3.3 V 5 V.25 V 3.3 V.3 V Industrial 4 C to +85 C 4 C to +5 C 5 V 5 V.5 V 5 V.5 V 3.3 V 5 V.5 V 3.3 V.3 V 5 V Device Electrical Characteristics Over the Operating Range [8] Parameter Description Test Conditions Min Typ Max Unit V OH Output HIGH Voltage V CC = Min I OH = 3.2 ma (Commercial / Industrial) [6] 2.4 V I OH = 2. ma (Military) [6] 2.4 V V OHZ Output HIGH Voltage with Output Disabled [7] V CC = Max I OH = A (Commercial) I OH = A (Industrial / Military) [8] V V I OH = A (Commercial) [8] 3.6 V I OH = 5 A (Industrial / Military) [8] 3.6 V V OL Output LOW Voltage V CC = Min I OL = ma (Commercial / Industrial) [6].5 V I OL = 2 ma (Military) [6].5 V V IH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs [9] 2. V CCmax V V IL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs [9].5.8 V I IX Input Load Current V I = or V CC, Bus-Hold Disabled A I OZ Output Leakage Current V O = or V CC, Output Disabled, Bus-Hold 5 5 A Disabled I OS Output Short Circuit Current [7, ] V CC = Max, V OUT =.5 V 3 ma Notes 4. Normal Programming Conditions apply across Ambient Temperature Range for specified programming methods. For more information on programming the Ultra37 Family devices, refer to the Application Note titled An Introduction to In System Reprogramming with the Ultra T A is the Instant On case temperature. 6. I OH = 2 ma, I OL = 2 ma for TDO. 7. Tested initially and after any design or process changes that may affect these parameters. 8. When the I/O is output disabled, the bus-hold circuit can weakly pull the I/O to above 3.6V if no leakage current is allowed. Note that all I/Os are output disabled during ISR programming. Refer to the application note Understanding Bus-Hold for additional information. 9. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.. Not more than one output should be tested at a time. Duration of the short circuit should not exceed second. V OUT =.5 V is chosen to avoid test problems caused b t t d d d ti Document Number: Rev. *I Page 9 of 5

20 5 V Device Electrical Characteristics (continued) Over the Operating Range Parameter Description Test Conditions Min Typ Max Unit I BHL Input Bus-Hold LOW Sustaining V CC = Min, V IL =.8 V +75 A Current I BHH Input Bus-Hold HIGH Sustaining V CC = Min, V IH = 2. V 75 A Current I BHLO Input Bus-Hold LOW Overdrive V CC = Max +5 A Current I BHHO Input Bus-Hold HIGH Overdrive Current V CC = Max 5 A Inductance Parameter [] Description Test Conditions L Maximum Pin Inductance V IN = 5 V at f = MHz Capacitance 44-pin TQFP 44-pin PLCC -pin TQFP -pin TQFP Unit nh Parameter [] Description Test Conditions Max Unit C I/O Input/Output Capacitance V IN = 5 V at f = MHz at T A = 25 C pf C CLK Clock Signal Capacitance V IN = 5 V at f = MHz at T A = 25 C 2 pf C DP Dual-Function Pins [2] V IN = 5 V at f = MHz at T A = 25 C pf Endurance Characteristics Parameter [] Description Test Conditions Min Typ Unit N Minimum Reprogramming Normal Programming Conditions [3],, Cycles Cycles Notes. Tested initially and after any design or process changes that may affect these parameters. 2. Dual pins are I/O with JTAG pins. 3. Normal Programming Conditions apply across Ambient Temperature Range for specified programming methods. For more information on programming the Ultra37 Family devices, refer to the Application Note titled An Introduction to In System Reprogramming with the Ultra37. Document Number: Rev. *I Page 2 of 5

21 3.3 V Device Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage Temperature C to +5 C Ambient Temperature with Power Applied C to +25 C Supply Voltage to Ground Potential....5 V to +4.6 V Operating Range DC Voltage Applied to Outputs in High-Z State....5 V to +7. V DC Input Voltage....5 V to +7. V DC Program Voltage to 3.6 V Current into Outputs... 8 ma Static Discharge Voltage (per MIL-STD-883, Method 35)... > 2 V Latch-up Current... > 2 ma The Operating Range is described as follows. [4] Range Ambient Temperature [4] Junction Temperature V [5] CC Commercial C to +7 C C to +9 C 3.3 V ±.3 V Industrial 4 C to +85 C 4 C to +5 C 3.3 V ±.3 V 3.3 V Device Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min Max Unit V OH Output HIGH Voltage V CC = Min I OH = 4 ma (Commercial) [] 2.4 V I OH = 3 ma (Military) [] V OL Output LOW Voltage V CC = Min I OL = 8 ma (Commercial) [].5 V I OL = 6 ma (Military) [] V IH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs [7] V V IL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs [7].5.8 V I IX Input Load Current V I = or V CC, Bus-Hold Disabled A I OZ Output Leakage Current V O = or V CC, Output Disabled, Bus-Hold 5 5 A Disabled I OS Output Short Circuit V CC = Max, V OUT =.5 V 3 ma Current [8, 9] I BHL Input Bus-Hold LOW Sustaining V CC = Min, V IL =.8 V +75 A Current I BHH Input Bus-Hold HIGH Sustaining V CC = Min, V IH = 2. V 75 A Current I BHLO Input Bus-Hold LOW Overdrive V CC = Max +5 A Current I BHHO Input Bus-Hold HIGH Overdrive Current V CC = Max 5 A Notes 4. Normal Programming Conditions apply across Ambient Temperature Range for specified programming methods. For more information on programming the Ultra37 Family devices, refer to the Application Note titled An Introduction to In System Reprogramming with the Ultra For CY3764VP-43AXC, CY3764VP44-43AXC; Operating Range: V CC is 3.3 V ±. V.. I OH = 2 ma, I OL = 2 ma for TDO. 7. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 8. Tested initially and after any design or process changes that may affect these parameters. 9. Not more than one output should be tested at a time. Duration of the short circuit should not exceed second. V OUT =.5 V is chosen to avoid test problems caused Document Number: Rev. *I Page 2 of 5

22 Inductance Parameter [2] Description Test Conditions L Maximum Pin Inductance V IN = 3.3 V at f = MHz 44- pin TQFP 44-pin PLCC - pin TQFP -pin TQFP Unit nh Capacitance Parameter [2] Description Test Conditions Max Unit C I/O Input/Output Capacitance V IN = 3.3 V at f = MHz at T A = 25 C 8 pf C CLK Clock Signal Capacitance V IN = 3.3 V at f = MHz at T A = 25 C 2 pf C DP Dual Functional Pins [2] V IN = 3.3 V at f = MHz at T A = 25 C pf Endurance Characteristics Parameter [2] Description Test Conditions Min Typ Unit N Minimum Reprogramming Cycles Normal Programming Conditions [22],, Cycles Notes 2. Tested initially and after any design or process changes that may affect these parameters. 2. Dual pins are I/O with JTAG pins. 22. Normal Programming Conditions apply across Ambient Temperature Range for specified programming methods. For more information on programming the Ultra37 Family devices, refer to the Application Note titled An Introduction to In System Reprogramming with the Ultra37. Document Number: Rev. *I Page 22 of 5

23 AC Test Loads and Waveforms 5V OUTPUT 35 pf INCLUDING JIG AND SCOPE Equivalent to: OUTPUT 238 (COM'L) 39 (MIL) (a) 7 (COM'L) 2 (MIL) Figure 3. 5 V AC Test Loads and Waveforms 238 (COM'L) 39 (MIL) 5V 3.V OUTPUT 5 pf INCLUDING JIG AND SCOPE THÉVENIN EQUIVALENT 99 (COM'L) (MIL) 2.8V (COM'L) 2.3V (MIL) (b) 7 (COM'L) 2 (MIL) <2 ns ALL INPUT PULSES 9% 9% % % <2 ns (c) 3.3V OUTPUT 35 pf INCLUDING JIG AND SCOPE 5 OR 35 pf 295 (COM'L) 393 (MIL) 34 (COM'L) 453 (MIL) (a) Equivalent to: THÉVENIN EQUIVALENT 58 (COM L) 27 (MIL) OUTPUT 5 OR 35 pf Figure V AC Test Loads and Waveforms 295 (COM'L) 393 (MIL) 3.3V 3.V OUTPUT.77V (COM'L).77V (MIL) 5 pf INCLUDING JIG AND SCOPE (b) 34 (COM'L) 453 (MIL) <2 ns ALL INPUT PULSES 9% 9% % % <2 ns (c) Document Number: Rev. *I Page 23 of 5

24 Parameter [23] V X Output Waveform Measurement Level t ER( ).5 V t ER(+) 2.6 V V OH.5V.5V V OL V X V X t EA(+).5 V V X.5V V OH t EA( ) V the V X.5V (d) Test Waveforms V OL Note 23. t ER measured with 5 pf AC Test Load and t EA measured with 35 pf AC Test Load. Document Number: Rev. *I Page 24 of 5

25 Switching Characteristics Over the Operating Range Parameter [24] Description Unit Combinatorial Mode Parameters t [25, 26, 27] PD Input to Combinatorial Output ns [25, 26, 27] t PDL Input to Output Through Transparent Input or Output Latch ns t PDLL [25, 26, 27] Input to Output Through Transparent Input and Output Latches ns t [25, 26, 27] EA Input to Output Enable ns [25, 28] t ER Input to Output Disable ns Input Register Parameters t WL Clock or Latch Enable Input LOW Time [] ns t WH Clock or Latch Enable Input HIGH Time [] ns t IS Input Register or Latch Set-up Time ns t IH Input Register or Latch Hold Time ns [25, 26, 27] t ICO Input Register Clock or Latch Enable to Combinatorial Output ns t ICOL [25, 26, 27] Input Register Clock or Latch Enable to Output Through Transparent Output Latch ns Synchronous Clocking Parameters t CO [26, 27] Synchronous Clock (CLK, CLK, CLK 2, or CLK 3 ) or Latch Enable to Output t S [25] Set-Up Time from Input to Sync. Clk (CLK, CLK, CLK 2, or CLK 3 ) or Latch Enable ns t H Register or Latch Data Hold Time ns [25, 26, 27] t CO2 Output Synchronous Clock (CLK, CLK, CLK 2, or CLK 3 ) or Latch Enable to Combinatorial Output Delay ns (Through Logic Array) [25] t SCS Output Synchronous Clock (CLK, CLK, CLK 2, or CLK 3 ) or Latch Enable to Output Synchronous Clock ns (CLK, CLK, CLK 2, or CLK 3 ) or Latch Enable (Through Logic Array) [25] t SL Set-Up Time from Input Through Transparent Latch to Output Register Synchronous Clock (CLK CLK, CLK 2, or CLK 3 ) or Latch Enable ns t HL Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK, CLK, CLK 2, or CLK 3 ) or Latch Enable ns ns Notes 24. All AC parameters are measured with two outputs switching and 35 pf AC Test Load. 25. Logic blocks operating in low power mode, add t LP to this specification. 26. Outputs using Slow Output Slew Rate, add t SLEW to this specification. 27. When = 3.3V, add t 3.3IO to this specification. 28. t ER measured with 5 pf AC Test Load and t EA measured with 35 pf AC Test Load. Document Number: Rev. *I Page 25 of 5

26 Switching Characteristics (continued) Over the Operating Range Parameter [24] Description Unit Product Term Clocking Parameters t COPT [3, 3, 32] Product Term Clock or Latch Enable (PTCLK) to Output t SPT Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK) ns t HPT Register or Latch Data Hold Time ns [3] t ISPT Set-Up Time for Buried Register used as an Input Register from Input to Product Term Clock or Latch ns Enable (PTCLK) t IHPT Buried Register Used as an Input Register or Latch Data Hold Time ns t CO2PT [3, 3, 32] Product Term Clock or Latch Enable (PTCLK) to Output Delay (Through Logic Array) ns Pipelined Mode Parameters [3] t ICS Input Register Synchronous Clock (CLK, CLK, CLK 2, or CLK 3 ) to Output Register Synchronous Clock (CLK, CLK, CLK 2, or CLK 3 ) Operating Frequency Parameters f MAX Maximum Frequency with Internal Feedback (Lesser of /t SCS, /(t S + t H ), or /t CO ) [33] MHz f MAX2 Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of /(t WL + t WH ), /(t S +t H ), or /t CO ) [33] f MAX3 Maximum Frequency with External Feedback (Lesser of /(t CO + t S ) or /(t WL + t WH ) [33] MHz f MAX4 Reset/Preset Parameters Maximum Frequency in Pipelined Mode (Lesser of /(t CO + t IS ), /t ICS, /(t WL + t WH ), /(t IS + t IH ), or MHz /t SCS ) [33] t RW Asynchronous Reset Width [33] ns [3] t RR Asynchronous Reset Recovery Time [33] ns [3, 3, 32] t RO Asynchronous Reset to Output ns t PW Asynchronous Preset Width [33] ns [3] t PR Asynchronous Preset Recovery Time [33] ns [3, 3, 32] t PO Asynchronous Preset to Output ns User Option Parameters t LP Low Power Adder ns t SLEW Slow Output Slew Rate Adder ns t 3.3IO 3.3 V I/O Mode Timing Adder [33] ns JTAG Timing Parameters t S JTAG Set-up Time from TDI and TMS to TCK [33] ns t H JTAG Hold Time on TDI and TMS [33] ns t CO JTAG Falling Edge of TCK to TDO [33] ns f JTAG Maximum JTAG Tap Controller Frequency [33] ns ns ns MHz Notes 29. All AC parameters are measured with two outputs switching and 35 pf AC Test Load. 3. Logic blocks operating in low power mode, add t LP to this specification. 3. Outputs using Slow Output Slew Rate, add t SLEW to this specification. 32. When = 3.3V, add t 3.3IO to this specification. 33. Tested initially and after any design or process changes that may affect these parameters. Document Number: Rev. *I Page 26 of 5

27 Switching Characteristics Over the Operating Range Parameter [34] 2 MHz 7 MHz 54 MHz 43 MHz 25 MHz MHz 83 MHz 66 MHz Min Max Combinatorial Mode Parameters Min Max Min Max Min Max t PD [35,, 37] ns t [35,, 37] PDL ns [35,, 37] t PDLL ns t EA [35,, 37] ns t ER [35, 38] ns Input Register Parameters t WL ns t WH ns t IS ns t IH ns [35,, 37] t ICO ns [35,, 37] t ICOL ns Synchronous Clocking Parameters [, 37] t CO [39] 6.5 [4] 8 [4] ns [35] t S [39] 6 [4] 8 [4] ns t H ns [35,, 37] t CO ns [35] t SCS [39] 2 5 ns t SL [35] ns t HL ns Notes 34. All AC parameters are measured with two outputs switching and 35 pf AC Test Load. 35. Logic blocks operating in low power mode, add t LP to this specification.. Outputs using Slow Output Slew Rate, add t SLEW to this specification. 37. When = 3.3V, add t 3.3IO to this specification. 38. t ER measured with 5 pf AC Test Load and t EA measured with 35 pf AC Test Load. 39. For reference only, the following values correspond to the obsolete CY3752 devices: t CO = 5 ns, t S = 6.5 ns, t SCS = 8.5 ns, t ICS = 8.5 ns, f MAX = 8 MHz. 4. The following values correspond to the CY3792V and CY37256V devices: t CO = 6 ns, t S = 7 ns, f MAX2 = 43 MHz, f MAX3 = 77 MHz, and f MAX4 = MHz; and for the CY3752 devices: t S = 7 ns. 4. For reference only, the following values correspond to the obsolete CY3752V devices: t CO = 6.5 ns, t S = 9.5 ns, and f MAX2 = 5 MHz. Min Max Min Max Min Max Min Max Unit Document Number: Rev. *I Page 27 of 5

28 Switching Characteristics (continued) Over the Operating Range Parameter [34] 2 MHz 7 MHz 54 MHz 43 MHz 25 MHz MHz 83 MHz 66 MHz Min Max Product Term Clocking Parameters t COPT [42, 43, 44] ns t SPT ns t HPT ns [42] t ISPT ns t IHPT ns t CO2PT [42, 43, 44] ns Pipelined Mode Parameters t ICS [42] [45] 2 5 ns Operating Frequency Parameters Min Max Min Max Min Max f MAX [45] MHz f MAX [46] 25 [47] MHz f MAX [46] MHz f MAX MHz Reset/Preset Parameters t RW ns t [42] RR ns Min Max Min Max Min Max Min Max Unit Notes 42. Logic blocks operating in low power mode, add t LP to this specification. 43. Outputs using Slow Output Slew Rate, add t SLEW to this specification. 44. When = 3.3V, add t 3.3IO to this specification. 45. For reference only, the following values correspond to the obsolete CY3752 devices: t CO = 5 ns, t S = 6.5 ns, t SCS = 8.5 ns, t ICS = 8.5 ns, f MAX = 8 MHz. 46. The following values correspond to the CY3792V and CY37256V devices: t CO = 6 ns, t S = 7 ns, f MAX2 = 43 MHz, f MAX3 = 77 MHz, and f MAX4 = MHz; and for the CY3752 devices: t S = 7 ns. 47. For reference only, the following values correspond to the obsolete CY3752V devices: t CO = 6.5 ns, t S = 9.5 ns, and f MAX2 = 5 MHz. Document Number: Rev. *I Page 28 of 5

29 Switching Characteristics (continued) Over the Operating Range Parameter [34] 2 MHz 7 MHz 54 MHz 43 MHz 25 MHz MHz 83 MHz 66 MHz Min Max Min Max Min Max Min Max t RO [48, 49, 5] ns t PW ns t PR [48] ns t PO [48, 49, 5] ns User Option Parameters t LP ns t SLEW ns t [5] 3.3IO ns JTAG Timing Parameters t S JTAG ns t H JTAG ns t CO JTAG ns f JTAG MHz Min Max Min Max Min Max Min Max Unit Notes 48. Logic blocks operating in low power mode, add t LP to this specification. 49. Outputs using Slow Output Slew Rate, add t SLEW to this specification. 5. When = 3.3V, add t 3.3IO to this specification. 5. Only applicable to the 5 V devices. Document Number: Rev. *I Page 29 of 5

30 Switching Waveforms Figure 5. Combinatorial Output INPUT t PD COMBINATORIAL OUTPUT Figure. Registered Output with Synchronous Clocking INPUT t S t H SYNCHRONOUS CLOCK REGISTERED OUTPUT REGISTERED OUTPUT SYNCHRONOUS CLOCK INPUT t WH Figure 7. Registered Output with Product Term Clocking Input Going Through the Array t CO t WL t CO2 t SPT t HPT PRODUCT TERM CLOCK t COPT REGISTERED OUTPUT Document Number: Rev. *I Page 3 of 5

31 Switching Waveforms (continued) Figure 8. Registered Output with Product Term Clocking Input Coming From Adjacent Buried Register INPUT t ISPT t IHPT PRODUCT TERM CLOCK t CO2PT REGISTERED OUTPUT Figure 9. Latched Output INPUT LATCH ENABLE LATCHED OUTPUT REGISTERED INPUT INPUT REGISTER CLOCK t PDL t SL t HL Figure 2. Registered Input t IS t IH t CO t ICO COMBINATORIAL OUTPUT t WH t WL CLOCK Figure 2. Clock to Clock INPUT REGISTER CLOCK t ICS t SCS OUTPUT REGISTER CLOCK Document Number: Rev. *I Page 3 of 5

32 Switching Waveforms (continued) Figure 22. Latched Input LATCHED INPUT t IS t IH LATCH ENABLE t PDL t ICO COMBINATORIAL OUTPUT t WH t WL LATCH ENABLE LATCHED INPUT LATCHED OUTPUT INPUT LATCH ENABLE OUTPUT LATCH ENABLE Figure 23. Latched Input and Output t PDLL t ICOL t SL t ICS t HL t WH t WL LATCH ENABLE Figure 24. Asynchronous Reset t RW INPUT t RO REGISTERED OUTPUT t RR CLOCK Document Number: Rev. *I Page 32 of 5

33 Switching Waveforms (continued) Figure 25. Asynchronous Preset t PW INPUT REGISTERED OUTPUT t PO t PR CLOCK Figure 26. Output Enable/Disable INPUT OUTPUTS t ER t EA Document Number: Rev. *I Page 33 of 5

34 Power Consumption Typical 5 V Power Consumption CY High Speed 5 4 Low Power Icc (ma) 3 2 CY Frequency (MHz) The typical pattern is a -bit up counter, per logic block, with outputs disabled. V CC = 5V, T A = Room Temperature High Speed Icc (ma) 5 4 Low Power Frequency (MHz) The typical pattern is a -bit up counter, per logic block, with outputs disabled. V CC = 5V, T A = Room Temperature Document Number: Rev. *I Page 34 of 5

35 Typical 5 V Power Consumption (continued) CY High Speed 2 Icc (ma) 8 Low Power CY3792 Icc (ma) Frequency (MHz) The typical pattern is a -bit up counter, per logic block, with outputs disabled. V CC = 5V, T A = Room Temperature Low Power High Speed Frequency (MHz) The typical pattern is a -bit up counter, per logic block, with outputs disabled. V CC = 5V, T A = Room Temperature Document Number: Rev. *I Page 35 of 5

36 Typical 5 V Power Consumption (continued) CY High Speed 25 2 Low Power Icc (ma) Frequency (MHz) The typical pattern is a -bit up counter, per logic block, with outputs disabled. V CC = 5V, T A = Room Temperature Document Number: Rev. *I Page of 5

37 Typical 3.3 V Power Consumption CY3732V 3 High Speed 25 Low Power 2 Icc (ma) 5 5 CY3764V Icc (ma) Frequency (MHz) The typical pattern is a -bit up counter, per logic block, with outputs disabled. V CC = 3.3V, T A = Room Temperature Low Power High Speed Frequency (MHz) The typical pattern is a -bit up counter, per logic block, with outputs disabled. V CC = 3.3V, T A = Room Temperature Document Number: Rev. *I Page 37 of 5

38 Typical 3.3 V Power Consumption (continued) CY3728V 8 High Speed Low Power Icc (ma) CY3792V Icc (ma) Frequency (MHz) The typical pattern is a -bit up counter, per logic block, with outputs disabled. V CC = 3.3V, T A = Room Temperature Low Power High Speed Frequency (MHz) The typical pattern is a -bit up counter, per logic block, with outputs disabled. V CC = 3.3V, T A = Room Temperature Document Number: Rev. *I Page 38 of 5

39 Typical 3.3 V Power Consumption (continued) CY37256V 4 2 High Speed Icc (ma) 8 6 Low Power Frequency (MHz) The typical pattern is a -bit up counter, per logic block, with outputs disabled. V CC = 3.3V, T A = Room Temperature Document Number: Rev. *I Page 39 of 5

40 Ordering Information 5 V Ordering Information Macrocells Speed (MHz) Ordering Code Package Name Package Type Operating Range CY3732P44-54AXI A44 44-pin TQFP (Pb-free) Industrial 25 CY3732P44-25AXC A44 44-pin TQFP (Pb-free) Commercial CY3732P44-25JXC J67 44-pin PLCC (Pb-free) CY3764P44-25AXC A44 44-pin TQFP (Pb-free) Commercial CY3764P44-25JXC J67 44-pin PLCC (Pb-free) CY3764P-25AXC A -pin TQFP (Pb-free) CY3764P44-25AXI A44 44-pin TQFP (Pb-free) Industrial CY3764P-25AXI A -pin TQFP (Pb-free) CY3728P-25AXC A -pin TQFP (Pb-free) Commercial CY3728P-25AXC A -pin TQFP (Pb-free) CY3728P-25AXI A -pin TQFP (Pb-free) Industrial CY3728P-25AXI A -pin TQFP (Pb-free) CY3728P-AXC A -pin TQFP (Pb-free) Commercial CY3792P-83AXC A -pin TQFP (Pb-free) Commercial CY3792P-83AXI A -pin TQFP (Pb-free) Industrial CY37256P-25AXC A -pin TQFP (Pb-free) Commercial CY37256P-25AXI A -pin TQFP (Pb-free) Industrial 83 CY37256P-83AXC A -pin TQFP (Pb-free) Commercial CY37256P-83AXI A -pin TQFP (Pb-free) Industrial 3.3 V Ordering Information Macrocells Speed (MHz) Ordering Code Package Name Package Type Operating Range CY3732VP44-43AXC A44 44-pin TQFP (Pb-free) Commercial CY3732VP44-AXC A44 44-pin TQFP (Pb-free) 64 CY3764VP44-AXC A44 44-pin TQFP (Pb-free) Commercial CY3728VP-25AXC A -pin TQFP (Pb-free) Commercial 83 CY3728VP-83AXI A -pin TQFP (Pb-free) Industrial Document Number: Rev. *I Page 4 of 5

41 Ordering Code Definitions C Y V P - 25 A X C Cypress Semiconductor ID Family Type 37 = Ultra37 Family Macrocell Density 32 = 32 Macrocells 92 = 92 Macrocells 64 = 64 Macrocells 256 = 256 Macrocells 28 = 28 Macrocells Operating Reference Voltage V = 3.3V Supply Voltage (5.V if not specified) Pin Count P44 = 44 Pins P = Pins P = Pins P256 = 256 Pins Operating Conditions Commercial C to +7 C Industrial -4 C to +85 C Lead Free X = Pb free Package Type A = Thin Quad Flat Pack (TQFP) J = Plastic Leaded Chip Carrier (PLCC) BB = Fine-Pitch Ball Grid Array (FBGA). mm Lead Pitch Speed 2 = 2 MHz 7 = 7 MHz 54 = 54 MHz 43 = 43 MHz 25 = 25 MHz = MHz 83 = 83 MHz 66 = 66 MHz Document Number: Rev. *I Page 4 of 5

42 Package Diagrams Figure pin TQFP (.4 mm) A44S Package Outline, Figure pin PLCC J44 Package Outline, *E *C Document Number: Rev. *I Page 42 of 5

43 Package Diagrams (continued) Figure 29. -pin TQFP (4 4.4 mm) ASA Package Outline, Figure 3. -pin TQFP ( mm) ASA Package Outline, *G *D Document Number: Rev. *I Page 43 of 5

44 Package Diagrams (continued) Figure ball FBGA (7 7.7 mm) BB256/BWBD Package Outline, *I Document Number: Rev. *I Page 44 of 5

45 Acronyms Acronym Description ATE automatic test equipment CMOS complementary metal oxide semiconductor CPLD complex programmable logic device FBGA fine-pitch ball grid array I/O input/output ISR in-system reprogrammable JEDEC joint electron devices engineering council JTAG joint test action group OE output enable PC personal computer PCI peripheral component interconnect PIM programmable interconnect matrix PLCC plastic leaded chip carrier TDI test data-in TDO test data-out TQFP thin quad flat pack TTL transistor-transistor logic Document Conventions Units of Measure Symbol Unit of Measure C degree Celsius MHz megahertz µa microampere mm millimeter ms millisecond nh nanohenry ns nanosecond ohm % percent pf picofarad V volt W watt Document Number: Rev. *I Page 45 of 5

46 Document History Page Document Title: Ultra37 CPLD Family, 5 V and 3.3 V ISR High Performance CPLDs Document Number: Rev. ECN No. Submission Date Orig. of Change Description of Change ** /8/ SZV Change from Spec number: to *A /2/3 OOR Updated 3.3V V CC requirements for 44 speeds Added an Addendum *B /9/3 TEH Changed pinout for CY3728V BB package *C //3 HOM Obsoleted following 3.3V PLCC packaged devices: CY3732VP44-43JC CY3732VP44-JC CY3732VP44-JI CY3764VP44-43JC CY3764VP84-43JC CY3764VP44-JC CY3764VP84-JC CY3764VP44-JI CY3764VP84-JI CY3728VP84-25JC CY3728VP84-83JC CY3728VP84-83JI *D /8/4 YDT Changed package diagrams and labels for consistency Added Pb-free logo on first page, and a note in Features Added Pb-free package diagram labels Added Pb-free Parts to Ordering Information CY3732P44-2AXC, CY3732P44-2JXC, CY3732P44-54AXI, CY3732P44-54JXI, CY3732P44-25AXC, CY3732P44-25JXC, CY3764P44-2AXC, CY3764P44-2JXC, CY3764P-2AXC, CY3764P44-54AXI, CY3764P44-54JXI, CY3764P44-25AXC, CY3764P44-25JXC, CY3764P-25AXC, CY3764P44-25AXI, CY3764P-25AXI, CY3728P84-7JXC, CY3728P-7AXC, CY3728P-7AXC, CY3728P84-25JXC, CY3728P-25AXC, CY3728P-25AXC, CY3728P84-25JXI, CY3728P-25AXI, CY3728P-25AXI, CY3728P84-JXC, CY3728P-AXC, CY3728P-AXC, CY3728P-AXI, CY3792P-54AXC, CY3792P-25AXC, CY3792P-25AXI, CY3792P-83AXC, CY3792P-83AXI, CY37256P-54AXC, CY37256P-25AXC, CY37256P-25AXI, CY37256P-83AXC, CY37256P-83AXI, CY3732VP44-43AXC, CY3732VP44-AXC, CY3732VP44-AXI, CY3732VP44-JXI, CY3764VP44-43AXC, CY3764VP-43AXC, CY3764VP44-AXC, CY3764VP-AXC, CY3764VP44-AXI, CY3764VP-AXI, CY3728VP-25AXC, CY3728VP-25AXC, CY3728VP-25AXI, CY3728VP-83AXC, CY3728VP-83AXC, CY3728VP-83AXI, CY3728VP-83AXI, CY3792VP-AXC, CY3792VP-66AXC, CY37256VP-AXC, CY37256VP-AXI, CY37256VP-66AXC *E /4/5 PCX Added Package Diagram BG292 Updated all PBGA package type information (BG292 & BG388) Document Number: Rev. *I Page 46 of 5

47 Document History Page (continued) Document Title: Ultra37 CPLD Family, 5 V and 3.3 V ISR High Performance CPLDs Document Number: Rev. ECN No. Submission Date Orig. of Change Description of Change *F /4/9 AAE a.in the features section, reduced the maximum number of pins from 4 to 256 in reference to current package pin count in production. b. 5V Selection Guide: Removed CY37384 and CY3752 options from the general information table, removed CY37384 and CY3752 options from the Speed Bins table, removed all in-active speed bin options, removed all in-active device-package offering and I/O count options. c. 3.3V Selection Guide: Removed CY37384V and CY3752V options from the general information table, removed CY37384V and CY3752V options from the Speed Bins table, removed all in-active speed bin options, removed all in-active device-package offering and I/O count options. d. Updated the development software support specific to Programming in which the CY37i (ISR Programming Kit) reference had been replaced with the CYUSBISRPC Programming Cable User s Guide. e. Logic diagrams: Removed references to CY37384/ CY37384V and CY3752/ CY3752V. f. 5V Device Electrical Characteristics specific to the Inductance table: Removed 44 pin CLCC, 84 pin PLCC, 84 pin CLCC and 28 pin PQFP from the table. g. 3.3V Device Electrical Characteristics specific to the Inductance table: Removed 44 pin CLCC, 84 pin PLCC, 84 pin CLCC and 28 pin PQFP from the table. h. Note : Updated CY3764VP-AC to CY3764VP-AXC and CY3764VP44-43AC to CY3764VP44-43AXC. Removed references to CY3764VP-43BBC and CY3764VP48-43BAC because these are obsolete device-package options. i. Note : Removed CY37384 device as a reference. j. Note 8: Removed CY37384V device as a reference. k. Power Consumption graphs: Removed reference graphs for CY37384, CY3752, CY37384V and CY3752V. l. Pin Configurations: Removed reference pin-outs for 44 Pin CLCC, 48B FBGA, 84 Pin PLCC, 84 Pin CLCC, B FBGA, pin CQFP, 28 pin CQFP, 28 pin PQFP, 292B PBGA, 388B PBGA, and 4B FBGA. Document Number: Rev. *I Page 47 of 5

48 Document History Page (continued) Document Title: Ultra37 CPLD Family, 5 V and 3.3 V ISR High Performance CPLDs Document Number: Rev. ECN No. Submission Date Orig. of Change Description of Change *F (cont) /4/9 AAE m. Updated the 5 V Ordering Information: Removed the following obsolete part numbers: CY3732P44-2AC, CY3732P44-2AXC, CY3732P44-2JC, CY3732P44-2JXC, CY3732P44-54AC, CY3732P44-54JC, CY3732P44-54AI, CY3732P44-54JI, CY3732P44-54JXI, CY3732P44-25AC, CY3732P44-25JC, CY3732P44-25AI, CY3732P44-25JI, CY3764P44-2AC, CY3764P44-2AXC, CY3764P44-2JC, CY3764P44-2JXC, CY3764P84-2JC, CY3764P-2AC, CY3764P44-54AC, CY3764P44-54JC, CY3764P84-54JC, CY3764P-54AC, CY3764P44-54AI, CY3764P44-54JI, CY3764P-54AI, CY3764P44-25AC, CY3764P44-25JC, CY3764P84-25JC, CY3764P-25AC, CY3764P44-25AI, CY3764P44-25JI, CY3764P84-25JI, CY3764P-25AI, QYA, CY3728P84-7JC, CY3728P84-7JXC, CY3728P-7AC, CY3728P-7AXC, CY3728P-7AC, CY3728P84-25JC, CY3728P84-25JXC, CY3728P-25AC, CY3728P-25AC, CY3728P84-25JI, CY3728P84-25JXI, CY3728P-25AI, CY3728P-25AI, QYA, CY3728P84-JC, CY3728P84-JXC, CY3728P-AC, CY3728P-AC, CY3728P84-JI, CY3728P-AI, CY3728P-AXI, CY3728P-AI, QYA, CY3792P-54AC, CY3792P-54AXC, CY3792P-25AC, CY3792P-25AI, CY3792P-83AC, CY3792P-83AI, CY37256P-54AC, CY37256P-54AXC, CY37256P28-54NC, CY37256P256-54BGC, CY37256P-25AC, CY37256P28-25NC, CY37256P256-25BGC, CY37256P-25AI, CY37256P28-25NI, CY37256P256-25BGI, QZC, CY37256P-83AC, CY37256P28-83NC, CY37256P256-83BGC, CY37256P-83AI, CY37256P28-83NI, CY37256P256-83BGI, CY37384P28-25NC, CY37384P256-25BGC, CY37384P28-83NC, CY37384P256-83BGC, CY37384P28-83NI, QZC, CY37384P256-83BG, CY3752P28-25NC, CY3752P256-25BGC, CY3752P28-NC, CY3752P256-BGC, CY3752P352-BGC, CY3752P28-NI, CY3752P256-BGI, CY3752P352-BGI, QZC, CY3752P28-83NC, CY3752P256-83BGC, CY3752P352-83BGC, CY3752P28-83NI, CY3752P256-83BGI, CY3752P352-83BGI, QZC. Document Number: Rev. *I Page 48 of 5

49 Document History Page (continued) Document Title: Ultra37 CPLD Family, 5 V and 3.3 V ISR High Performance CPLDs Document Number: Rev. ECN No. Submission Date Orig. of Change Description of Change *F (cont) /4/9 AAE n. Updated the 3.3V Ordering Information: Removed the following obsolete part numbers: CY3732VP44-43AC, CY3732VP48-43BAC, CY3732VP44-AC, CY3732VP48-BAC, CY3732VP44-AI, CY3732VP44-AXI, CY3732VP48-BAI, CY3732VP44-JI, CY3732VP44-JXI, CY3764VP44-43AC, CY3764VP48-43BAC, CY3764VP-43AC, CY3764VP-43BBC, CY3764VP44-AC, CY3764VP48-BAC, CY3764VP-AC, CY3764VP-BBC, CY3764VP44-AI, CY3764VP44-AXI, CY3764VP48-BAI, CY3764VP-BBI, CY3764VP-AI, QYA, CY3728VP-25AC, CY3728VP-25BBC, CY3728VP-25AC, CY3728VP-25AI, CY3728VP-83AC, CY3728VP-83BBC, CY3728VP-83AC, CY3728VP-83AI, CY3728VP-83BBI, CY3728VP-83AI, QYA, CY3792VP-AC, CY3792VP-66AC, CY3792VP-66AI, CY37256VP-AC, CY37256VP28-NC, CY37256VP256-BGC, CY37256VP256-BBC, CY37256VP-AI, CY37256VP-66AC, CY37256VP28-66NC, CY37256VP256-66BGC, CY37256VP-66AI, CY37256VP256-66BGI, QZC, CY37384VP28-83NC, CY37384VP256-83BGC, CY37384VP28-66NC, CY37384VP256-66BGC, CY37384VP28-66NI, CY37384VP256-66BGI, CY3752VP28-83NC, CY3752VP256-83BGC, CY3752VP352-83BGC, CY3752VP4-83BBC, CY3752VP28-66NC, CY3752VP256-66BGC, CY3752VP352-66BGC, CY3752VP4-66BBC, CY3752VP28-66NI, CY3752VP256-66BGI, CY3752VP352-66BGI, CY3752VP4-66BBI, QZC. *F (cont) /4/9 AAE o. Updated package diagram drawing revisions on the following: , 5-853, p. Removed package diagram drawing references for obsoleted part numbers: 44 pin CLCC (5-84), 48FBGA (5-859), 84 pin CLCC (5-895), B FBGA (5-857), pin CQFP (5-86), 28 pin PQFP (5-8569), 28 pin CQFP (5-85), 292B PBGA (5-8597), 388B PBGA (5-853), 4B FBGA (5-85). q. Addendum for 3.3V Operating Range: Updated CY3764VP-AC to CY3764VP-AXC and CY3764VP44-43AC to CY3764VP44-43AXC. Removed references to CY3764VP-43BBC and CY3764VP48-43BAC because these are obsolete device-package options. r. Removed Military Operating Range because all Military Part numbers have been obsoleted. *G /9/2 AAE Removed inactive parts from Ordering Information. Updated Table of Contents. Updated Packaging Information. Updated links in Sales, Solutions, and Legal Information. *H 3892 /9/2 AAE Updated Ordering Information and Ordering Code Definitions. Minor edits. *I /23/22 AAE Updated Package Diagrams (spec (Changed revision from *D to *E), spec (Changed revision from *B to *C), spec (Changed revision from *D to *G), spec (Changed revision from *C to *D), spec (Changed revision from *H to *I)). Added Acronyms and Units of Measure. Updated in new template. Document Number: Rev. *I Page 49 of 5

50 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/psoc cypress.com/go/touch cypress.com/go/usb cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC PSoC 3 PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: Rev. *I Revised August 23, 22 Page 5 of 5 ViewDraw and SpeedWave are trademarks of ViewLogic. Windows is a registered trademark of Microsoft Corporation. Warp is a registered trademark, and In-System Reprogrammable, ISR, Warp Professional, Warp Enterprise, and Ultra37 are trademarks, of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.