Lab 5. Using Fpro SoC with Hardware Accelerators Fast Sorting
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1 Lab 5 Using Fpro SoC with Hardware Accelerators Fast Sorting Design, implement, and verify experimentally a circuit shown in the block diagram below, composed of the following major components: FPro SoC platform available source codes:
2 1. Microblaze MCU 2. RAM 3. Memory controller 4. Clock management circuit 5. FPro bridge 6. MMIO controller 7. Timer 8. GPI (General Purpose Input) and GPI2 9. GPO (General Purpose Output) and GPO2 Customized hardware accelerator: 1. Sorting IP: Hardware implementation of Fast sort algorithm Sorting IP should include a Nx8 DATA RAM which is used to store the array of 8-bit values to be sorted by this IP. By default N should be equal to 256. During configuration, 256x8 RAM should be initialized to values {"00", "01",..., "FE", FF"}, i.e., the value at each location should be equal to the address of that location. Task 1 Browsing Mode (default mode):
3 In the Browsing Mode, the circuit should display Current Address (using Seven Segment Displays 3 and 2) Value in Data RAM at position given by the Current Address (using Seven Segment Displays 1 and 0). Button Up should increment the Current Address in the wrap-around fashion ("FF" followed by "00"). Button Down should decrement the Current Address in the wrap-around fashion ("00" followed by "FF"). Task 2 Initialize in Software:
4 In this mode, each time Button Left is pressed, the entire Data memory stored in the Processor s RAM should be initialized with N pseudorandom values generated in software using a Pseudorandom Number Generator. Two identical copies of the Data memory should be created, one used for software sorting and another used for hardware sorting. When the initialization is completed, the system should return to the browsing mode. Task 3 Sorting:
5 Pressing Center Button should initiate sorting. Sorting should be performed in software and hardware. Sorting in software should be performed on the array stored in the Processor memory. Sorting in hardware should involve transferring input data to the Sorting Unit, performing sorting, and transferring results back to the Processor memory. The processed numbers should be treated as signed numbers, and should be sorted in the descending order. During sorting ---- should be displayed on the seven segment displays. Task 4 Cycle Count Display Mode: After sorting the total number of clock cycles used for sorting should be displayed on the seven segment displays. The position of switch S7 should indicate whether the least significant 16 bits of the Cycle Counter (for S7=0), or the most significant 16 bits of the Cycle Counter (for S7=1) should be displayed. Pressing any button (other than Center) after sorting, should bring the circuit back to the browsing mode. Task 5 size of Memory to Initialize & Sort:
6 Switch S5... S0 should indicate log $ of the number of elements to initialize and sort by the software or hardware. Here are the suggested values for for different modes of operation: 1. Debugging: 4 (16 elements) 2. Demo: 8 (256 elements) 3. Timing measurements to be included in the report: 8 16 (from 256 to 64k elements) Perform the following tasks to verify the correctness of your designs: Write C/C++ code for fast sorting algorithm and verify it s operation. You can use Xilinx SDK which is installed on your machine as a part of Vivado package to compile and debugging your C/C++ code. Write VHDL code for the fast sort algorithm and the required Data memory. Write a testbench to verify the operation of hardware implementation of fast sort algorithm and perform functional simulation. Synthesize your design together with FPro subsystem and all required available VHDL code. Implement your code using the customized Basys3 XDC file for this project. Check the timing report and make sure there is no timing violation. Generate the.elf file and load it in Vivado. Generate the bitstream and program the FPGA board. Verify experimentally the correct operation of your circuit. Deliverables: 1. VHDL Code for the sorting accelerator IP. 2. C/C++ Code for the fast sorting algorithm implemented in MicroBlaze. 3. VHDL Code of the Entire System (including code accompanying the textbook). 4. Entire C/C++ Code Used (including code accompanying the textbook). 5. Constraints files for the entire system. 6. Report file. Note: Make sure to create a separate directory for each deliverable mentioned above. Report File: 1. List of fully completed tasks. 2. List of partially completed tasks, including the description of any missing functionality. 3. Table showing for each number of memory elements between 2 & and 2 $' (powers of 2 only): a. Execution time in software (clock cycles & ms). b. Execution time in hardware (clock cycles & ms). c. Ratio of the execution time in software vs. hardware.
7 Bonus Task Contest for the Fastest Implementation of Sorting: Bonus points will be awarded to students who perform sorting (correctly) using the smallest number of clock cycles in hardware and/or software. Possible optimizations: Faster sorting algorithms in software Efficient C implementation Faster sorting algorithms in hardware Efficient VHDL implementation Tuesday Section Wednesday Section Friday Section Hands-on Sessions and Introductions to the Experiment Demonstration and Deliverables 04/10/ /11/ /13/ /01/ /02/ /04/2018
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