5 th HERD workshop CERN. Presentation of scmos in IsCMOS Sub-System. Jiarui GAO XIOPM, CAS

Transcription

1 5 th HERD workshop CERN Presentation of scmos in IsCMOS Sub-System Jiarui GAO XIOPM, CAS

2 Outline Background scmos Design Next step 2

3 Background scmos is the readout module of IsCMOS. IsCMOS is the calorimeter s readout system of HERD. + About 7500 cubes of LYSO crystals, 2 outputs for every LYSO crystal to IsCMOS CALO Shifting Fibers Shifting Fibers HighRange IsCMOS LowRange IsCMOS Image pre- Proce ssor Lossle ss Image Compre ssion IsCMOS Camera Satellite -ground Data trans Image processing 3

4 Background done Beam test at CERN successfully. 4

5 Background Beam test at CERN is going with IsCMOS Sub-System. 5

6 Background Progress made by scmos as compared to the 2015 CCD sub-system: Electronic Shutter Better Dynamic Range Lower Noise Better Linearity for Energy Measurement Better Pixel response uniformity 6

7 scmos Design: Why scmos High resolution Low noise Rapid frame CMOS SCMOS CCD Large view High QE EMCCD Wide dynamic Unlike previous generations of CMOS, EMCCD and CCD-based sensors, SCMOS is uniquely capable of simultaneously offering: Extremely low noise Rapid frame rates High quantum efficiency (QE) Wide dynamic range Large field of view High resolution 7

8 scmos Design: Why scmos Read noise<2e - Focal Plane Resolution vs. Input Illumination Dark current Quantum efficiency 8

9 scmos Design: composition of scmos sensor 9

10 scmos Design: specificantion Spectral response range: 450nm~600nm Read noise: <2e- Peak frame rate: exposure time Buffer capability: 4GB (it works when average speed bigger than 275fps) Full-well capacity: Power consumption: 70W Total weight: ~4kg 10

11 scmos Design: composition of scmos Module 11

12 scmos Design: DR vs. Sensitivity Pixels clipped Pixels well balanced Loss of DR 12

13 scmos Design: scmos working with I.I. IIT Gating -150V : Open Event window Camera Triger scmos exposure Exposure time 1.2ms When the trigger occurs, the II closed and the scmos starts its Exposure Period. And after the exposure period, the scmos module switch on the II to wait next trigger. The trigger width must bigger than 100ns. 13

14 scmos Design: Bandwidth vs. RT Processing Original data coming out of the scmos is about 65Gbit per second. In the scmos module, it have to deal with such numerous data. After the processing logic and circuits, the data reduced to 10Gbit per second. Below is the architecture of the FPGA real time processor. 14

15 scmos Design: Verification & Validation 15

16 scmos Design: Verification & Validation 16

17 Next Step: Moore Law still works Shrinking Chips Number and length of transistors bought per $ Source: Intel, 2012 Source: Samsung foundry, 2016 Moore Law: The number of transistors doubles every 18 months. 17

18 Next Step: Sensors will be better and better 16/14nm FinFET Technology (3D transistor architecture) 20nm Technology 28nm Technology(Low-Power/High-Performance) LELE/LLE 40nm Technology(low-power/high-performance/flash) HKMG Layout decomposition 55nm Technology (LP/HP/RF/HV /CIS/flash) APF LEC FCVD STI gap fill 55nm Baseline <100> /(110) U-shape esige Σ-shape esige SiC <100> /(100) Immersion ArF STI Twin-well S/D Laser Anneal SPT Vulcan Elevated S/D ISSG/DPN gate oxide Pre-Doped poly gate Dual Gate Module Spacer SMT BDII Single Damascene NiSi Laser Anneal M0 Local connection S/D Spike MIM BDI 1XDD Ni-Pt USG Silicide 2XDD USG CESL 4XDD Anneal Passivation BDI Single and Damascene Al pad UTM OPC Inductor MHM BDII DFM 1XDD ALD OX+Harp STI gap fill MHM BDIII BDIII Single 1XDD(self-align Damascene etch) 18

19 Next Step: scmos benefits from its architechture Mix. Signal Pixel Array Interface(SERDE S or MIPI ) Image Signal Processor In the past, most of companies generally integrated the various functional modules of CMOS image sensor into a single chip. This is based on the application of system-onchip design method. Mix. Signal Pixel Array Interface(SERDES or MIPI ) Image Signal Processor Tech. node 55nm 28nm 40nm Tech. node 28nm 14nmFF 20nm System In Package 19

20 Next Step: Back-illuminated scmos The typical frontilluminated scmos sensor architecture (left) relies on the use of microlenses. Backilluminated scmos sensors (right) do not utilize microlenses. 20

21 Next Step: Back-illuminated scmos 21

22 Next Step: Data Processing in Space Sensor Platform Data Buffer NOC/Router Packets Protocol Pixels Binning HDR Energy Mergying Data Package Board1:Data Buffer Board2:Network On Chip Board3:Packets protocol Board4:Pixels binning Board5:HDR Energy Merging Board6:Data Package VPX BackP lane Transfers signals into the final data, wihich can be shown directly as the amount of energy of 3D calorimeter. 22

23 Next steps Back-illuminated scmos development; Realtime Processing development; Performance Optimization; Space adaptation. THANKS! 23