Lecture 4a. CMOS Fabrication, Layout and Simulation. R. Saleh Dept. of ECE University of British Columbia

Transcription

1 Lecture 4a CMOS Fabrication, Layout and Simulation R. Saleh Dept. of ECE University of British Columbia 1

2 Fabrication Fabrication is the process used to create devices and wires. Transistors ndiff, pdiff, wells, poly, transistors, threshold adjust implants Wires contacts, metal1, via, metal2 Fabrication is pretty complex. Give a brief overview of the process, for background. Want to understand origin of layout rules / process parameters The abstractions of the process for the designer (us). 2

3 Making Chips Masks Layout Chips Wafers Chemicals Processing Processed Wafer 3

4 Basic Fabrication Step Two parts: 1) Transfer an image of the design to the wafer 2) Using that image as a guide, create the desired layer on silicon diffusion (add impurities to the silicon) oxide (create an insulating layer) metal (create a wire layer) Use the same basic mechanism (photolithography) to do step 1. Use three different methods to do step 2. Ion Implant - used for diffusion. Shoot impurities at the silicon. Deposition - used for oxide/metal. Usually from chemical vapor deposition (CVD) Grow - used for some oxides. Place silicon in oxidizing ambient. 4

5 Integrated Circuit Fabrication Repeat: Create a layer on the wafer Put a photo-sensitive material (resist) on top of the wafer Optically project an image of the pattern you desire on the wafer Develop the resist Use the resist as a mask to prevent the etch (or other process) from reaching the layer under the resist, transferring the pattern to the layer Remove the resist Key point is that all the chips (die) on the wafer are processed in parallel, and for some chemical steps, many wafers are processed in parallel. 5

6 Photolithography To transfer the pattern onto the wafer, one first needs to have an image to project. While this can be done using some scanning technology directly from the design database to the wafer (like generating a TV picture), it is usually done using a two step process: First a glass plate with a image of the pattern etched in chrome is generated from the design database. This glass plate is called a mask, and serves the same function of a negative in photography. This image is optically projected onto wafer using a projection-aligner which is very much like an enlarger in photography. It projects the image of the mask onto the silicon wafer. This two step process is used since scanning data serially is an expensive step since it takes a long time on an expensive machine. By generating a mask which can print on a large number of wafers, the cost per wafer can be made small. (But implies that you want lots of parts). 6

7 Basic Processing Step 1: Apply material to wafer material to be patterned wafer Step 2: Spin on a photoresistive photoresist material Step 3: Pattern photoresist with UV light through glass mask UV light glass mask soluble photoresist Step 4: Apply specific processing step such as etch, implant, oxidation, after etch away unwanted material removing soluble photoresist Step 5: Wash off resist patterned material 7

8 Making Transistors Cross-sectional View Plan View STI p-well STI n-well STI Apply threshold adjust implant gate oxide gate oxide polysilicon gate polysilicon gate 8

9 Making Transistors (cont d) Cross-sectional View Plan View n+ implant p+ implant polycide salicide 9

10 Final Transistor Structure n+ n+ p+ p+ STI p-well STI n-well STI common substrate 10

11 Structure of NMOS Device V GS + Self-aligned silicide = salicide Polycide Spacers + V DS STI n+ n+ Lightly-doped drain p STI 11

12 Fabrication Information Now that we know what fabrication is trying to do, how do we tell them precisely what to build? GDS-II Design House Layout (Mask Set) Design Rules (layout) Process Parameters (simulation) tapeout Foundry (Fab) We don t care about the real details of the fab, but we have to define the patterning of the layers (that meet their rules) to specify our design. Sometimes knowing more about the fab details is useful when you need to debug a part. 12

13 Layout Design Rule Examples Resolution min. spacing 3λ 3λ 3λ 3λ 3λ min. width rule Alignment min. poly width 2λ min. contact size 2λx2λ poly to diffusion spacing 2λ poly overlap of field 2λ min. contact spacing to gate 2λ min. contact overlap λ 13

14 Transistor Layout Information D A D =Y D x W P D = W NMOS D Y D G W L G B Y S Z S P S = W S A S =Y s x W 14

15 Circuit Simulation with SPICE For deep submicron devices, we must have an elaborate set of device models in SPICE to handle realistic situations when the chip is fabricated To address these issues, we will: Briefly review the most important issues Device modeling history Binning of device sizes Process variations Temperature variations Voltage variations 15

16 MOSFET Modeling 2 basic approaches Physical Empirical parameters make physical sense; mostly extracted from process (tox, Leff, etc.) ; usually few params curves match measured devices well parameters are difficult to understand, and there are lots parameters extracted from carefully measured devices Reality is always a compromise between the two. ***WARNING*** Empirical models can break in unpredictable ways if pushed beyond their characterization space. (but we need them since physics can only help us model to the limits of our knowledge) 16

17 Brief history of Spice MOS models First generation Hspice Level 1, 2, 3 physical analytical models with geometry in model equations Holding onto hand-calculation... Second generation Hspice level 13 (Bsim), 28 ( MetaMOS ), 39(Bsim2) Shift in emphasis to circuit simulation with lots of mathematical conditioning Quality of outcome is highly dependent on parameter extraction methodology Good luck with hand-calculation => BUT served industry well for over 12 years! 17

18 Spice MOS models... the present Second generation models fell apart somewhere between 0.8m and 0.5m There is also a new need: low-voltage design Third generation: Hspice level 49 (Bsim3v3), 55 (EKV) Bsim3 intent was return to simplicity... but... now Bsim3v3 > 100 parameters! Vendors have now figured out how to reliably build Bsim3v3 models You will be using a Bsim3v3 model (or BSIM4 in the future) EKV model developed by EPFL in Switzerland... has promise 18

19 Checking out your models Linear Generate IV Characteristics 19

20 Checking out your models Try out multiple W/L s and compare against measure data Try out NMOS and PMOS devices Check out Ids vs. Vgs to estimate V T Try different temperature ranges Check out Ids vs. Vgs Check out Ids vs. Vbs Check out V T vs. L Check out V T vs. W Run simple timing experiments: compute R eq, Cg, Cj, etc. For analog circuits, need to plot gm, gds, gmbs etc... 20

21 Ids vs. Vgs (NMOS) Plot log(ids) vs. Vgs Examine two regions saturation subthreshold Leakage currents flow when device is completely off Log I DS Leakage Subthreshold Active V GS 21

22 Binning approach to Modeling May need to bin space of models & stay inside covered space Beware of non-physical behavior beyond boundaries! Some model sets were really just developed with minimum L s rather than all possible L s. 22

23 Process Variations So far we have talked about transistors as if all transistors were the same Normal Distribution 1 Not true -- no two are exactly alike Parameters of a fabrication run are generally normally distributed - mean, standard deviation Prob Series1 sigma 23

24 Circuit Parameters We need a way to identify and use the extreme points in parameter distributions (spec limits) Wan to stress circuits at these points Good place to test your design for robustness Define Process Corners: Select appropriate process parameters: Poly linewidth, nmos Vt, pmos Vt, Tox, metal width, oxide thickness Choose operating conditions Operating voltage (die voltage) Temp (0-100 o C die temp) P V T 24

25 Process Corners Group parameters into transistor effects, and operating effects nmos can be slow, typical, fast (S, T, F) pmos can be slow, typical, fast (S, T, F) Temperature can be hot, typical, cold (S, T, F) Vdd can be high, typical, low (F, T, S) Label process corner as nmos, pmos, Temp, Vdd TTTT = typical nmos, typical pmos, room temp, nominal supply SSSS = slow nmos, slow pmos, hot temp, low supply FSSS = fast nmos, slow pmos, hot temp, low supply 25

26 Berkeley Predictive Models What parameters should we use for 65nn, 45nm, etc.? Folks at Berkeley have created a set of predictive models based on the ITRS projections and known trends for MOS devices They are kept on the BPM website and updated each year We will be using these models for our simulations but we should be aware that they have some shortcomings since they are predictive models. Always check out your models before using them! 26