Mixed-Signal&RF -0.18μm. 0.18um Process Feature. 0.18um Process Device Feature. 0.18um Process Key Design Rule. Isolation

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1 Mixed-Signal/RF-0.18μm CSMC 0.18 micron process is process-matched to other foundry. CSMC logic process provide generic and low power process micron process provide 1.8V operation voltage core device, 3.3V or 5V operation voltage IO device process option include native VT device, medium low VT device, isolation NMOS, MIM capacitor, high precision poly resistor, varactor and induct. CSMC provide 90% shrunk and 85% shrunk 0.18 process for customer cost down. CSMC 0.18 micron process provide OTP/MTP process, OTP/MTP process no need extra mask layer. Process Feature Starting Material Well Structure Isolation Gate Poly Source, Drain and Gate Formation ILD Contact IMD Via Metal(6 layers) Capacitor Passivation P-Substrate(8-12ohm.cm) Diffused Twin Wells STI Un-doped Poly Co Silicide BPSG/TEOS/CMP Ti/TiN/Wplug FSG/CMP Ti/TiN/Wplug Ti/TiN/AlCu/Ti/TiN MIM Structure HDP/SiN Process Device Feature Technology Core Voltage 3.3V/5V I/O Voltage 1.8V VT Standard/Medium Low/Native MIM Capacitor 1fF/um2 HR Resistor 1075ohm/sq Inductor Al Varactor Available Dnwell Available Process Key Design Rule Layers 0.18 Width Space Pitch Active GT Contact Metal Inter Via Inter Metal Top Via Top Metal Thick Top Metal (Optional)

2 Process Electrical Design Rule Item Channel Length(um) Vt(V) Ion(uA/um) Ioff(pA/um) 1.8V Stand Vt N/P 0.18/ / / / V Stand Vt N/P 0.35/ / /-300 5V Stand Vt N/P 0.6/ / / V Isolation N V Isolation N V Isolation N V Medium Low Vt N/P 0.3/ / / V Medium Low Vt N V Native Vt N V Native Vt N V Low Power N/P 0.18/ / /-185 3/-2 Brief Flow 0.18 Logic Layer Option Layer Active Photo and Etch RE Photo and Etch Dnwell Photo and imp Nwell Photo and imp Pwell Photo and imp Medium VTN Photo and imp Medium VTP Photo and imp Dual Gate Photo and imp Poly Photo and Etch LVNLDD Photo and imp LVPLDD Photo and imp HVNLDD Photo and imp HVPLDD Photo and imp High Resistor Photo and imp N+ Photo and imp P+ Photo and imp PESD Photo and imp SAB Photo and imp W1 Photo and Etch A1 Photo and Etch Inter Via Photo and Etch Inter Metal Photo and Etch MiM Photo and Etch Top Via Photo and Etch Top Metal Photo and Etch Top Thick Metal Photo and Etch

3 Document List 1. Mask tooling information 2. Electrical design rule 3. Topological Design Rule 4. ESD Protection Guideline IP and Library CSMC 0.18 process CSMC Library include 9 track Standard Library, I/O Library, Memory Complier; 7 track Library. Verisilicon I/O library include: 1. Analog I/O with and without resistors 2. 3-state output configure as bi-directional, open source and open drain 3. Input buffer with pull-up 4. Oscillator I/O 5. Selectable drive strength and speed For In-line I/O library, VeriSilicon have designed a digital testchip to test its ESD performance. The latest ESD report shows that our In-line I/O can pass 2kv HBM and 200v MM. For Stagger I/O library, VeriSilicon have designed a digital testchip to test its ESD performance. The latest ESD report shows that our In-line I/O can pass 2kv HBM and 200v MM process offer Mix/RF PDK files process offer IP include Generic/High Density/Low Power 6T-SRAM,OTP, MTP, 2T-SRAM, ADC/DAC, DC-DC, PLL, POR, OSC, PRG, MMC, Charger, USB1.1 PHY, USB2.0 Device PHY, USB2.0 OTG PHY, Sigma-Delta Stereo Codec, Audio Codec. Soft IP: MCU(LEON3, DP8051, DR80390). Detail IP list, please refer to the following sheet:

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5 0.162/0.153um CSMC provide 90% shrunk and 85% shrunk process for customer cost down. Customer no need change design and decrease chip area. Process Shrink Methodology Summary Original GDS DRC Check Core s IO s Pad Mixed Mode SRAM Non-SRAM Non-ESD ESD Pad CUP MIM Analog IP Resistor SRAM Shrink Rule Special Shrink Guideline Non-Shrink Operation Non-Shrink Operation new GDS Direct Shrink Tapout Verification (by customer) 90% and 85% Shrunk Tapeout Flow Original Database Circuit Simulation & Timing Verification Non-shrink Area Sizing Operation Non-shrinkable Area No Shrinkable? Yes Shrinkable Area 90% Shrink Database x 111.1% 85% Shrink Database x 117.6% Rerouting Customer Side DRC1 () Logic Operation CSMC Side Dummy Generation 90% Shrink Database x 90% 85% Shrink Database x 85% DRC2 (90% Shrink) DRC2 (85% Shrink) OPC (90% Shrink) OPC (85% Shrink) Tapeout DRC3 (90% Shrink) DRC3 (85% Shrink)