Collaborate to Innovate FinFET Design Ecosystem Challenges and Solutions
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1 2013 TSMC, Ltd Collaborate to Innovate FinFET Design Ecosystem Challenges and Solutions
2 2 Agenda Lifestyle Trends Drive Product Requirements Concurrent Technology and Design Development FinFET Design Challenges FinFET Ecosystem Solutions
3 3 Agenda Lifestyle Trends Drive Product Requirements Concurrent Technology and Design Development FinFET Design Challenges FinFET Ecosystem Solutions
4 4 Future Lifestyle Trends Mobile Convergence Augmented Reality Image: FreeDigitalPhotos.net Cloud Computing Image: zh.wikipedia.org Image: public-domain-images.com Ubiquitous Connectivity Image: FreeDigitalPhotos.net Internet of Things
5 5 Enabling Product Requirements Mobile Convergence Augmented Reality Service availability Latency Bandwidth Battery life Connectivity Integration Battery life Form factor Cloud Computing Latency Throughput Performance/ W/ $ Service availability Bandwidth Battery life Ubiquitous Connectivity Connectivity Reliability Battery life Cost Internet of Things TSMC, Ltd
6 6 Enabling Product Functionality Mobile Convergence Augmented Reality CMOS Image Sensor Wireless Transceiver Pico Projector Gyroscope Accelerometer Power Management CMOS Image Sensor Wireless Transceiver Power Management Accelerometer Gyroscope E-Compass Cloud Computing Power Management Wireless Transceiver Power Management Micro-controller Wireless Transceiver Power Management Ubiquitous Connectivity Internet of Things
7 Design Challenges 7 Design Collaboration to Reduce New Technology Challenges Low Power High K Metal Gate Double Patterning FinFET Transistor Multi-Patterning & Spacer Design Enablement To Lower Design Barriers 65nm 40nm 28nm 20nm 16nm 10nm
8 8 Increasing EDA Tools and Feature Sets to Enable Customer Designs Number of Supported EDA Tools and Features by Process Node DFM Custom DFM Custom Simulator IR/EM Simulator IR/EM STA Custom Simulator IR/EM STA APR RCX LVS DRC DFM Custom Simulator IR/EM STA APR RCX LVS DRC DFM Custom Simulator IR/EM STA APR RCX LVS DRC 65 nm 40nm 28nm 20nm 16nm STA APR RCX LVS DRC APR RCX LVS DRC
9 9 Agenda Lifestyle Trends Drive Product Requirements Concurrent Technology and Design Development FinFET Design Challenges FinFET Ecosystem Solutions
10 10 An Ecosystem for Innovation Customer Product Roadmap Design Service Mask Making / OPC Process Definition EDA Enablement Design Enablement Customer Tape-out Design Productization Wafer Fabrication Backend Service IP Enablement Test Chip Validation Customer Product Launch
11 11 Concurrent Technology and Design -- EDA Partner Collaboration EDA Partner Development EDA Ready PDK Enablement Design Solution Definition Design Solution Development Design Solution Certification TSMC Technology Development Process Ready
12 12 Concurrent Technology and Design -- IP Partner Collaboration IP Partner Development IP Ready Process / IP Roadmap Alignment Enablement Kit / Training TSMC 9000 Certification MPW Silicon Validation TSMC Technology Development Process Ready
13 13 Concurrent Technology and Design -- Design Partner Collaboration Design Partner Development Design Ready Technology Optimization TV Plan Design Kits Foundation IP Design Guideline TV Validation Product Tapeout TSMC Technology Development Process Ready
14 14 Concurrent Design & Technology Readiness TSMC-Online Design rules SPICE model Tech files/pdk Design kits Utilities Ref Flow Certified EDA Tools DRC/LVS/RC DFM P&R STA/IR/EM Simulation Layout editor Certified IP Portfolio Foundation IP Interface IP Embedded CPU Embedded GPU Analog IP OTP/MTP Design Tapeout TSMC, Ltd
15 15 Agenda Lifestyle Trends Drive Product Requirements Concurrent Technology and Design Development FinFET Design Challenges FinFET Ecosystem Solutions
16 16 A look back at 50 years of Silicon Julius Blank Eugene Kleiner Robert Noyce Victor Grinich Jay Last Sheldon Roberts Jean Hoerni Gordon Moore
17 17 Transistor to IC First Transistor Bell Labs 1947 First IC TI 1958 First Planar IC Fairchild 1960
18 18 FinFET vs. Planar Characteristics FinFET Benefits Lower leakage Higher driving current Low-voltage operability Better mismatch Higher intrinsic gain FinFET Challenges Higher parasitic capacitance due to 3D profile Higher parasitic resistance due to local interconnect Quantized device widths Planar Device FinFET
19 19 FinFET Value Proposition ~2X gate density improvement compared to 28nm 16nmFinFET offers extra 20% speed same total power or 35% power same speed with similar gate density compared to 20nm 16FF/28HPM 16FF/20SoC same total power 38% 20% Total power same speed 54% 35% Gate density 2X 1.1X
20 20 FinFET Design Enablement Requires Collaboration Among Foundry, EDA and Lead Partners Parasitic RC extraction: 3D profile support, accuracy Design methodology for low voltage operation Design methodology for interconnect resistance minimization EM reliability and power integrity: High drive current 3D
21 21 Agenda Lifestyle Trends Drive Product Requirements Concurrent Technology and Design Development FinFET Design Challenges FinFET Ecosystem Solutions
22 22 FinFET Design Flow Requirements 3D FinFET device structure Advanced SPICE modeling for 3D structure Modeling layout dependent effects in 3D structure Accurate RC extraction Higher parasitic capacitance due to 3D profile Higher parasitic resistance due to local interconnects Quantized device width due to fin pitch/grid requirements PODE device handling in designs, EDA tools and IPs High-drive current leads to EM reliability and power integrity issues
23 23 FinFET EDA Tool Certification Two levels of tool certification Tool certifications as the foundation of FinFET design infrastructure Integrated Tool Certification Using Cortex-A15 Tool Certifications Individual Tool Certification STA P&R DRC LVS FastSpice RC EM IR Custom Design Lib Char
24 24 Summary Technology advancements are driving earlier, wider and deeper ecosystem collaboration to deliver enabling design solutions TSMC s collaborative ecosystem unleashes innovations to address FinFET design challenges TSMC Open Innovation Platform has a proven record of success and is more critical than ever for 16nm and beyond
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