CCD Line Scan Array P-Series High Speed Linear Photodiode Array Imagers 14um, dual output, 2048 and 4096 elements

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CCD Line Scan Array P-Series High Speed Linear Photodiode Array Imagers 14um, dual output, 2048 and 4096 elements - Preliminary INDISTRIAL SOLUTION D A T A S H E E T Description Based on the industry

increasing demands of advanced imaging applications.

1 CCD Line Scan Array P-Series High Speed Linear Photodiode Array Imagers 14um, dual output, 2048 and 4096 elements - Preliminary INDISTRIAL SOLUTION D A T A S H E E T Description Based on the industry standard Reticon arrays, PerkinElmer has combined the best features of high-sensitivity photodiode array detection and highspeed charge coupled scanning to offer an uncompromising solution to the increasing demands of advanced imaging applications. These high performance imagers feature low noise, high sensitivity, impressive charge storage capacity, high speed, and lag-free dynamic imaging in a convenient dual-output architecture. The 14µm square contiguous pixels in these imagers reproduce images with minimum information loss and artefact generation, while their unique photodiode structure provides excellent blue response extending below 400nm and into the ultraviolet. The two-phase CCD readout register requires only 5 volts for clocking yet achieves excellent charge transfer efficiency. Additional electrodes provide independent control of exposure and antiblooming. Finally, the high-sensitivity readout amplifier provides a large output signal to relax noise requirements on the camera electronics that follow. Available in standard array lengths of 2048, and 4096 elements with either glass or UV-enhanced fused silica windows, these versatile imagers are widely used in high-speed document reading, web inspection, mail sorting, production measurement and gauging, position sensing, spectroscopy, and other industrial and scientific applications requiring peak imager performance. P- series imagers combine highperformance photodiodes with high speed CCD readout registers and a highsensitivity readout amplifier. Refer to Figure 1 for functional details. Features and Benefits Extended Spectral Range 200 to 1000nm. 80MHz pixel data rate. Line rates to 37 khz Center-split, dual channel readout > 2,500:1 dynamic range 5 Volt clocking 14um square pixels with 100% fill factor Ultra low image lag Electronic exposure and antiblooming control Applications High-speed document reading Web inspection Mail sorting Production measurement and gauging Position Sensing Spectroscopy Optical Coherence Tomography Imaging

2 Figure 1 Imager Functional Diagram Light Detection Area The light detection area in P-series imagers is a linear array of contiguous pinned photodiodes on 14µm centers. These photodiodes are constructed using PerkinElmer's advanced photodiode design that extends short-wavelength sensitivity into the deep UV below 200nm, while preserving 100% fill factor and delivering extremely low image lag. Figure 2a Spectral Sensitivity Curve This unique design also avoids polysilicon layers in the light detection area that reduces the quantum efficiency of most CCD imagers. The P-series imagers are supplied with glass windows for general visible use, or fused silica windows for use in the UV below 350nm. On a custom basis, P-series imagers can be supplied without an affixed window. See Figures 2a and 2b for Quantum Efficiency/Responsivity and window transmission curves respectively. CCD Line Scan Array 2

3 Figure 2b Window Transmission Curve For lowest lag, all P-series imagers feature pinned photodiodes. Pinning, which requires a special semiconductor process step, provides a uniform internal voltage reference for the charge stored in every photodiode. This stable reference assures that every photodiode is fully discharged after every scan. Photodiodes covered with light shields included at both ends of the imager provide a dark level reference for clamping. These are separated from the active photodiodes by two unshielded transition pixels that assure uniform response out to the last active photodiode. Due to the potential for light leakage, the two dark pixels nearest the transition pixels should not be used as a dark reference. Figure 3 Transfer Timing Diagram CCD Line Scan Array 3

4 Table 1. Transfer Timing Requirements Item Symbol Min. Typical Max. Delay of Ø TG falling edge from Ø PG falling edge t 5 ns 20 ns - 1 Delay of Ø TG rising edge from end of Ø t 0 ns 10 ns H1 2 Delay of Ø AB rising edge from Ø PG falling edge t 5 ns 5 ns - 3 Ø TG pulse width t 500 ns 500 ns - 4 Ø PG pulse width t 400 ns 400 ns - 5 Rise/ fall time t 10 ns 20 ns - 6 Integration time t 0 ns Ø AB pulse width t ns 1 - Delay of Ø 1 falling edge from ØTG falling edge t9-25 ns - Note 1: 750ns is the typical time to fully drain the photodiode - Horizontal Shift Registers Charge packets collected in the photodiodes as light is received are converted to a serialized output stream through a buried channel, two phase CCD shift register that provides high charge transfer efficiency at shift frequencies up to 40MHz. The PerkinElmer 5Volt CCD process used in this design enables low-power, high-speed operation with inexpensive, readily available driver devices. The transfer gate (ØTG) controls the movement of charge packets from the photodiodes to the CCD shift register. During charge integration, the voltage controlling the ØTG is held in its low state to isolate the photodiodes from the shift register. When transfer of charge to the shift register is desired, ØTG is switched to its high state to create a transfer channel between the photodiodes and the shift register. Figure 4 Readout Timing Waveforms After readout of a particular image line (n), the shift register is empty of charge and ready to accept new charge packets from the photodiode representing image line n+1. To begin the CCD Line Scan Array 4

5 transfer sequence, the horizontal clock pulses (ØH1 and ØH2) are stopped with ØH1 held in its high state, and ØH2 in its low state. ØTG is then switched high to start the transfer of charge to the shift register. Once the ØTG reaches its high state, the photo gate voltage (ØPG) is set to high to complete the transfer. It is recommended that the photo gate voltage be held in the high state for at least 0.1µs to ensure complete transfer. After this interval, the photo gate voltage is returned to its low state, and when this is completed, the transfer gate is also returned to its low state. The details of the transfer timing are shown in Figure 3 with ranges in Table 1. After transfer, the charge is transported along the shift register by the alternate action of two horizontal phase voltages ØH1 and ØH2. While the two-phase CCD shift register architecture allows relaxed timing tolerances over those required in three or four-phase, optimum charge transfer efficiency (CTE) and lowest power dissipation is obtained when the overlap of the twophase CCD clocks occurs around the 50% transition level. Additionally, the phase difference between signals ØH1 and ØH2 should be maintained near 180 and the duty cycle should be set near to 50% to prevent loss of full well charge storage capacity and charge transfer efficiency. Readout timing details are shown in Figure 4 with ranges in Table 2. Table 2. Readout Timing Requirements Item Symbol Min. Typical Max. Ø H1 and Ø H2 clock period t ns - - Ø H1 and Ø H2 rise/fall time t 11-5 ns - Ø RG rise/fall time t 12-2 ns - Ø RG clock high duration t 13 2 ns - - Delay of Ø 1 high-to-low tansition from Ø RG low t 14 0 ns - - Note: The cross over point for Ø H1 and Ø H2 clock transitions should occur within the 10-90% level of the clock amplitude. Timing Requirements In high-speed applications, fast waveform transitions allow maximum settling time of the output signal. However, it is generally advisable to use the slowest rise and fall times consistent with required video performance because fast edges tend to introduce more transition noise into the video waveform. When the highest speeds are required, careful smoothing of the waveform transitions may improve the balance between speed and video quality. Table 3. Imager Performance (Typical) Pixel count Pixel size Exposure control Horizontal Clocking 2048 elements (HL2048P) 4096 elements (HL4096P) 14um x 14um yes 2Ø (5V amplitude) CCD Line Scan Array 5

6 Number of outputs 2 Dynamic range > 2,500:1 Readout noise (rms) Amplifier Reset transistor Total noise without CDS 20 electrons 45 electrons 50 electrons Saturation exposure (750 nm) 27nJ/cm 2 Noise equivalent Exposure 8.1pJ/cm 2 Amplifier sensitivity Saturation output voltage Saturation charge capacity 6.0µV/electron 1,100mV 167,000 electrons Charge transfer efficiency > Peak responsivity (w/o window) 41V/µJ/cm 2 PRNU +/- 5% Dead pixels 0 Lag < 0.1% Spectral response range Pixel data rate 200nm to 1,000nm 80MHz Output Amplifier Charge emerging from the last stage of the shift register is converted to a voltage signal by a charge integrator and video amplifier. The integrator, a capacitor created by a floating diffusion, is initially set to a DC reference voltage (VRD) by setting the reset transistor voltage (ØRG) to its high state. To read out the charge, ØRG is pulsed low turning the reset transistor off and isolating the integrator from VRD. The next time ØH1 goes low, the charge packet is transferred to the integrator, where it generates a voltage proportional to the packet size. The reset transistor voltage, ØRG, must reach its low state prior to the high-to-low transition of ØH1. An apparent clipping of the video signal will result if this condition is not satisfied. Figure 4 details the clock waveform requirements and overlap tolerances. The video amplifier buffers the signal from the integrator for output from the imager. Care must be taken to keep the load on this amplifier within its ability to drive highly reactive or low impedance loads. The half power bandwidth into an external load of 10pF is 150MHz. It is recommended that the output video signal be buffered with a wide bandwidth follower or other appropriate amplifier to provide a large Zin to the output amplifier. Keep the external amplifier close to the output pins to minimize stray inductive and capacitive coupling of the output signal that can harm signal quality. CCD Line Scan Array 6

7 Table 4. Operating Voltages Signal Function State Voltage (V) Ø H1 Ø H2 Ø TG Ø PG Ø AB Horizontal Clocks Transfer Gate Photo Gate Antiblooming Gate High Low High Low High Low High Low Min. Typical Max Ø PG High V Output Gate Ø RG Reset Gate High Low V DD Amplifier Voltage Supply V RD Amplifier Reset Drain 9 9 2,3 12 V SS /LS Amplifier Return / Light Shield 0 I DD Amplifier Current 20 ma Note 1: Lower than typical Ø AB High voltage may result in higher PRNU due to semiconductor processing variation. Note 2: Higher than typical V RD voltage setting requires higher Ø RG High voltage. Note 3: Higher than typical V DD voltage could increase amplifier gain with correspinding higher than typical V RD voltage. Exposure Control and Antiblooming An exposure control feature in the P-series imagers supports variable charge accumulation time in the photodiode. When the antiblooming gate voltage (ØAB) is set to its high state, charge is drained from the pixel storage gate to the drain. During normal charge collection in the photodiode, ØAB is set to its low state. Due to the timing requirements of the exposure control mode, charge is always accumulated at the end of the period just before the charge is transferred to the readout register. Figure 3 includes the timing requirements for exposure control with the antiblooming gate. The exposure control timing shown will act on the charge packets that emerge as video data on the next readout cycle. Table 5. Maximum Voltage and Temperature Rating Min Max Units Temperature Storage C Operating C Voltage (with respect to Pin 11 for 2K array) Pins 1, 2, 9, 10, 12, V Pins 3, 4, 7, 8, V CCD Line Scan Array 7

8 Min Max Units Voltage (with respect to Pin 21/22 for 4K array) Pins 1-5, 10-15, V Pins 19, 20, V Precautionary Note: The CCD output pins must never be shorted to either V DD or V SS while power is applied to the device. Catastrophic device failure will result. Imager Performance In P-series imagers each element performs its own function independently while integrating smoothly with the other elements in the array. The photodiodes efficiently transform light to charge, the readout registers accurately transport the charge to the amplifier, and the amplifier delivers a clean, robust signal for use in image processing electronics. While the actual performance of these imagers depends strongly on the details of the electronics and timing the camera provides, their straight-forward implementation requirements facilitate optimum designs. Operating Conditions For optimum performance and longest life, carefully follow the operational requirements of these imagers. Provide stable voltage sources free of noise and variation, and clean waveforms with controlled edges. Protect the imager from electrostatic discharge (ESD) and excessive voltages and temperatures. Do not violate the limits on output register speed or reduce timing margins below the minimums. Table 6. Pinout Description and Capacitance Values of Clocked Phases Typical Function Pin Capacitance (pf) Amplifier Return Reset Drain (A) 50 2 Signal Output (A) Amplifier Return (A) CCD Horizontal Phase 2 (A) Signal Output (A) CCD Horizontal Phase 1 (A) Amplifier Drain Supply (A) No Connection Output Gate (A) 8 6 No Connection No Connection 7 CCD Horizontal Phase 1 (B) No Connection CCD Horizontal Phase 2 (B) No Connection Signal Output (B) No Connection 10 Amplifier Drain Supply Output Gate (B) 8 11 Light Shield / die attach Amplifier Drain Supply (B) 12 Reset Gate (B) Signal Output (B) 7 13 No Connection Amplifier Return (B) No Connection Reset Drain (B) 15 Antiblooming Gate Reset Gate (B) Photo Gate No Connection CCD Line Scan Array 8

9 Typical Function Pin Capacitance (pf) Transfer Gate No Connection Output Gate No Connection 8 19 Reset Gate (A) CCD Horizontal Phase 2 (B) Reset Drain CCD Horizontal Phase 1 (B) Light Shield / die attach 22 Light Shield / die attach 23 CCD Horizontal Phase 1 (A) CCD Horizontal Phase 2 (A) Antiblooming Gate Photo Gate Transfer Gate Reset Gate (A) 7 Imager Configuration All P-series imagers are constructed using ceramic packages and optically-flat windows. Imager die are secured to precision lead frames by thermal silver-filled epoxy. Packages are baked before sealing to eliminate moisture, and tested for seal integrity. Figure 5 Pinout Configuration 2K Array 4K Array CCD Line Scan Array 9

10 Figure 6 Outline Drawings 2K Array 4K Array Table 7. Package Dimensions and Tolerances A B Device Inches mm Inches mm HL2048P / / HL4096P / / Ordering Information The HL2048 and HL4096 P-Series imagers are available with either glass or quartz windows. On special orders, PerkinElmer can supply anti-reflective coated windows or windowless packages. Imagers are individually packaged in electrostatic-resistant boxes and identified by lot number for tracking. CCD Line Scan Array 10

11 Table 8. Stock Part Numbers Active Pixels Window Glass HL2048PAG-021 HL4096PAG-021 Quartz HL2048PAQ-021 HL4096PAQ-021 Note: While the HL P-Series imagers have been designed to resist electrostatic discharge (ESD), they can be damaged from such discharges. Always observe proper ESD precautions when handling and storing this imager. Worldwide Headquarters PerkinElmer Optoelectronics Christy Street European Headquarters Asia Headquarters Fremont, CA PerkinElmer Optoelectronics PerkinElmer Optoelectronics Telephone: Wenzel-Jaksch-Str Ayer Rajah Crescent #06-12 Toll free: (North America) OPTO (6786) Wiesbaden, Germany Singapore Fax: Telephone: (+49) Telephone: (+65) Fax: (+49) Fax: (+65) For a complete listing of our global offices, visit PerkinElmer, Inc. All rights reserved. The PerkinElmer logo and design are registered trademarks of PerkinElmer, Inc. All other trademarks not owned by PerkinElmer, Inc. or its subsidiaries that are depicted herein are the property of their respective owners. PerkinElmer reserves the right to change this document at any time without notice and disclaims liability for editorial, pictorial or typographical errors _01 DTS CCD Line Scan Array 11

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