A Brief Compendium of On Chip Memory Highlighting the Tradeoffs Implementing SRAM,

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1 A Brief Compendium of On Chip Memory Highlighting the Tradeoffs Implementing, RAM, or edram Justin Bates Department of Electrical and Computer Engineering University of Central Florida Orlando, FL Abstract On chip memory or cache is an important piece of technology associated with lower energy consumption and increased system performance. The different configurations and technology types reveal many tradeoffs to be considered for optimizing a system designed for the consumer. The three main types of cache tech, RAM, and edram will be defined, and discussion will reveal what makes them good at their specializations. Fundamental metrics like mapping, associativity, volatile or non-volatile and MOSFETS as well as interesting designs and protocols like MESI will be detailed. By the end of this paper you should gain a deeper understanding of the pros and cons of different cache configurations and reasons behind implementing them. Keywords, Energy Consumption, IPC, Cache Latency, Area overhead, GB,, RAM, edram, Capacity, Protocol, MESI, MOSFET, MTJ, CPU, MLC, Associativity Introduction Cache Configuration has become a large area of research since the introduction of massive amounts of multicore embedded processors in modern societies technology. There is now a demand for lower energy consumption and smaller area overhead while maintaining the lowest possible read and write latency in processor and memory systems [6]. Because of these factors there is a need to implement memory onto the chip itself; known as the CPU cache. CPU cache is a piece of hardware used to access memory faster. Instead of the more time and energy consuming method of going to main memory, the on chip memory is a much better alternative partly because it is so close to the processor. Generally, cache memory contains data that the CPU frequently askes the main memory for and therefore is kept in a more accessible spot. Although cache is a great way to enhance performance of the machine, like any other piece of hardware there are tradeoffs. Certain caches like (static random access memory) have low density and leak a lot of current, whereas RAM (spin-transfer torque magnetic random access memory) generally have high write latency but are smaller physically. RAM is a non-volatile memory type meaning it does not require power to maintain its stored information whereas and edram are volatile and will not save data when the power goes out! edram (embedded dynamic random access memory.) are generally more expensive but have performance advantages [9]. Since there are various types of caches, we can compose a system with multiple levels of cache that complement each other s weaknesses creating an optimal machine for the task at hand. What are some of these caches physically made up of? The way RAM stores data is by use of a magnetic tunnel junction (MTJ). Each cell of the RAM is generally made up of 1 MOSFET (Metal Oxide Semi-Conductor Field Effect Transistor) and a MTJ (Fig.B.). On the contrary the standard cell is composed of six MOSFET s (Fig. A.) which explains the size discrepancy between the two as later discussed []. The edram can have multiple physical makeups including one design that has one MOSFET and one Capacitor or a three MOSFET design [9]. Fig. A. 6 MOSFET design. [9] Page 1 of 5

2 Fig. B. RAM 1 MOSFET 1 MTJ [9] Another tradeoff is organization of cache. Associativity of a cache determines how a cache is set up relative to the main memory. Some types of associativity include direct-mapped, full-associative, and set-associative. How does Direct mapping work? Direct-mapped cache organization allows one location in main memory to connect to one location in the cache. This is also known as one-way set associative and is simpler than other configurations but larger in area overhead. -associative organizations can have multiple locations of the memory associated with one cache. Finally, there is full-associative which has a very high chance of finding the memory since each section of the cache can access any portion of the memory. The downside of this is that searching through many more lines between cache and memory can cause performance issues. The bottom line is more associativity generally means a higher chance to find the data without having to go to main memory [7]. To determine the effectiveness of cache there are terms referred to as cache hit and miss ratio. The cache hit ratio is a successful attempt to read or write data in the cache divided by the number of times it tried and failed to access data. If the processor reviews the cache for the contents it is looking for and comes up empty handed it goes to main memory for the data. This increases latency and decreases the overall performance of the machine. Contrarily cache miss ratio is equal to 1 Hit Ratio [7]. The following sections go further in depth to the tradeoffs of different cache components, organizations, and hardware types discussed here. Further on, there are various collected data from reference papers to aid in comparing and contrasting for a better analysis of these tradeoffs. A table of comparative specs is listed at the end of this paper. I. LITERATURE REVIEW In the recent decade there has been a great amount of research published about the effectiveness of RAM and edram compared to. This section goes through some of the research implementing newer cache configurations with the nonvolatile RAM and some of the advantages of using edram. The paper Multi Retention Level RAM Cache Designs with a Dynamic Refresh Scheme (11) [8] referenced, dissects the tradeoffs of using RAM on different levels of cache. On one of their baseline platforms the L3 cache uses 4MB of RAM with a 16-way set associativity. The on L has 56KB and 8-way set associativity. The findings of this paper show that their use of RAM on last level caches has been shown to decrease energy consumption and power leakage as well as having an overall smaller area overhead than using technology. Figure shows a read energy average of.77 nj for RAM opposed to.197 nj about.5 times more for tech. Figure 3 shows a comparison of read latency, this shows about the same.5 times higher latency for the opposed to RAM. The improved latency and likely hit rate of the RAM over the can partly be attributed to the higher set associativity. Another reference that analyzed RAM was Cache Revive: Architecting Volatile RAM Caches for Enhanced Performance in CMPs (1) [6]. Again the paper highlights the low power usage, and high density of this type of memory as well as its non-volatile nature but also alludes to the RAMs current issues with write energy consumption/latency. Figures 1 and will give a good idea of how the types of memory reviewed in that paper compare while figure 3 shows a similar read energy consumption of the two. Process Variation Aware Data Management for RAM Cache Design (1) [1] again highlights the effectiveness of STT vs but also gives more information on the geometric cell variations. Variations such as a deviation from the MTJ shape, variation of the thickness of the MgO (Magnesium Oxide) semi-conductor have an effect on the performance of the memory. Both said deviations from the standard MTJ cause variations in switching current of the transistor as well as resistance values of the MTJ itself. RAM cells placed closer together would have smaller difference in write periods than they would if placed further apart. It seems having smaller overhead area may in some cases correlate to increased performance in RAM. Technology Comparison for Large Last-Level Caches (L3Cs): Low- Leakage, Low Write-Energy RAM, and Refresh-Optimized edram (13) [9] touches on the geometry of each type of RAM and how they operate. A section of this paper studies the edram gain cell which is the three MOSFET cell mentioned earlier. The cache had 3MB and was 16-way set associative. This particular cache was pipelined to decrease cycle time and had overall decrease energy consumption. While read latency is neglected in this study (Fig.3) you can see that their edram implementation as well as their other caches have a relatively low power consumption (Fig..) A Coherent Hybrid and RAM L1 Cache Architecture for Shared Memory Multicores (14) [] tries to implement a hybrid cache configuration consisting of both and RAM on L1. The cache design lowers the impact RAM has on write latency at the same time having a reduced power consumption. Where the RAM falls short the standard L1 takes over. This is called MESI protocol and ends up helping to reduce memory that may be stored in multiple caches. This is another power saving configuration because it helps increase the use of cache rather than going to main memory. Page of 5

3 As mentioned earlier and shown in Fig. 1. edram based cache usually has a smaller area overhead partially due to its memory cell having less components than an cell. Because cells are being placed closer and closer together there are more instances of soft errors or disruption of data. Cells that are closer together have a greater chance to be interrupted if a little bit too much charge passes through. The reference paper Bit-Upset Vulnerability Factor for edram Last Level Cache Immunity Analysis (16) [] attempts to reduce soft errors that come from attempts at decreasing the energy and area overhead footprint. The cache configuration in AOS: Adaptive Overwrite Scheme for Energy-Efficient MLC RAM Cache (16) [3] chose to use 8-way set associative mapping for both 3KB of and 4MB of RAM. The goal of the research was to mitigate energy consumed by an MLC (Multi-Level Cell) RAM type. The Figure graph shows a comparatively lower read energy consumption for the RAM at.16 nj. More research revealed from Read-Tuned RAM and edram Cache Hierarchies for Throughput and Energy Enhancement (16) [4] a technique aimed to reduce L miss ratio by more than 5% and IPC (instructions per clock) by about 1%. These are accomplished partly by the use of the nonvolatile RAM to store cache blocks of memory for long term memory while keeping energy low while maintaining a similar read latency to that of device tech. II. DATA ANALYSIS Data from various reference papers was collected and compared in a few plots for analysis. Below is a chart that compares the area overhead (mm ) by each type of memory. The data trends towards a larger sized, smaller edram, and a smaller sized RAM. Fig.. Comparison of the read energy in nanojoules per 4 MB of memory. Below shows figure 3. Which is a plot of the instructions per clock (IPC) found in a few different types of memory. Figure 3. below is a plot of the L cache read latency in nanoseconds. The general trend shows that the types of memory used at L did not have a major impact on read time. nanoseconds nanojoules Read Energy / 4MB L/L3 Cache(nJ) [8] 11 [6] 1 [9] 13 [3] 16 [4] 16 STT Read Read edram Read L Cache Read Latency(ns) [8] [6] 1 [9] 13 [4] 16 STT edram 3 Area overhead in mm per 1MB Fig. 3. Comparison of L cache read latency time in nanoseconds per type of memory. mm 1 [6] 1 [9] 13 [3] 16 [4] 16 [11] 16 STT edram Fig. 1. Comparison of physical area of memory types. Figure. shows a plot of the read energy expended per four MB of L and L3 cache technology. As shown there is no real reliable trend to find because of the nature of the content the reference papers were comparing as mentioned earlier in the Literature Review section. III. CONCLUSION Research has concluded that the CPU requires a much faster and energy efficient way to access memory. On chip cache is the alternative and has been the go to technology for years now. Cache device tech may be heading away from the physically larger and less power efficient, and heading towards more dense, non-volatile RAM as well as edram for certain cases. There are many trends to support why although RAM may have its issues with write latency, overall it is the better option when compared to the standard. REFERENCES [] N. Khoshavi, X. Chen, J. Wang and R. F. DeMara, Bit-Upset Vulnerability Factor for edram Last Level Cache Immunity Analysis, Proceedings of 17th International Symposium on Quality Electronic Design (ISQED 16), Santa Clara, CA, USA, March 15-16, 16. Page 3 of 5

4 [3] X. Chen, N. Khoshavi, J. Zhou, D. Huang, R. F. DeMara, J. Wang, W. Wen and Y. Chen, AOS: Adaptive Overwrite Scheme for Energy- Efficient MLC RAM Cache, 53rd Design Automation Conference, Austing, TX, USA, 16. [4] N. Khoshavi, X. Chen, J. Wang and R. F. DeMara, "Read-Tuned RAM and edram Cache Hierarchies for Throughput and Energy Enhancement, arxiv preprint, 16. [6] A. Jog, A. K. Mishra, C. Xu, Y. Xie, V. Narayanan, R. Iyer, and C. R. Das, Cache Revive: Architecting Volatile RAM Caches for Enhanced Performance in CMPs, in Proceedings of 49th Annual Design Automation Conference (DAC). 1, pp [8] Z. Sun, X. Bi, H. H. Li, W.-F. Wong, Z.-L. Ong, X. Zhu, and W. Wu, Multi Retention Level RAM Cache Designs with a Dynamic Refresh Scheme, in Proceedings of 44th annual IEEE/ACM International Symposium on Microarchitecture. 11, pp [9] M.-T. Chang, P. Rosenfeld, S.-L. Lu, and B. Jacob, Technology Comparison for Large Last-level Caches (L 3 Cs): Low-leakage, Low Write-energy RAM, and Refresh-optimized edram, in Proceedings of 19th International Symposium on High Performance Computer Architecture (HPCA), 13, pp [1] Z. Sun, X. Bi, and H. Li, Process variation aware data management for stt-ram cache design, in Proceedings of the 1 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED, 1, pp [11] M. R. Jokar, M. Arjomand, and H. Sarbazi-Azad, Sequoia: High- Endurance NVM-Based Cache Architecture, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 16. [] Wang, Jianxing, et al. "A coherent hybrid and RAM L1 cache architecture for shared memory multicores." 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 14. [6] Mao, Mengjie, et al. "Coordinating prefetching and RAM based lastlevel cache management for multicore systems." Proceedings of the 3rd ACM international conference on Great lakes symposium on VLSI, 13. [7] CPU cache. (n.d.). Retrieved July 6, 16, from Page 4 of 5

5 TABLE I. TABLE OF COMPARABLE DEVICE SPECS Parameters for Processor the below techniques # of Freq. Capacity cores Khoshavi [] 16 Sun [8] 11 Chen [3] GHz A.Jog [6] 1 Mao [6] 13 Chang[9] 13 Z. Sun [1] 1 M.R. Jokar [11] 16 N. Khoshavi [4] 16 Wang [] 14 Level 1 (L1) for Instruction (I) or Data (D) Level (L) Level 3 (L3) or Last Level Cache (LLC) # of CL Protocol Capacity # of CL Protocol Capacity # of CL Protocol 8 3GHz 3KB 8-way 51 MESI 51KB 8-way 819 MESI 96MB 16-way edram ~1M WB 4 GHz 3KB 4-way 51 N/A 56KB 8-way 496 N/A 4MB 16-way RAM N/A 3KB 8-way 51 WB 4MB 8-way WB N/A N/A N/A N/A N/A 4 GHz 3KB 4-way 51 WB 4MB 16-way N/A N/A N/A N/A N/A N/A 4 4GHz 3KB 4-way N/A 51 WB 56KB 8-way N/A 496 WB 8MB 16-way 1317 WB RAM 8 GHz 3KB 8-way 51 MESI 56KB 8-way 496 MESI 3MB 16-way N/A ~33M WB 8 GHz 16KB -way 56 WT 8MB 3-way 1317 WB N/A N/A N/A N/A N/A 4 3GHz 3KB 8-way DRAM 51 WB MB 8-way 9715 WB 8MB 8-way ReRAM 1317 WB 3.GHz 3KB 8-way 51 WB 51KB 8-way N/A 819 WB 96MB 16-way edram ~1M WB 4 3 GHz 64KB 4-way 14 MESI MB 16-way MESI 9715 N/A N/A N/A N/A N/A N/A Page 5 of 5