Cascaded Channel Model, Analysis, and Hybrid Decoding for Spin-Torque Transfer Magnetic Random Access Memory (STT-MRAM)

Transcription

1 1/16 Cascaded Channel Model, Analysis, and Hybrid Decoding for Spin-Torque Transfer Magnetic Random Access Memory (STT-MRAM) Kui Cai 1, K.A.S Immink 2, and Zhen Mei 1 Advanced Coding and Signal Processing Lab 1 Singapore University of Technology and Design (SUTD) 2 Turing Machine Corporation, Netherlands 9TH ANNUAL NON-VOLATILE MEMORIES WORKSHOP, UCSD, MARCH 2018

2 Introduction of STT-MRAM 2/16 A promising emerging non-volatile memory (NVM) technology Non-volatility High endurance Good scalability magnetic tunneling junction High write/read speed (MTJ) Low power consumption 1->0 0->1

3 Major Technical Challenges 3/16 Process variation & thermal fluctuation result in the simultaneous existence of 3 types of errors Write errors Process variation induced variation of the MTJ geometry and nmos transistor size => widened distribution of the switching current threshold & variation of the transistor driving current Thermal fluctuation => switching is probabilistic The write error rate for 0->1 switching (P 1 ), is much higher than that for 1->0 switching (P 0 ) Read disturb errors Accidental flipping of MTJ during read (P r ) Caused by a large read current due to process variation or thermal fluctuation Read decision errors Fail to differentiate the two resistance states due to widened resistance distributions Caused by process variation induced variations of the tunneling oxide thickness and cross-section area, the tunneling oxide imperfection and the interfacial scattering effect probability density function Block schematic of MTJ switching current distribution MTJ switching current

4 Modeling of STT-MRAM Memory physics based modeling [1] Modeling of switching current distributions Analytical approach to compute J c using macrospin model Statistical approach to compute MTJ switching current distributions Modeling of magnetization dynamical switching using LLG equations Switching current vs switching time Modeling of NMOS transistors Generates MTJ driving current distributions for given NMOS parameters at a specific technology node Modeling of static resistance distributions Statistical model to estimate distributions due to parametric variations Quantum tunneling model: interface imperfections; oxygen vacancy defects in MgO Memory circuit level modeling Compact models [2] [1] B. Chen, K. Cai, G.C. Han, S.T. Lim, and M. Tran, A portable dynamic switching model for perpendicular magnetic tunnel junctions considering both thermal and process variations, IEEE Trans. Magnetic, vol. 51, no. 11, Article #: , Nov [2] W. Guo et al., SPICE modelling of magnetic tunnel junctions written by spin-transfer torque, J. Phys. D, Appl. Phys., vol. 43, no. 21, pp , /16

5 The Cascaded BAC and GMC Channel Model We propose a new class of binary-input, asymmetric, and memoryless channel model, the cascaded binary asymmetric channel (BAC) and Gaussian mixture channel (GMC) model [3] A communication type of channel model The combined model of the write error and read disturb error [3] K. Cai and K.A.S Immink, Cascaded Channel Model, Analysis, and Hybrid Decoding for Spin-Torque Transfer Magnetic Random Access Memory (STT-MRAM), IEEE Trans. Magnetics, vol. 53, no. 11, Article #: , Nov /16

6 The Cascaded BAC and GMC Channel Model 6/16 Cascaded Binary Asymmetric Channel (BAC) and Gaussian Mixture Channel (GMC) Model Significantly improves the memory array error rate simulation speed Facilitates the theoretical design and analysis of the memory sensing and error correction coding schemes for STT-MRAM

7 Channel Raw Bit Error Rate (BER) 7/16 Channel raw bit error rate (BER) analysis Dominant error events distributions

8 Soft-Output Channel Detection Algorithm 8/16 Soft-output detector for the cascaded BAC-GMC channel

9 The Maximum Likelihood (ML) Decision Criterion 9/16 Optimum decoding for the cascaded BAC-GMC channel

10 Extended Hamming Codes with Hybrid Decoding The state of the art ECCs for STT-MRAM Everspin s 16Mb MRAM: (71, 64) Hamming code [4] TDK-Headway s 8Mb STT-MRAM test chip (2017): 2-bit ECC [5] As an example, we adopt an extended Hamming code (72, 64) extended Hamming code We first propose a modified Chase decoder with ML metric for STT-MRAM We further present a two-stage hybrid decoder Hard decision-decoding Yes Successful error correction? No Modified Chase decoding Exit [4] [5] 10/16

11 Simulation Results 11/16 FER P 1 = w/o ECC 2 (71,64) code, HDD 3 (71, 64) code, Chase, Cascaded ML metric 4 (71, 64) code, Hybrid 5 (72, 64) code, HDD 6 (72, 64) code, Chase, SED metric 7 (72, 64) code, Chase, GMC ML metric 8 (72, 64) code, Chase, Cascaded ML metric 9 (72, 64) code, Hybrid / 0 0 (%) Chase decoder with ML metric performs significantly better than both the hard-decision decoder (HDD) and Chase decoder with the conventional metric The two-stage hybrid decoder achieves similar performance with the full Chase decoder The (72, 64) code with hybrid decoding performs significantly better than (71, 64) code with hybrid decoding The hybrid decoder can greatly improve the system s tolerance to the process variation (2% more), in the presence of write errors

12 Simulation Results (contd.) 12/16 FER w/o ECC 2 (71,64) code, HDD 3 (71, 64) code, Chase, BAC-GMC ML metric 4 (71, 64) code, Hybrid 5 (72, 64) code, HDD 6 (72, 64) code, Chase, SED metric 7 (72, 64) code, Chase, GMC ML metric 8 (72, 64) code, Chase, BAC-GMC ML metric 9 (72, 64) code, Hybrid P 1 There is a high error floor at FER = , for the HDDs of both the (71,64) code and (72, 64) code. This means the system will never work with the HDD, no matter how small the write error rate P 1 is The hybrid decoder of the (71, 64) code only slightly lower the error floor. The (72, 64) code with hybrid decoding overcomes the high error floor with the HDD, and improves the maximum affordable write error rate The hybrid decoder can greatly improve the system tolerance to the write errors, irrespective of the resistance spread.

13 Decoding Latency Analysis 13/16 Computational complexity analysis of the full-chase decoder Latency of the hybrid decoder The decoding latency of the hybrid decoder is just 0.11% higher than the hard-decision decoder

14 Conclusions 14/16 We have proposed the cascaded BAC-GMC model, a new communication type of channel model for STT-MRAM To significantly improve the memory array error rate simulation speed To facilitate the theoretical design and analysis of the memory sensing and error correction coding schemes for STT-MRAM We have derived for the cascaded BAC-GMC channel The channel raw BERs The bit LLR The ML decision criterion As an example, we present a hybrid decoding algorithm for extended Hamming codes for the cascaded channel The hybrid decoding algorithm can significantly improve the system s tolerance to both the write errors and the read errors, with little increase of the decoding latency over the HDD It can also be directly applied to other extended BCH codes, for the applications of NVMs with relaxed requirement on the decoding latency

15 Subsequent Work 15/16 Polar coding for STT-MRAM Accepted by Intermag 2018 Dynamic threshold detection based on pearson distance detection Accepted by IEEE Trans. Commun.

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