Chapter Seven. Idea: create powerful computers by connecting many smaller ones

Transcription

1 Chapter Seven Multiprocessors Idea: create powerful computers by connecting many smaller ones good news: works for timesharing (better than supercomputer) vector processing may be coming back bad news: its really hard to write good concurrent programs many commercial failures Cache Cache Cache Cache Cache Cache Single bus ory ory ory ory I/O Network 2

2 Uniprocessor Performance (SCint) X Performance (vs. VX-/780) From Hennessy and Patterson, Computer rchitecture: Quantitative pproach, 4th edition, %/year 52%/year??%/year VX : 25%/year 978 to 986 RISC + x86: 52%/year 986 to 2002 RISC + x86:??%/year 2002 to present 3 Flynn s Taxonomy M.J. Flynn, "Very High-Speed Computers", Proc. of the IEEE, V 54, , Dec Flynn classified by data and control streams in 966 Single Instruction Single Data (SISD) (Uniprocessor) Single Instruction Multiple Data SIMD (single PC: Vector, CM-2) Multiple Instruction Single Data (MISD) (????) Multiple Instruction Multiple Data MIMD (Clusters, SMP servers) SIMD Data Level Parallelism Flexible: N pgms and multithreaded pgm Cost-effective: same MPU in desktop & MIMD 4

3 SIMD s Control Single control unit Multiple datapaths (processing elements s) running in parallel s are interconnected (usually via a mesh or torus) and exchange/share data as directed by the control unit Each performs the same operation on its own local data 5 Example SIMD Machines Maker Year # s # b/ Max memory (MB) clock (MHz) System BW (MB/s) Illiac IV UIUC ,560 DP ICL 980 4, ,560 MPP Goodyear 982 6, ,480 CM-2 Thinking Machines , ,384 MP-26 MasPar 989 6, ,000 6

4 MIMD: Centralized vs. Distributed ory Scale P Pn P P n Interconnection network Interconnection network Centralized ory Distributed ory 7 MIMD: Shared ory or Message-Passing. Communication occurs by explicitly passing messages among the processors: message-passing multiprocessors 2. Communication occurs through a shared address space (via loads and stores): shared memory multiprocessors either UM (Uniform ory ccess time) for shared address, centralized memory MP NUM (Non Uniform ory ccess time multiprocessor) for shared address, distributed memory MP 8

5 MIMD: Centralized vs. Distributed ory Scale P Pn P P n Interconnection network Interconnection network Centralized ory: shared memory (UM or Symmetric MP (SMP) Distributed ory: Message-passing or shared memory (NUM) 7.3 Multiprocessors connected by a single bus 7.4 Clusters & Multiprocessors connected by a network 7.8 Network topologies 9 Supercomputer Style Migration (Top500) Clusters Constellations SIMDs MPPs SMPs Uniproc's Cluster whole computers interconnected using their I/O bus Constellation a cluster that uses an SMP multiprocessor as the building block In the last 8 years uniprocessor and SIMDs disappeared while Clusters and Constellations grew from 3% to 80% 0

6 7.3 Multiprocessors Connected by a Single Bus Cache Cache Cache Single Bus ory I/O Caches are used to reduce latency and to lower bus traffic Must provide hardware to ensure that caches and memory are consistent (cache coherency) Must provide a hardware mechanism to support process synchronization Central memory, shared memory architecture Inexpensive microprocessors with large cache motivate small-scale multiprocessors However, caching of a shared data makes trouble What happens when a program running in processor loads data from a memory location that was written (into cache) by processor 2? Snooping: Cache-coherence protocols track the state of any sharing of a data block to maintain coherent caches 2

7 Example Cache Coherence Problem P P 2 P 3 u =? u =? 4 5 u :5 u :5 3 u= 7 u:5 2 I/O devices ory s see different values for u after event 3 With write back caches, value written back to memory depends on happenstance of which cache flushes or writes back value when Processes accessing main memory may see very stale value Unacceptable for programming, and its frequent! 3 Cache coherency protocol: Snooping Bus snooping cache controllers monitor shared bus traffic with duplicate address tag hardware (so they don t interfere with processor s access to the cache) Proc Proc2 ProcN Snoop DCache Snoop DCache Snoop DCache Single Bus ory I/O 4

8 Bus Snooping Protocols Multiple copies are not a problem when reading must have exclusive access to write a word ll other processors sharing that data must be informed of writes 5 Handling Writes Ensuring that all other processors sharing data are informed of writes can be handled two ways:. Write-update (write-broadcast) writing processor broadcasts new data over the bus, all copies are updated ll writes go to the bus higher bus traffic Since new values appear in caches sooner, can reduce latency 2. Write-invalidate writing processor issues invalidation signal on bus, cache snoops check to see if they have a copy of the data, if so they invalidate their cache block containing the word (this allows multiple readers but only one writer) Uses the bus only on the first write lower bus traffic, so better use of bus bandwidth 6

9 Example: Write-invalidate P P 2 P 3 u =? u =? u :5 u :5 u= 7 u:5 u = 7 2 I/O devices ory Must invalidate before step 3 Write update uses more broadcast medium BW all recent MPUs use write invalidate 7 Example Write-invalidate Snoopy Protocol Invalidation protocol, write-back cache Snoops every address If it has a dirty copy of requested block, provides that block in response to the read request and aborts the memory access Each memory block is in one state: Clean in all caches and up-to-date in memory (Shared) OR Dirty in exactly one cache (Exclusive) OR Not in any caches Each cache block is in one state (track these): Shared : block can be read OR Exclusive : cache has only copy, its writeable, and dirty OR Invalid : block contains no data (in uniprocessor cache too) Read misses: cause all caches to snoop bus Writes to clean blocks are treated as misses 8

10 State Machine CPU Requests CPU Read hit State machine for CPU requests for each cache block Non-resident blocks invalid Invalid CPU Read Shared (read/only) CPU Write Place Write Miss Cache Block State CPU read hit CPU write hit Exclusive (read/write) CPU Write Place Write Miss on Bus 9 State Machine - Block-replacement State machine for CPU requests for each cache block Invalid Shared (read/only) CPU read miss Write back block, CPU Read miss Cache Block State Exclusive (read/write) CPU Write Miss Write back cache block Place write miss 20

11 State Machine ll CPU Requests CPU Read hit State machine for CPU requests for each cache block Invalid CPU Read Shared (read/only) Cache Block State CPU Write Place Write Miss CPU read hit CPU write hit Exclusive (read/write) CPU read miss Write back block, CPU Write CPU Read miss Place Write Miss on Bus CPU Write Miss Write back cache block Place write miss 2 State Machine - Bus Request State machine for bus requests for each cache block Invalid Write miss for this block Shared (read/only) Write miss for this block Write Back Block; (abort memory access) Exclusive (read/write) Read miss for this block Write Back Block; (abort memory access) 22

12 State Machine - Summary CPU Read hit Write miss for this block Write Back Block; (abort memory access) Invalid CPU Write Place Write Miss Write miss for this block CPU Read Shared (read/only) Read miss for this block CPU Read miss CPU read miss Write back block, CPU read hit CPU write hit Exclusive (read/write) CPU Write Place Write Miss on Bus Write Back Block; (abort memory access) CPU Write Miss Write back cache block Place write miss 23 Write-Invalidate CC Examples I = invalid, S = shared, E = exclusive (only one). Read hit for Proc Proc 2 2. Reads E I Main 24

13 Write-Invalidate CC Examples I = invalid, S = shared, E = exclusive (only one). Read hit for Proc Proc 2 2. Reads E I Main 3. Snoop sees read. Read miss for request for, writes-back Proc to Proc 2 4. Gets from MM MM & changes its 5. Changes its E Istate to S state to S 2. read request for Main 25 Write-Invalidate CC Examples I = invalid, S = shared, E = exclusive (only one). Read hit for Proc Proc 2 Proc 2. Reads 4. change E I state to IS. Write hit for Proc 2 2. Writes & changes its state S to E Main 3. Snoop sees read. Read miss for request for, writes-back Proc to Proc 2 4. Gets from MM MM & changes its 5. Changes its E Istate to S state to S 2. read request for Main 3. P2 sends invalidate for Main 26

14 Write-Invalidate CC Examples I = invalid, S = shared, E = exclusive (only one). Read hit for Proc 2. Reads E Proc 2 I Proc 4. change state to IS. Write hit for Proc 2 2. Writes & changes its state S to E 3. P2 sends invalidate for Main Main. Write miss for 2 3. Snoop sees read. Read miss for Proc Proc 2. Writes-back 2 request for, writes-back Proc to Proc 2 4. Gets from to MM MM MM & changes its I E 4. Gets 2 from 5. Changes its E Istate to S MM & changes its state to S 3. Read request state to E 2. read request for for 2Main Main 27 Other Coherence Protocols There are many variations on cache coherence protocols nother write-invalidate protocol used in the Pentium 4 (and many other micro s) is MESI with four states: Modified same Exclusive only one copy of the shared data is allowed to be cached; memory has an up-to-date copy Since there is only one copy of the block, write hits don t need to send invalidate signal Shared multiple copies of the shared data may be cached (i.e., data permitted to be cached with more than one processor); memory has an up-to-date copy Invalid same 28

15 MESI Cache Coherency Protocol shared read nother processor has read/write miss for this block Invalid (not valid block) [Write back block] Modified (dirty) write or read hit write miss Invalidate for this block write [Write back block] [Write back block] shared read miss [Send invalidate signal] exclusive read miss exclusive read miss Shared (clean) shared read Exclusive (clean) exclusive read exclusive read 29