DNNBuilder: an Automated Tool for Building High-Performance DNN Hardware Accelerators for FPGAs
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1 IBM Research AI Systems Day DNNBuilder: an Automated Tool for Building High-Performance DNN Hardware Accelerators for FPGAs Xiaofan Zhang 1, Junsong Wang 2, Chao Zhu 2, Yonghua Lin 2, Jinjun Xiong 3, Wen-mei Hwu 1, Deming Chen 1 1 UIUC, 2 IBM Research-China, 3 IBM T. J. Watson Research Center ICCAD 18 Best Paper Award
2 Outline: 1. Background 2. Motivations 3. Automation Flow 4. Accelerator Architecture 5. Design Space Exploration 6. Experimental Results 7. Conclusions 2
3 Background Deploying deep learning workloads in the cloud Major requirements: Throughput performance Tail latency Power efficiency DNN Design Recommendations Auto-gen Sport Highlights 3
4 Background Deploying deep learning workloads at the edge Major requirements: Real-time ability Energy efficiency design Area constraint 4
5 Outline: 1. Background 2. Motivations 3. Automation Flow 4. Accelerator Architecture 5. Design Space Exploration 6. Experimental Results 7. Conclusions 5
6 Motivation Try FPGAs for both cloud- and edge-computing But.. FPGAs deliver improved latency & energy efficiency (vs. CPUs, GPUs) FPGA have limited computation & memory resources (DSPs, BRAMs) Large design & test efforts (RTL programming, HW verification ) Challenges in resource allocation for unbalanced DNN layers We need An end-to-end automated tool for mapping DNN to FPGAs 6
7 Outline: 1. Background 2. Motivations 3. Automation Flow 4. Accelerator Architecture 5. Design Space Exploration 6. Experimental Results 7. Conclusions 7
8 Automation Design Flow 3-step-solution as Design, Generation, & Execution To bridge the gap between fast DNN construction in software and slow hardware implementation Low latency High throughput Efficient use of FPGA on-chip memory Auto on-chip resource allocation 8
9 Outline: 1. Background 2. Motivations 3. Automation Flow 4. Accelerator Architecture 5. Design Space Exploration 6. Experimental Results 7. Conclusions 9
10 Architecture Overview of the proposed accelerator design A fine-grained layer-based pipeline structure 1) Higher throughput 2) Better support of streaming inputs 3) Higher efficiency with dedicated design for each DNN layer A column-based cache scheme 1) Lower latency, lower on-chip MEM demands 2) Support HD input 3) Real-time capability 10
11 Architecture A fine-grained layer-based pipelined architecture Reduce 7.7x latency for running YOLO Proposed design Higher throughput vs. recurrent structure Lower latency vs. conventional pipeline structure General design 11
12 Architecture Pipelined stages instantiated on FPGA External memory (DRAM) On-chip memory (BRAM) Computation resources 2-dim parallelism KPF - kernel parallel factor CPF - channel parallel factor Arbitrary quantization DW - bit-width for feature map WW - bit-width for weight/bias 12
13 Architecture RTL IPs for different DNN layers Adjustable parallel factor = CPF x KPF (more/less DSP utilization) On-chip buffers for sufficient data supply 13
14 Architecture A column-based cache scheme Save on-chip memory Adjust data reuse factor 1 2 For example: Kernel size = 3 Stride = 1 4 slices cache on-chip instead of keeping the whole feature maps 14
15 Architecture Column-based cache scheme Reduce 43x BRAM usage for running YOLO BRAM usage reduction for keep feature maps 320x ~ 7x 43x on average 15
16 Outline: 1. Background 2. Motivations 3. Automation Flow 4. Accelerator Architecture 5. Design Space Exploration 6. Experimental Results 7. Conclusions 16
17 Design Space Exploration An automatic resource allocator Step1: Computation allocation Total BW 10 GB/S;Total capability: 100 GOPS FC Conv3 Conv1 Conv4 Conv5 Conv2 Conv1 -> 15 GOPS Conv2 -> 15 GOPS Conv3 -> 21 GOPS Conv4 -> 8 GOPS Conv5 -> 5 GOPS FC layer maximum usage 5GOPS CTC: Mem. bound Comp. bound 17
18 Design Space Exploration An automatic resource allocator Step2: memory bandwidth adjustment To meet the BW constraint Total capability 100 GOPS Total BW 10 GB/S Conv3 CTC increase Required mem. BW drop CTC: Col. 1 Mem. bound Comp. bound Col. 2 Cache one more Col. 18
19 Outline: 1. Background 2. Motivations 3. Automation Flow 4. Accelerator Architecture 5. Design Space Exploration 6. Experimental Results 7. Conclusions 19
20 Experimental Results Case study: real-time pedestrian/cyclist/car detection Yolo9000 with HD input (1280x384, 20FPS) is mapped to Xilinx Zynq MHz 20
21 Experimental Results Case study: real-time pedestrian/cyclist/car detection 21
22 Experimental Results Accuracy results after 16-bit & 8-bit quantization *f.-t. in Design represents the accuracy results are collected after retraining and fine-tuning 22
23 Experimental Results Comparison:Embedded FPGAs for edge-devices Zynq XC7Z045 LUT: 218,600 FF: 437,200 BRAM: 545 DSP: 900 Peaking at 524 GOPS Comparison:High-performance FPGAs for cloud computing KU115 LUT: 663,360 FF: 1,326,720 BRAM: 2160 DSP: 5520 Peaking at 4022 GOPS 23
24 Experimental Results Comparison:AlexNet inference performance GPU vs FPGA 24
25 Outline: 1. Background 2. Motivations 3. Automation Flow 4. Accelerator Architecture 5. Design Space Exploration 6. Experimental Results 7. Conclusions 25
26 Conclusions We presented DNNBuilder for building DNN accelerator on FPGAs 1) an automation tool (Design, Generation, and Execution) 2) a fine-grained layer-based pipeline architecture 3) a column-based cache scheme 4) an automatic resource allocation algorithm We delivered the state-of-the-art performance and power efficiency 1) the best throughput: 4022 (KU115) and 524 GOPS (ZC706) 2) the best efficiency: (KU115) and 72.8 GOPS/W (ZC706) 26
27 Q & A #AI Research Week hosted by MIT-IBM Watson AI Lab
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