DRAF: A Low-Power DRAM-based Reconfigurable Acceleration Fabric

Transcription

1 DRAF: A Low-Power DRAM-based Reconfigurable Acceleration Fabric Mingyu Gao, Christina Delimitrou, Dimin Niu, Krishna Malladi, Hongzhong Zheng, Bob Brennan, Christos Kozyrakis ISCA June 22, 2016

2 FPGA-Based Accelerators Improve performance and energy efficiency Good balance between flexibility (CPUs) and efficiency (ASICs) Recently used for many datacenter apps o Image/video processing, websearch, neural networks, Pictures: Putnam, et al. A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services. ISCA 14 2

3 Motivation Deploy FPGAs in cost & power constrained systems Datacenter systems o High-density FPGAs for large accelerators for multiple apps o Low-power FPGAs to simplify integration in servers and racks Mobile systems o High-density FPGAs for accelerators for multiple apps o Low-power FPGAs for low cost and long battery life 3

4 DRAF in a Nutshell A high-density & low-power FPGA o Bit-level reconfigurable, just like conventional FPGAs Uses dense DRAM technology for lookup tables o Replacing the SRAM technology in conventional FPGAs DRAF vs. FPGA o x logic density o 1/3 power consumption o Multi-context support with fast context switch 4

5 Challenges of Building DRAM-based FPGAs 5

6 bitline Row decoder DRAM Array Structure Master wordline Input Local wordline MAT Sense-amp Output Subarray A DRAM subarray is naturally a lookup-table 6

7 bitline Row decoder Challenges ns delay Local wordline Master wordline ~1k rows ~10-bit input MAT Sense-amp Mismatch LUT size a 8192-bit LUT? Slow speed a LUT with 10 ns delay? ~8k-bit output Destructive access data lost after access? 7

8 Destructive Access Explicit activation, restoration, and precharge operations o Longer access delay due to serialization Issue of LUT chaining: order of LUT access L1 L2 Must activate L2 after L1 R1 L4 R2 Physical Path L3 Must activate L4 after both L2 & L3 User Clock 8

9 DRAF Architecture Basic Logic Element Multi-Context Support Timing 9

10 DRAF Overview Same island layout and configurable interconnect as FPGA CLB Contains multiple basic logic elements (BLEs) DSP In DRAM technology Slower but not critical Block RAM Uses DRAM arrays 10

11 bitline Row decoder Basic Logic Element Local wordline Master wordline 7-10 bits input 2-4 bits output x2 MAT Sense-amp Col logic 4x2 Subarray Narrower MAT 1k bits to 8-16 bits Specialized column logic Better flexibility 3 FFs 4 4 Additional FFs & MUXs Registering & retiming 4 Single-MAT access Multi-context 11

12 Multi-Context Support DRAF supports 8-16 contexts per chip o Context: one MAT per BLE o Efficient use of MATs with little area and power overhead Instant switch between active contexts o Similar to context-switch between processes on CPU Context uses o One context per accelerator design or application o One context per part of a very large accelerator design 12

13 Timing Destructive Access Issue of LUT chaining: order of LUT access Solution: phase similar to critical path finding L1 L2 R1 Phase 0 Phase 1 L4 R2 Physical Path L3 Phase 0 Phase 2 User Clock Phase Timeline Phase 0 Phase 1 Phase 2 13

14 Timing Latency Optimization Issue: precharge and restore delays Solution: 3-way delay overlapping o Hide PRE/RST delays with wire propagation delay Performance gap between DRAF and FPGA reduces from >10x to 2-4x LUT-1 LUT-2 PRE ACT RST Wire PRE ACT RST LUT-1 LUT-2 PRE ACT RST Wire PRE ACT RST Saved delay 14

15 Summary Challenges solutions o Mismatch LUT size multi-context BLE o Destructive access phase-based timing o Slow speed 3-way delay overlapping Other design features (see paper) o Sense-amp as register o Time-multiplexed routing o Handling DRAM Refresh 15

16 Evaluation Area, power, performance against FPGA and CPU 16

17 Methodology Synthesize, place & route with Yosys + VTR CACTI-3DD with 45 nm power and area models Comparisons o 70 mm 2 FPGA based on Xilinx Virtex-6 o 70 mm 2 DRAF device, 8-context o Intel Xeon E multi-core processor (2.3 GHz) 18 accelerator designs o MachSuite, Sirius, Vivado HLS Video Library, VTR benchsuite o Web service, image processing, analytics, neural networks, 17

18 Chip Area (mm2) Peak Chip Power (W) DRAF Chip Area & Power 10x area improvement 50x peak power reduction FPGA DRAF FPGA DRAF 0.01 Logic Capacity (in million 6-LUT equivalents) 0.01 Logic Capacity (in million 6-LUT equivalents) 18

19 Normalized Min Bounding Area FPGA vs. DRAF (Area) 8-context DRAF occupies 19% less area than 1-context FPGA o 10x area efficiency: 8 designs in less silicon area than 1 design before o But only one context can be active at a time exp/log functions Inefficient use of larger DRAM LUT aes backprop gemm gmm harris stemmer stencil viterbi editdist FPGA Logic FPGA Routing DRAF Logic DRAF Routing 19

20 Normalized Power FPGA vs. DRAF (Power) Use one context in DRAF DRAF consumes 1/3 power of FPGA and 15% less energy o Note: current CAD tools are less efficient with DRAF aes backprop gemm gmm harris stemmer stencil viterbi editdist FPGA Logic FPGA Routing DRAF Logic DRAF Routing 20

21 Normalized Throughput Performance DRAF is 2.7x slower than FPGA DRAF is 13.5x faster than CPU, 3.4x faster than ideal 4-core exp/log functions Efficient line buffer aes backprop gemm gmm harris stemmer stencil viterbi CPU 4 CPU FPGA DRAF 21

22 Conclusions DRAF: high-density and low-power reconfigurable fabric o Based on dense DRAM technology o Optimized timing + multi-context support DRAF targets cost and power constrained applications o E.g., datacenters and mobile systems DRAF trades off some performance for area & power efficiency o 10x smaller area, 3x less power, and 2.7x slower than FPGA o Still 13x speedup over Xeon cores 22

23 Thanks! Questions?