EEL 4783: HDL in Digital System Design

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1 EEL 4783: HDL in Digital System Design Lecture 13: Floorplanning Prof. Mingjie Lin

2 Topics Partitioning a design with a floorplan. Performance improvements by constraining the critical path. Floorplanning dangers. Creating an optimal floorplan. Floorplanning the data path Constraining high fan-out logic Shaping the floorplan around built-in FPGA devices Reusability Floorplanning to reduce power dissipation.

3 Standard versus Physical Synthesis Flow

4 Example Three major functional blocks, each of which is assigned to a separate designer. The blocks only interact at specific interfaces that have been predefined by the system designer, who has also defined the timing of these interfaces by means of a timing budget. Because the interfaces have been clearly defined, and most likely all I/O of the functional blocks will be registered, the critical path timing will lie within the blocks themselves.

5 Example Floorplan for Design Partitioning

6 Results The regions in this diagram define the physical area occupied by each block. An FPGA device of this size would normally take many hours to successfully place and route with a blanket sea of gates. With the above partitioning, however, this run time will be dramatically reduced to three smaller (and more manageable) place and route operations. Assuming all interfaces are registered at the boundary, the relatively large gaps between the blocks will not cause timing problems. Besides run time, another benefit to this type of partitioning is that major structural or layout changes in one block need not affect the others. Thus, a methodology that employs design partitioning works in close harmony with an incremental design flow.

7 CRITICAL-PATH FLOORPLANNING Floorplanning is often used by designers who have very difficult timing constraints and need to tighten their critical paths as much as possible. The floorplan in this case would be created after the final implementation results were generated and the critical path was defined. This information would be back-annotated to the floorplanner whereby the designer would manually define location constraints for the critical logic elements. These physical constraints would then be forward annotated into the place and route tool to complete an iterative cycle.

8 Design Flow with Critical Path Floorplanning

9 Example Critical-Path-Floorplan Constraints When floorplanning the critical path, the floorplan is a key link in the iterative timing closure loop.

10 FLOORPLANNING DANGERS The danger in floorplanning is that if done incorrectly, it can dramatically decrease the performance of the implementation. This is because of the fact that good placement directly corresponds with a design that performs well, and bad placement directly corresponds with a design that performs poorly. This may seem like an obvious statement, but a corollary to this is that a bad floorplan will lead to bad placement and will subsequently lead to poor performance. Thus, a floorplan of any type will not have a nondecreasing impact on performance. Rather, a bad floorplan will make things much worse. A bad floorplan can dramatically reduce the performance of a design.

11 What Circuits are for Floorplanning? It is important to note that not all designs lend themselves to floorplanning. Designs that are pipelined and have a very regular data flow, such as with a pipelined microprocessor, clearly lend themselves to floorplanning. Devices that implement primarily control or glue logic or that don t have any definable major data path often do not lend themselves to a good floorplan that is intended to partition the design. If the design is indeed simply a sea of gates, then it would be optimal to allow the synthesis and place and route tools to treat it as such.

12 General Heuristic One general heuristic to determine if a design is a good candidate for critical-path floorplanning is to analyze the routing versus logic delays. If the percentage of a critical path that is consumed in routing delay is the vast majority of the total path delay, then floorplanning may assist in bringing these structures closer together and optimizing the overall routing resources and improving timing performance. If, however, the routing delay does not take up the majority of the critical-path delay and there is no clearly definable data path, then the design may not be a good candidate for floorplanning. Floorplanning is a good fit for highly pipelined designs or for layouts dominated by routing delay. For designs that may lend themselves to a good floorplan, there are a number of considerations that must be taken into account to ensure that the performance will actually be improved.

13 OPTIMAL FLOORPLANNING The optimal floorplan will group logic structures that have direct interconnect in close proximity to one another and will not artificially separate elements that may lie in a critical path. Scenarios Data Path High Fan-Out Device Structure Reusability

14 Data Path A design that is data path centric is often relatively easy to partition. For most high-speed applications, the pipeline to be partitioned will usually apply to the data path. Because the data path carries the processed information and is required to do so at very high speeds (often running continuously), it is recommended to floorplan this first as shown. In this scenario, a floorplan is created to partition the data path only. This includes the main pipeline stages and all associated logic. The control structures and any glue logic that do not lie on the primary data path can be placed automatically by the back-end tools. The floorplan usually includes the data path but not the associated control or glue logic.

15 Data Path

16 High Fan-Out High fan-out nets are often good candidates for floorplanning as they require a large amount of routing resources in one specific region. This requirement often leads to a high degree of congestion if the loads are not placed in a close proximity to the driver as shown. If the loads are located a relatively long distance from the driver, the interconnect will occupy a large amount of routing resource at the output of the driver. This will make other local routes more difficult and correspondingly longer with larger delays. Figure illustrates the benefit of constraining the high fan-out region to a small area. By confining the high fan-out region to a small and localized area, the effects to other routes will be minimized. This will provide faster run times for the place and route tool as well as a higher performance implementation due to the minimization of routing delays.

17 Examples

18 Device Structure The device structure is critical in the floorplan, as built-in structures cannot be moved around with either the floorplan or the placement tools. These built-instructures include memories, DSPs, hard PCI interfaces, hard microprocessors, carry chains, and so forth. It is therefore important not only to floorplan the design such that the blocks are placed optimally relative to one another but also such that built-in structures can be utilized efficiently and that routes to the custom logic are minimized. A floorplan should take into consideration built-in resources such as memories, carry chains, DSPs, and so forth.

19 Example Input and output logic resources are tied to the RAM interface. For a sizable RAM block, it is usually more desirable to use the fixed RAM resources available in certain regions of the FPGA as opposed to an aggregation of smaller RAM elements distributed throughout the FPGA. The constraint for a floorplan on this path would then be dependent on the fixed location of the RAM resource as shown.

20 Example

21 Reusability A good floorplan will allow various modules and groups of modules to be reused without a dramatic impact on the performance of those modules. In a sea of gates design, it is common to find that changes to totally unrelated areas of the design can cause timing problems in other aspects of the design. This is due to the progressive nature of an unconstrained place and route algorithm. The chaos effect ensues when a small placement change on one side of the FPGA shifts logic resources over, forcing other local logic structures out of the way, and so on until the entire chip has been replaced with entirely new timing. For a constrained placement via a good floorplan, this is not an issue as the relative timing is fixed for the critical-path modules, and any changes must operate around that floorplan.

22 Reusability The critical logic is constrained inside the floorplan region and will not be affected internally as placement changes around it.

23 REDUCING POWER DISSIPATION We discussed floorplanning in the context of timing performance, organization, and implementation run-time. There is an additional use for floor planning, and that is the reduction of the dynamic power dissipation. Because of the fact that the capacitance of the trace (C trace ) is proportional to the area of the trace, and assuming the width of the trace is fixed for an FPGA routing resource, the capacitance will be proportional to the length of the trace. In other words, the capacitance that the driver must charge and discharge will be proportional to the distance between the driver and the receiver.

24 Dynamic Power In our original discussion on dynamic power dissipation, it was determined that the power dissipated on high-activity lines was proportional to the capacitance of the trace times the frequency. Here, we will assume that the functionality is locked down and the activity on the various traces cannot be changed. Thus, to minimize the power dissipation, we must minimize the routing lengths of high-activity lines. For timing optimization, the place and route tool will place criticalpath components in close proximity to one another in an attempt to achieve timing compliance. The critical path, however, does not indicate anything about high activity/. In fact, a critical path may have a very low toggle rate, whereas a component that easily meets timing such as a free running counter may have a very high toggle rate.

EEL 4783: HDL in Digital System Design

EEL 4783: HDL in Digital System Design Lecture 10: Synthesis Optimization Prof. Mingjie Lin 1 What Can We Do? Trade-offs with speed versus area. Resource sharing for area optimization. Pipelining, retiming,