EEL 4783: HDL in Digital System Design

Transcription

1 EEL 4783: HDL in Digital System Design Lecture 4: HLS Intro* Prof. Mingjie Lin *Notes are drawn from the textbook and the George Constantinides notes 1

2 Course Material Sources 1) Low-Power High-Level Synthesis for Nanoscale CMOS Circuits, Mohanty, S.P., Ranganathan, N., Kougianos, E., Patra, P., ) Giovanni De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994 A good description of most of the topics covered Also covers logic synthesis, not covered in this course 3) Keshab K. Parhi, VLSI Digital Signal Processing Systems, Wiley Interscience, 1999 Useful for retiming, and a slightly different perspective 4) Sabih H. Gerez, Algorithms for VLSI Design Automation, Wiley, Useful for a general overview, and some details on floorplanning 5) M. McFarland, A. Parker, R. Camposano, The High-Level Synthesis of Digital Systems, Proc. IEEE, Vol. 78, No. 2, Feb ) R. Camposano, From Behavior to Structure: High-Level Synthesis, IEEE Design & Test of Computers, October * Some notes are directly drawn from George Constantinides@Imperial College notes 2

3 What is Synthesis? 3

4 A Demonstrative Example 4

5 A Demonstrative Example 5

6 A Demonstrative Example 6

7 A Demonstrative Example 7

8 A Demonstrative Example 8

9 A Demonstrative Example 9

10 A Demonstrative Example 10

11 Scheduling Algorithms The scheduling problem is a non-deterministic polynomial (NP) problem. Behavioral scheduling algorithms may be of various types based on the constraints and optimization schemes 11

12 Why Synthesis? Why not Synthesis? Productivity Performance Loss Correctness Unsynthesizability Re-Targetability Inertial 12

13 Various phases of high-level synthesis 13

14 Compilation 1) The behavior of a system to be synthesized is usually specified at the algorithmic level using a high-level programming language like C/C++ or a hardware description language (HDL) such as VHDL and Verilog. 2) The behavior of the system is then compiled into internal representations, which are usually data flow graphs (DFGs) and control flow graphs (CFGs). 3) Each behavioral specification is transformed into a unique graphical representation. The DFG is a directed graph that represents data movement, whereas the CFG is a directed graph that indicates the sequence of operations. 14

15 Steps for converting VHDL to CDFG 15

16 Graphs and Models 16

17 Graphs and Models 17

18 Data Flow Graphs 18

19 Data Flow Graphs 19

20 Data Flow Graphs and Compilation 20

21 Data Flow Graphs and Parallelism 21

22 Data Flow Graphs 22

23 Control Data Flow Graphs 23

24 Conditionals 24

25 Loops 25

26 Function Calls 26

27 Various phases of high-level synthesis 27

28 Transformation 1) In the transformation step, the initial DFG is transformed so that the resultant DFG is more suitable for scheduling and allocation 2) These transformations include compiler-like optimizations such as dead-code elimination, common subexpression elimination, loop unrolling, constant propagation and code motion 3) In addition, some hardware-specific transformations like minimization of syntactic variances and retiming may be applied to take advantage of the associativity and commutativity of certain operations 28

29 Various phases of high-level synthesis 29

30 Scheduling 1) Scheduling is the process of partitioning the set of arithmetic and logical operations in the DFG into groups so that the operations in the same group can be executed concurrently, while taking into consideration possible trade-offs between the total execution cost and hardware cost 2) A group of concurrent computations to be executed simultaneously is referred to as a control step 3) The total number of control steps needed to execute all operations in the DFG, the minimum number of functional units of each type to be used in the design and the lifetimes of the variables generated during the computation of operations are determined in the scheduling step. 30

31 Various phases of high-level synthesis 31

32 Selection or Allocation 1) Selection is the process of choosing resources from the library, which involves trade-offs according to different features like delay, area, power and leakage 2) Resource allocation is the process of determining the number of functional units of each type for performing operations, memory units (registers) for storing data values and interconnects for data transportation. 3) Often, the selection and allocation processes are a single task. Allocation is further divided into sub-tasks, such as functional unit allocation, memory unit allocation and interconnect allocation. 4) Resource allocation and binding may share resources so that the same hardware can be used to execute different operations or so that the same register can be used to store more than one variable. 32

33 Various phases of high-level synthesis 33

34 Binding or Assignment 1) Binding or assignment is the process of assigning variables to memory units and data transfers to interconnections 2) Binding is further divided into several sub-tasks, such as functional unit binding, memory unit binding and interconnect binding 3) Functional unit binding involves the mapping of operations in the behavioral description into a set of selected functional units 4) Memory unit binding maps data carriers (constants, variables, arrays) in the behavioral description onto storage elements (read-only memories, registers, memory units) in the data path 5) The interconnect binding task maps every data transfer in the behavior onto a set of interconnection units for data routing 34

35 Various phases of high-level synthesis 35

36 Output Generation 1) In the output generation phase, design output is generated 2) The output should be in a form such that logic-level synthesis tools can optimize the combinational logic and layout synthesis tools can design the chip geometry 3) The generated output is generally in a low-level HDL, such as structural VHDL 36

37 Final issues Please fill out the student info sheet before leaving Come by my office hours (right after class) Any questions or concerns? 37