Design Methodologies

Transcription

1 Design Methodologies

2 Complexity Productivity (K) Trans./Staff - Mo. Productivity Trends Logic Transistor per Chip (M) 10, mm 1, mm mm Logic Tr./Chip Tr./Staff Month. x x x x x x x x 58%/Yr. compounded Complexity growth rate 21%/Yr. compound Productivity growth rate 100, ,000,000 10,000 10,000,000 1,000 1,000, , , , Source: Sematech Complexity outpaces design productivity 2

3 INPUT/OUTPUT A Simple Processor MEMORY CONTROL INPUT-OUTPUT DATAPATH 3

4 A System-on-a-Chip: Example 4

5 Energy Efficiency (in MOPS/mW) Hardwired custom Configurable/Parameterizable Domain-specific processor (e.g. DSP) Embedded microprocessor Impact of Implementation Choices None Somewhat flexible Fully flexible Flexibility (or application scope) 5

6 Implementation Choices Digital Circuit Implementation Approaches Custom Semicustom Cell-based Array-based Standard Cells Compiled Cells Macro Cells Pre-diffused (Gate Arrays) Pre-wired (FPGA's) 6

7 The Custom Approach Intel

8 Transition to Automation and Regular Structures Intel 4004 ( 71) Intel 8080 Intel 8085 Intel 8286 Intel

9 Cell-based Design Routing channel requirements are reduced by presence of more interconnect layers Standard Cell Layout methodology 9

10 The Evolution of Standard Cell [Brodersen92] 10

11 Standard Cell The New Generation Cell-structure hidden under interconnect layers 11

12 Standard Cell - Example 3-input NAND cell (from ST Microelectronics): 12

13 Automatic Cell Generation Initial transistor geometries Placed transistors Routed cell Compacted cell Finished cell 13

14 MacroModules (or 8192 bit) SRAM Generated by hard-macro module generator Implemented in 0.18 mm CMOS technology (0.094 mm 2 ) 14

15 Soft MacroModules 8 x 8 Multiplier Synopsys DesignCompiler 15

16 Design Iteration Semicustom Design Flow Pre-Layout Simulation Design Capture HDL Logic Synthesis Behavioral Structural Post-Layout Simulation Circuit Extraction Floorplanning Placement Routing Physical Tape-out 16

17 The Design Closure Problem Iterative Removal of Timing Violations (white lines) Courtesy Synopsys 17

18 Integrating Synthesis with Physical Design RTL (Timing) Constraints Physical Synthesis Macromodules Fixed netlists Netlist with Place-and-Route Info Place-and-Route Optimization Artwork 18

19 Late-Binding Implementation Array-based Pre-diffused (Gate Arrays) Pre-wired (FPGA's) 19

20 Gate Array Sea-of-gates polysilicon In1 In2 In3 In4 V DD metal GND possible contact Out Uncommited Cell Committed Cell (4-input NOR) 20

21 Gate Array Architectures 21

22 Examples of Sea-of-gate Primitive Cells Oxide-isolation PMOS PMOS NMOS NMOS NMOS Using oxide-isolation Using gate-isolation 22

23 Sea-of-gates Random Logic Memory Subsystem LSI Logic LEA300K (0.6 mm CMOS) 23

24 Xilinx FPGA Architecture 24

25 Antifuse-Based FPGA antifuse polysilicon ONO dielectric n + antifuse diffusion 2 l Open by default, closed by applying current pulse 25

26 RAM-based FPGA Xilinx XC4000ex 26

27 Two-Level Logic Every logic function can be expressed in sumof-products format (AND-OR) x 0 x 1 Product terms Inverting format (NOR-NOR) more effective AND plane x 2 OR plane f 0 f 1 x 0 x 1 x 2 27

28 Array-Based Programmable Logic (1) I 3 I 2 I 1 I 0 Programmable OR array Fixed AND array PROM O 3 O 2 O 1 O 0 Indicates programmable connection Indicates fixed connection 28

29 Programming a PROM 1 X 2 X 1 X 0 : programmed node NA NA f 1 f 0 29

30 Array-Based Programmable Logic (2) I 5 I 4 I 3 I 2 I 1 I 0 Programmable OR array Programmable AND array PLA O 1 O 2 O 3 O 0 30

31 Array-Based Programmable Logic (3) I 5 I 4 I 3 I 2 I 1 I 0 Fixed OR array Programmable AND array PAL O 1 O 2 O 3 O 0 Indicates programmable connection Indicates fixed connection 31

32 More Complex PAL i x i inputs, j minterms/macrocell, k macrocells 32

33 PLA Layout Exploiting Regularity V DD And-Plane Or-Plane f GND x 0 x 0 x 1 x 1 x 2 x 2 Pull-up devices f 0 f 1 Pull-up devices 33

34 Cell-Based Programmable Logic A 0 B 1 S 2-input mux as programmable logic block F Configuration A B S F= X 1 X 0 Y 1 Y 0 Y X XY X 0 Y XY Y 0 X XY Y 1 X X + Y 1 0 X X 1 0 Y Y F = A S + B S 34

35 Logic Cell of Actel Fuse-Based FPGA A B 1 SA C 1 Y D 1 SB S0 S1 35

36 Memory Look-up Table Based Logic Cell In Out Out ln1 ln2 Cell schematic XOR function 36

37 LUT-Based Logic Cell Xilinx 4000 Series 37

38 Array-Based Programmable Wiring M Interconnect Point Programmed interconnection Input/output pin Cell Horizontal tracks Vertical tracks 38

39 Mesh-based Interconnect Network Switch Box Connect Box Interconnect Point 39

40 Transistor Implementation of Mesh 40

41 Hierarchical Mesh Network Use overlayed mesh to support longer connections Reduced fanout and reduced resistance 41

42 Prewired Arrays Classification of prewired arrays (or fieldprogrammable devices): Based on Programming Technique Fuse-based (program-once) Non-volatile EPROM based RAM based Programmable Logic Style Array-Based Look-up Table Programmable Interconnect Style Channel-routing Mesh networks 42

43 Analog System-on-a-Chip Multi- Spectral RAM Imager 500 k Gates FPGA + 1 Gbit DRAM Preprocessing 64 SIMD Processor Array + SRAM Image Conditioning 100 GOPS mc system +2 Gbit DRAM Recognition Embedded applications where cost, performance, and energy are the real issues! DSP and control intensive Mixed-mode Combines programmable and application-specific modules Software plays crucial role 43

44 Heterogeneous Programmable Platforms FPGA Fabric Embedded PowerPc Embedded memories Hardwired multipliers High-speed I/O Xilinx Vertex-II Pro 44

45 Berkeley Pleiades Processor Interface FPGA Reconfigurable Data-path ARM8 Core 0.25um 6-level metal CMOS 5.2mm x 6.7mm 1.2 Million transistors 40 MHz at 1V 2 extra supplies: 0.4V, 1.5V 1.5~2 mw power dissipation 45

46 Summary Digital CMOS Design is kicking and healthy Some major challenges down the road caused by Deep Sub-micron Super GHz design Power consumption!!!! Reliability making it work Some new circuit solutions are bound to emerge Who can afford design in the years to come? Some major design methodology change in the making! 46